KR20080017120A - Probe card, method of manufacturing the same and method of testing lcd pannel using the same - Google Patents

Probe card, method of manufacturing the same and method of testing lcd pannel using the same Download PDF

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Publication number
KR20080017120A
KR20080017120A KR1020060078526A KR20060078526A KR20080017120A KR 20080017120 A KR20080017120 A KR 20080017120A KR 1020060078526 A KR1020060078526 A KR 1020060078526A KR 20060078526 A KR20060078526 A KR 20060078526A KR 20080017120 A KR20080017120 A KR 20080017120A
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KR
South Korea
Prior art keywords
axis
line
cell
axis line
electrode
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Application number
KR1020060078526A
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Korean (ko)
Inventor
이재홍
Original Assignee
이재홍
주식회사 나디스
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Priority to KR1020060078526A priority Critical patent/KR20080017120A/en
Publication of KR20080017120A publication Critical patent/KR20080017120A/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • G01R1/07307Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]

Abstract

Probe card of the present invention, the circuit board; An insulating substrate formed on the circuit board; A plurality of X-axis line electrodes arranged in parallel with each other on the insulating substrate; A plurality of Y-axis line electrodes arranged parallel to each other on the X-axis line electrode, spaced apart from the X-axis line electrode line, and connected to the X-axis line electrode through conductive vias formed at the intersections; And a plurality of probe pins formed on the Y-axis line electrode so as to be aligned with the conductive via and in contact with the Y-axis line electrode.

Description

Probe Card, Method of Manufacturing and Method of Testing LCD Panel Using the Same {Probe Card, Method of Manufacturing the Same and Method of Testing LCD Pannel Using the Same}

1 is a plan view and a cross-sectional view showing a conventional probe probe card for LCD panel inspection.

2 is a plan view of a probe card according to an embodiment of the present invention.

3 is a cross-sectional view of the probe card of FIG. 2.

4 is a plan view of a probe card according to another embodiment of the present invention.

5 is a cross-sectional view of the probe card of FIG. 4.

6 to 22 are cross-sectional views and plan views illustrating a method of manufacturing a probe card according to an embodiment of the present invention.

It is a perspective view which shows the principal part of the probe card which concerns on embodiment of this invention.

24 to 26 are schematic diagrams schematically showing a defective state of the cells of the LCD panel under test.

<Description of the symbols for the main parts of the drawings>

100: probe card 101: circuit board

110: insulation substrate 120, 130: insulator layer

115: X-axis line electrode 125: Y-axis line electrode

115a, 115b, 125a, 125b: electrode pad portion

150: probe pin 160: bonding wire

170: conductive via 180, 280: probe

The present invention relates to a probe card, a method for manufacturing the same, and a method for inspecting an LCD panel using a probe card. Particularly, a probe card and a method for manufacturing the same and an LCD panel using the same can be used to effectively and easily inspect a large number of LCD cells at the same time. It is about an inspection method.

In general, in the final stage of the LCD panel manufacturing process, the inspection process using a probe card to check whether there is a defective cell (cell) in the manufactured LCD panel. Probe cards used to inspect cells in LCD panels typically have a ceramic insulating substrate having a plurality of holes and a needle inserted into the hole. Such a probe card is obtained by assembling these parts after manufacturing the individual parts. An LCD card inspection probe card which is currently widely used is shown in FIG. 1.

Referring to FIG. 1, the probe card 10 includes a PCB substrate 11 and a ceramic substrate 15 disposed thereon and having a plurality of holes (holes). The ceramic substrate 15 is disposed on the central portion of the PCB substrate 11, and the needle 17 is inserted into a hole formed in the ceramic substrate 15 so that the needle 17 comes into contact with the inspection object. The lower end of the needle 17 is connected to the wiring 18 formed on the PCB substrate 11, which extends toward the edge of the PCB substrate 18.

In the probe card 10 of this structure, the needle 17 is not only plugged into a minute hole but also concentrated in a ceramic substrate (located at the center of the PCB substrate), thereby limiting the number of LCD cells that can be probed at one time. have. For example, it is very difficult to fabricate a probe card that can inspect cells over 1000 or 10,000 pins at a time. Therefore, a lot of time and effort is required to inspect the LCD panel having many cells using the probe card 10. In addition, even when producing a probe card having 1000 or 10,000 needles or more, it is difficult to accurately locate the defective cell.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a probe card that can effectively inspect a large number of LCD cells at the same time.

Another object of the present invention is to provide a method of manufacturing a probe card that can effectively inspect a large number of LCD cells at the same time.

Yet another object of the present invention is to provide a method for inspecting an LCD panel using the probe card.

In order to achieve the above technical problem, the probe card of the present invention, the circuit board; An insulating substrate formed on the circuit board; A plurality of X-axis line electrodes arranged in parallel with each other on the insulating substrate; A plurality of Y-axis line electrodes arranged parallel to each other on the X-axis line electrode, spaced apart from the X-axis line electrode line, and connected to the X-axis line electrode through conductive vias formed at the intersections; And a plurality of probe pins formed on the Y-axis line electrode so as to be aligned with the conductive via and in contact with the Y-axis line electrode.

According to a preferred embodiment, the X-axis line electrode and the Y-axis line electrode are arranged to be orthogonal to each other. Also preferably, each of the X-axis line electrode and the Y-axis line electrode may include a line portion extending in a straight line and a pad portion formed at one end of the line portion and connected to an external wiring. Preferably, the plurality of x-axis line electrodes are arranged such that the pad portion is alternately arranged at one end and the other end of the line portion. Similarly, preferably, the plurality of Y-axis line electrodes are arranged such that pad portions are alternately arranged at one end and the other end of the line portion.

In order to achieve another object of the present invention, a method of manufacturing a probe card according to the present invention comprises the steps of forming a plurality of X-axis line electrodes arranged in parallel to each other on an insulating substrate; Forming a plurality of conductive vias in contact with the X-axis line electrodes on the plurality of X-axis line electrodes; Forming a plurality of Y-axis line electrodes on the conductive via, the plurality of Y-axis line electrodes arranged in parallel with each other to be in contact with the conductive via and intersect the X-axis line electrode; Forming a plurality of probe pins on the plurality of Y-axis line electrodes that are aligned with the conductive vias and are in contact with the Y-axis line electrodes.

Preferably, the Y-axis line electrode is formed to be orthogonal to the X-axis. Preferably, each of the X-axis line electrode and the Y-axis line electrode is formed to have a line portion extending in a straight line, and a pad portion disposed at one end of the line portion and connected to an external wiring.

Preferably, the plurality of X-axis line electrodes are formed such that the pad portion is alternately disposed at one end and the other end of the line portion. Similarly, preferably, the plurality of Y-axis line electrodes are formed such that the pad portion is alternately arranged at one end and the other end of the line portion.

The X-axis line electrode forming step, the conductive via forming step, the X-axis line electrode forming step, and the probe pin forming step may use a microelectro-mechanical system (MEMS) manufacturing process involving photolithography. It can be executed precisely and easily.

Preferably, the forming of the X-axis line electrode includes: forming a first insulator layer on the insulating substrate; Forming a photoresist pattern having an opening in the shape of an X-axis line electrode on the first insulator layer; Selectively etching the first insulator layer using the photoresist pattern as an etching mask; Depositing a metal layer on the entire surface of the resultant material; Removing the photoresist pattern and the metal layer deposited thereon by a lift-off method.

Preferably, forming the conductive via comprises: forming a second insulator layer on the X-axis electrode line; Forming a photoresist pattern defining a conductive via region on the second insulator layer; Selectively etching the second insulator layer using the photoresist pattern as an etch mask to form via holes in the insulator layer; Depositing a metal layer over the entire surface of the product to fill the via hole; Removing the photoresist pattern and the metal layer deposited thereon by a lift off method.

According to an embodiment, the depositing of the metal layer for filling the via hole may include depositing a first metal on a bottom and an outer surface of the via hole; Thereafter depositing a second metal to fill the inside of the via hole; Thereafter, depositing the first metal again to a predetermined height. Preferably, the first metal is gold (Au), and the second metal is nickel (Ni).

Advantageously, forming the Y-axis line electrode comprises: forming a third insulator layer on the conductive via; Forming a photoresist pattern having an opening in the shape of a Y-axis line electrode on the third insulator layer; Selectively etching the third insulator layer using the photoresist pattern as an etching mask; Depositing a metal layer on the entire surface of the resultant material; Removing the photoresist pattern and the metal layer deposited thereon by a lift off method.

Preferably, the probe pin forming step comprises: forming a fourth insulator layer on the Y-axis line electrode; Forming a photoresist pattern defining a probe pin region on the fourth insulator layer; Selectively etching the fourth insulator layer using the photoresist pattern as an etching mask to form a hole for forming a probe pin; Filling the hole for forming the probe pin with a metal by a plating method; Removing the photoresist pattern.

In order to achieve another object of the present invention, an inspection method of an LCD panel using a probe card of the present invention, the current is applied to the plurality of cells while the probe pin of the probe card in contact with the plurality of cells of the LCD panel. Applying at the same time; Measuring a current flowing through each line electrode of the probe card in the current application state; Identifying an LCD cell line having defective cells through the measurement current; If there is at least one LCD cell line with a defective cell, the step of identifying the location of the defective cell.

Identifying the LCD cell line with the defective cell includes identifying a line electrode exhibiting a lower measurement current than other line electrodes. The LCD cell line corresponding to the line electrode (X-axis or Y-axis) through which a relatively low measurement current flows is determined as a cell line with defective cells. If all line electrodes show the same measurement current, there are no defective cells.

Preferably, the step of determining the location of the defective cells, the defective cells in only one of the X-axis cell lines of the X-axis cell line or the defective cells of only one of the Y-axis cell lines of the Y-axis cell line If it is determined that there is, determining the position of the defective cell at the intersection of the X-axis cell line and the Y-axis cell line having the defective cell; If it is confirmed that there are defective cells in at least two X-axis cell lines and at least two Y-axis cell lines, current is detected at the Y-axis line electrode by applying current to only the X-axis cell lines in which the defective cells exist. Checking the position of the defective cell through.

The determining of the location of the defective cell may include identifying a location of the defective cell by applying a current to only the X-axis cell line where the defective cell is located and by detecting the current at the Y-axis line electrode. . Alternatively, the step of identifying the position of the defective cell, the step of identifying the position of the defective cell through the current detected by the X-axis line electrode by applying a current individually to the Y-axis cell line with the defective cell. It may include.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

2 is a plan view of a probe card according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of the probe card of FIG. 2. 2 and 3, the probe card 100 includes a circuit board 101 such as a PCB and a probe 180 formed thereon. The probe unit 180 connects an insulating substrate 110 such as a glass substrate, a plurality of X-axis line electrodes 115 and Y-axis line electrodes 125, and X-axis and Y-axis line electrodes 115 and 125 to each other. A conductive via 170, and a plurality of probe pins 150 protruding upward. In addition, the conductive via 170 and the probe pin 150 are surrounded by the insulators 120 and 130.

The plurality of X-axis line electrodes 115 are formed on the insulating substrate 110 and arranged in parallel with each other. Each X-axis line electrode 115 has a line portion extending in a straight line and a pad portion 115a formed at one end of the line portion. The pad part 115a may be connected to an external wiring through wire bonding or the like.

The plurality of Y-axis line electrodes 125 are arranged parallel to each other on the X-axis line electrode 115, and are spaced apart from and cross the X-axis line electrode line 115. Preferably, the X-axis line electrode 115 and the Y-axis line electrode 125 are orthogonal to each other, and the spacing between the line electrodes is also the same. Accordingly, when viewed from above, the intersection of the X-axis line electrodes 115 and the Y-axis line electrodes 125 forms an array in a matrix shape. The Y-axis line electrode 125 also has a line portion and a pad portion 125a similarly to the X-axis line electrode 115.

The plurality of X-axis line electrodes 115 are arranged such that the pad portion is arranged as a teaching material at one end and the other end of the line portion. Similarly, the plurality of Y-axis line electrodes 125 are also arranged such that the pad portion is arranged as a teaching material at one end and the other end of the line portion. Such pad part alternation arrangement enables the line electrodes to be arranged more densely.

A conductive via 170 connecting the electrodes is formed between the X-axis line electrode 115 and the Y-axis line electrode. In particular, the conductive via 170 is positioned at the intersection of the X-axis line electrode 115 and the Y-axis line electrode 125 to form a matrix arrangement.

The probe pin 150 is formed on the Y-axis line electrode 125 to be in contact with the Y-axis line electrode 125, and protrudes over the insulator layer 130 so as to contact the terminal of the cell under test. The plurality of probe pins 150 are formed at positions aligned with the conductive vias 170 to form a matrix-like arrangement like the conductive vias 170. The probe pin 150 may have an outer portion 150a made of gold (Au) and an inner portion 150b made of nickel.

As shown in FIGS. 2 and 3, the probe card 100 includes ten X-axis line electrodes and ten Y-axis line electrodes. This allows 100 LCD cells to be tested simultaneously, including 10 x 10 = 100 probe pins.

4 is a plan view of a probe card (in particular, a probe except for a circuit board) according to another embodiment of the present invention, and FIG. 5 is a cross-sectional view thereof. In this embodiment, a larger number of line electrodes are provided. The probe unit 280 includes 20 X-axis line electrodes X1 to X20 and 20 Y-axis line electrodes Y1 to Y20. Thus, 20 × 20 = 100 LCD cells can be inspected at the same time.

However, the present invention is not limited to the above embodiments, and by applying the MEMS fabrication process as described below, the number of line electrodes can be increased by a desired number, and tens of thousands to hundreds of thousands of probe pins can be precisely manufactured. Can be. Therefore, according to the present invention, tens of thousands or more cells can be inspected at the same time. In addition, as will be described later, by using the probe card of the present invention, the position of the defective cell can be easily and accurately confirmed.

Hereinafter, the manufacturing method of the probe card which concerns on embodiment of this invention is demonstrated. The X-axis line electrode, the Y-axis line electrode, the vias, the probe pins, etc. of the probe card can be manufactured precisely and easily by using a MEMS (Micro Electro-Mechanical System) manufacturing process involving a photolithography process as described below. have. Hereinafter, the manufacturing process of the probes 180 and 280 forming the main part of the present invention will be described. The manufactured probe portion is mounted on a circuit board such as a PCB, and then a necessary wiring process such as wire bonding can be performed.

6 to 22 are cross-sectional views and plan views illustrating a method of manufacturing a probe card according to an embodiment of the present invention. In order to manufacture the probe part of a probe card, it progresses in order of an X-axis line electrode formation process, a conductive via formation process, a Y-axis line electrode formation process, and a probe pin formation process.

First, referring to FIG. 6, an insulator layer 112a and a photoresist layer 113a are sequentially formed on an insulating substrate 110 such as a glass substrate. Thereafter, as shown in FIG. 7, the photoresist layer 113a is patterned through a photolithography process to form a photoresist pattern 113 having an opening having an X-axis line electrode shape. By selectively etching the insulator layer 112a using the photoresist pattern 113 as an etch mask, an insulator layer pattern 112 having an opening 114 in the shape of an X-axis line electrode is formed.

Next, as shown in FIG. 8, a metal layer such as gold (Au) is deposited on the entire surface of the resultant having the insulating layer pattern 112. Accordingly, the metal layer 115 ′ is formed on the opening 114 and the photoresist pattern 113. Thereafter, as shown in FIG. 9, the photoresist pattern 113 and the metal layer deposited thereon are removed by lifting off the photoresist pattern 113. As a result, the metal layer remains only in the opening 114 to obtain a plurality of X-axis line electrodes 115 arranged in parallel with each other. As described above, the plurality of X-axis line electrodes 115 have a line portion and a pad portion, and each pad portion is alternately disposed at one end and the other end of the line portion.

After the X-axis line electrode 115 is formed, a conductive via forming step is performed. For convenience of description, in FIG. 10 to FIG. 22, the resultant in which the X-axis line electrode 115 is formed is shown in a sectional view rotated by 90 degrees. That is, the sectional drawing of FIG. 10 (b) is a sectional view cut along the cut surface of the direction parallel to an X-axis line electrode.

Referring to FIG. 11, an insulator layer 120a and a photoresist layer 121a are sequentially formed on the entire surface of the resultant on which the X-axis line electrode 115 is formed. Thereafter, referring to FIG. 12, the photoresist layer 121a is patterned to form a photoresist pattern 121 defining a conductive via region, and the insulator layer 120a is formed by using the pattern 121 as an etching mask. By selectively etching, the insulator layer pattern 120 is formed. As a result, the via hole 124 is formed in the insulator layer. The via holes 124 are arranged in a matrix to selectively expose the X-axis electrode lines.

Next, as shown in FIG. 13, a metal layer is deposited on the entire surface of the resultant via hole 124. Accordingly, the via hole 124 is partially filled with the metal layer. In the deposition of the metal layer, first, the bottom and the outer surface of the via hole 124 are deposited with gold (Au), and then a large amount of deposition is performed with nickel or the like, and then gold may be deposited again for height adjustment. Such three-step deposition can form a conductive via having a nickel inside and a gold outside, and can achieve cost reduction (especially gold material cost) while ensuring sufficient conductivity.

Thereafter, as shown in FIG. 14, the photoresist pattern 121 and the metal layer deposited thereon are removed by lifting off the photoresist pattern 121. Accordingly, a plurality of conductive vias 170 contacted with the X-axis line and arranged in a matrix form are obtained.

After the conductive via 170 is formed, a Y-axis line electrode forming step is performed. As shown in FIG. 15, an insulator layer 131a and a photoresist layer 132a are sequentially formed on the entire surface of the resultant product in which the conductive via 170 is formed. Thereafter, as shown in FIG. 16, the photoresist layer 132a is patterned to form a photoresist pattern 132 having an opening having a Y-axis line electrode shape, and the insulator layer 131a is formed as an etch mask. Etch selectively. As a result, an insulator layer pattern 131 having an opening 134 having a Y-axis line electrode shape is formed. The plurality of openings 134 are arranged in parallel to each other in a direction orthogonal to the X-axis line electrode 115, and expose the conductive vias 170.

Next, as shown in FIG. 17, a metal layer such as gold is deposited on the entire surface of the resultant product on which the insulator layer pattern 131 is formed. Accordingly, the metal layer 125 ′ is formed on the opening 134 and the photoresist pattern 132. Thereafter, as shown in FIG. 18, the photoresist pattern 132 and the metal layer deposited thereon are removed by lifting off the photoresist pattern 132. Accordingly, the metal layer remains only in the region of the opening 134, thereby obtaining a plurality of Y-axis line electrodes 125 arranged in parallel with each other. As described above, the plurality of Y-axis line electrodes 125 has a line portion and a pad portion, and each pad portion is alternately disposed at one end and the other end of the line portion. The plurality of Y-axis line electrodes 125 are connected to the X-axis line electrode 115 through the conductive via 170 and orthogonal to the X-axis line electrode 115.

After the Y-axis line electrode 125 is formed, a probe pin forming step is performed. Referring to FIG. 19, an insulator layer 135a and a photoresist layer 136a are sequentially formed on the entire surface of the resultant surface on which the Y-axis line electrode 125 is formed. Preferably, the insulator layer 135a is formed to a thickness of about 50 μm or more and the photoresist layer 136a is formed to a thickness of about 30 μm so as to secure a sufficient height and a protruding length of the probe pin.

Thereafter, referring to FIG. 20, the photoresist layer 136a is patterned to form a photoresist pattern 136 that defines a probe pin region. The probe pin regions (openings) defined by the photoresist pattern 136 are formed to align with the conductive vias 170 thereunder. The insulator layer pattern 135 is formed by selectively etching the insulator layer 135a using the pattern 136 as an etching mask. Accordingly, the probe pin forming hole 138 is formed in the insulator layer. The probe pin forming hole 138 is aligned with the conductive via 170 below it, and selectively exposes the Y-axis line electrode 125.

Next, referring to FIG. 21, electroplating is performed to fill the probe pin forming hole 138 with a metal such as gold (Au) or nickel (Ni). As a result, a probe pin 150 connected to the Y-axis line electrode is formed on the Y-axis line electrode. The probe pins 150 are aligned with the conductive vias 170 below them to form a matrix arrangement. In the electroplating, the bottom and the outer surface of the probe pin forming hole 138 may be plated with gold 150b and plated with nickel 150a to fill the inside thereof. Thereafter, as shown in FIG. 22, the photoresist pattern 136 is removed to protrude outward from the probe pin 150. Thereby, the probe part of the probe card which concerns on this embodiment is completed.

FIG. 23 is a perspective view illustrating a main part of the probe card probe shown in FIG. 22. As shown in FIG. 23, the X-axis line electrodes 115 and the Y-axis line electrodes 125 that are perpendicular to each other are electrically connected through conductive vias 170 at their intersections (see FIG. 23 (a)). On the Y-axis line electrode 125, a probe pin 150 connected to the protrusion protrudes (see FIG. 23B). The LCD panel inspection is performed by contacting the probe pin 150 with the LCD cell under test.

As described above, tens of thousands to hundreds of thousands of probe pins may be precisely manufactured by using a MEMS manufacturing process including a photolithography process. By using such a probe card, tens of thousands to hundreds of thousands of cells can be probed simultaneously to determine whether a cell is defective or the location of a defective cell.

Hereinafter, a method of inspecting the electrical characteristics of an LCD panel (LCD cell) using the probe card of the present invention will be described. For convenience of explanation of the measuring principle, for example, using a probe card of a 5 × 5 line electrode (see FIGS. 2 and 3), an LCD cell arranged in 5 × 5 (see FIGS. 24 to 26) is used. Check it. As shown in Figs. 24 to 26, each cell C is located at the intersection of the X-axis cell lines X1 'to X5' and the Y-axis cell lines Y1 'to Y5' of the LCD panel. .

First, while the probe pin 150 of the probe card 100 is in contact with the plurality of cells C of the LCD panel at the same time, current is applied to the plurality of cells simultaneously to supply current to each cell. For example, if the current supplied to each cell of the LCD panel is 2 mA, a current of 1 mA flows through the X-axis cell lines X1 'to X5' and the Y-axis cell lines Y1 'to Y5', respectively.

In the current (or power) supply state, current flowing through each of the line electrodes X1 to X5 and Y1 to Y5 of the probe card is measured. Through this measurement current, the LCD cell line with a defective cell can be confirmed. If all the cells C are good (no defective cells) as shown in Fig. 24, the measurement current of all the line electrodes (X1 to X5, Y1 to Y5) equally represents 5 mA. Thus, each line If the measured currents of the electrodes X1 to X5 and Y1 to Y5 are all the same, it is determined that there are no defective cells.

In contrast, when at least one cell is a defective cell, the electrode line (of the probe card) corresponding to the cell line (of the LCD) with the defective cell exhibits a measurement current lower than 5 mA. For example, referring to FIG. 25, 4 mA is respectively detected in the electrode lines X3 and Y2 corresponding to the cell lines X3 'and Y2' having the defective cells P, and the remaining electrode lines X1, X2, 5 mA is detected at X4, X5, Y1, and Y3 to Y5). When a relatively low current is detected in the specific electrode lines X3 and Y2 in this manner, it is confirmed that the cell lines X3 'and Y2' corresponding to the specific electrode lines X3 and Y2 have defective cells.

When it is confirmed that there are defective cells in only one X-axis cell line among the X-axis cell lines as shown in FIG. 25, the position of the defective cells can be readily identified. That is, the position of the defective cell can be immediately confirmed by the intersection points X3 'and Y2' between the X-axis cell line X3 'and the Y-axis cell line Y2' with the defective cells. Even when it is confirmed that there is a defective cell in only one Y-axis cell line among the Y-axis cell lines, the position of the defective cell can be immediately identified. For example, when it is confirmed that there are defective cells only in X1 ', X4' and Y5 'through the measurement current of the line electrode, the positions of the defective cells are (X1', Y5 '), (X4', Y5 '). .

However, when at least two X-axis cell lines and at least two Y-axis cell lines are found to have defective cells as shown in FIG. 26 (that is, at least two X-axis electrode lines and at least two Y-axis electrode lines are relative to each other). As a result of low current (less than 5mA), the location of a defective cell cannot be immediately identified, and as described below, an additional process of 'detecting for each X-axis cell line having a defective cell' is needed.

Referring to FIG. 26, when a current is supplied to all cells, a current of 4 mA is detected at the X2 electrode line, a current of 3 mA is detected at the X4 electrode line, and a current of 5 mA is detected at the remaining X-axis electrode line. In addition, 4 mA is detected at the Y2, Y3, and Y4 electrode lines, and 5 mA is detected at the remaining Y-axis electrode lines. Thus, it is confirmed that the cell lines X2 ', X4', Y2 ', Y3', Y4 'have defective cells.

In this case, in order to check the position of the defective cell, the Y-axis electrode line (especially the Y-axis cell with defective cell) is supplied by supplying an electrical signal (current) for each line only to the X-axis cell lines (X2 ', X4') with the defective cells. The current of the Y-axis electrode line corresponding to the line is detected.

That is, first, an electrical signal is supplied only to the X2 'cell line, and currents of the Y2, Y3, and Y4 line electrodes (the Y-axis line electrodes corresponding to the Y-axis cell lines with defective cells) are detected. If the detected current is Y2 = Y4 = 1mA and Y3 = 0mA, the position of the defective cell on the X2 'cell line eventually turns out to be (X2', Y3 '). Thereafter, an electrical signal is supplied only to the X4 'cell line, and currents of the Y2, Y3 and Y4 line electrodes are detected. If the detected current is Y2 = Y4 = 0mA and Y3 = 1mA, the position of the defective cell on the X4 'cell line is finally determined to be (X4', Y2 '), (X4', Y4 ').

The method for determining the defective cell position described above is merely described, for example, and there are various other cases. Basically, however, if the current is applied only to the X-axis (or Y-axis) cell line where the defective cell is located, and the current detected from the Y-axis (or X-axis) line electrode is simultaneously examined, the position of the defective cell is determined in any case. You can check it. For example, referring to FIG. 25, the position of the defective cell can be determined by applying power only to the X3 ′ cell line identified as having a defective cell and simultaneously inspecting all the Y-axis line electrodes of the probe. In this case, the current of the Y-axis line electrode is Y1 = Y3 = Y4 = Y5 = 1mA, and Y2 = 0mA is detected so that the position of the defective cell is confirmed as (X3 ', Y2').

The present invention is not limited by the above-described embodiment and the accompanying drawings, but is intended to be limited by the appended claims, and various forms of substitution, modification, and within the scope not departing from the technical spirit of the present invention described in the claims. It will be apparent to those skilled in the art that changes are possible.

As described above, according to the present invention, there is provided a probe card that can effectively and accurately inspect a large number of LCD cells simultaneously. In addition, according to the probe card manufacturing method of the present invention, a probe card having a large number of prop pins can be manufactured more precisely. In addition, by using the LCD panel inspection method of the present invention, a large number of LCD cells can be inspected more quickly and accurately, and the position of defective cells can be easily and accurately confirmed.

Claims (20)

  1. Circuit board;
    An insulating substrate formed on the circuit board;
    A plurality of X-axis line electrodes arranged in parallel to each other on the insulating substrate;
    A plurality of Y-axis line electrodes arranged parallel to each other on the X-axis line electrode, spaced apart from the X-axis line electrode line, and connected to the X-axis line electrode through conductive vias formed at the intersections; And
    And a plurality of probe pins formed on the Y-axis line electrode to be in contact with the conductive via and in contact with the Y-axis line electrode.
  2. The method of claim 1,
    And the X-axis line electrode and the Y-axis line electrode are arranged to be perpendicular to each other.
  3. The method of claim 1,
    And each of the X-axis line electrode and the Y-axis line electrode includes a line portion extending in a straight line and a pad portion formed at one end of the line portion and connected to an external wiring.
  4. The method of claim 3,
    And the plurality of x-axis line electrodes and the Y-axis line electrodes are arranged such that the pad portion is alternately arranged at one end and the other end of the line portion.
  5. Forming a plurality of X-axis line electrodes arranged parallel to each other on an insulating substrate;
    Forming a plurality of conductive vias in contact with the X-axis line electrodes on the plurality of X-axis line electrodes;
    Forming a plurality of Y-axis line electrodes on the conductive via and arranged in parallel with each other to be in contact with the conductive via and intersect the X-axis line electrode; And
    Forming a plurality of probe pins on the plurality of Y-axis line electrodes that are aligned with the conductive vias and are in contact with the Y-axis line electrodes.
  6. The method of claim 5,
    And the Y-axis line electrode is formed to be orthogonal to the X-axis.
  7. The method of claim 5,
    And each of the X-axis line electrode and the Y-axis line electrode is formed to have a line portion extending in a straight line and a pad portion disposed at one end of the line portion and connected to an external wiring.
  8. The method of claim 7, wherein
    The plurality of X-axis line electrodes and Y-axis line electrodes, the pad portion is formed so that the pad portion is alternately arranged on one end and the other end.
  9. The method of claim 5,
    The X-axis line electrode forming step,
    Forming a first insulator layer on the insulating substrate;
    Forming a photoresist pattern having an opening in the shape of an X-axis line electrode on the first insulator layer;
    Selectively etching the first insulator layer using the photoresist pattern as an etching mask; And
    Depositing a metal layer on the entire surface of the resultant material; And removing the photoresist pattern and the metal layer deposited thereon by a lift off method.
  10. The method of claim 5,
    The conductive via forming step,
    Forming a second insulator layer on the X-axis electrode line;
    Forming a photoresist pattern defining a conductive via region on the second insulator layer;
    Selectively etching the second insulator layer using the photoresist pattern as an etch mask to form via holes in the insulator layer;
    Depositing a metal layer on the entire surface of the resultant material to fill the via hole; And
    And removing the photoresist pattern and the metal layer deposited thereon by a lift off method.
  11. The method of claim 10,
    The metal layer deposition step for filling the via hole,
    Depositing a first metal on a bottom and an outer surface of the via hole;
    Thereafter depositing a second metal to fill the inside of the via hole; And
    Thereafter, depositing the first metal again to a predetermined height.
  12. The method of claim 11,
    And the first metal is gold, and the second metal is nickel.
  13. The method of claim 5,
    The Y-axis line electrode forming step,
    Forming a third insulator layer on the conductive vias;
    Forming a photoresist pattern having an opening in the shape of a Y-axis line electrode on the third insulator layer;
    Selectively etching the third insulator layer using the photoresist pattern as an etching mask;
    Depositing a metal layer on the entire surface of the resultant product; And
    And removing the photoresist pattern and the metal layer deposited thereon by a lift off method.
  14. The method of claim 5,
    The probe pin forming step may include forming a fourth insulator layer on the Y-axis line electrode;
    Forming a photoresist pattern defining a probe pin region on the fourth insulator layer;
    Selectively etching the fourth insulator layer using the photoresist pattern as an etching mask to form a hole for forming a probe pin;
    Filling the probe pin forming hole with a metal by a plating method; And
    Probe card manufacturing method comprising the step of removing the photoresist pattern.
  15. Simultaneously applying current to the plurality of cells while the probe pins of the probe card of claim 1 are in contact with the plurality of cells of the LCD panel;
    Measuring a current flowing through each line electrode of the probe card while the current is applied;
    Identifying an LCD cell line having defective cells through the measured current; And
    If there is at least one LCD cell line with defective cells, identifying the location of the defective cells.
  16. The method of claim 15,
    Identifying the LCD cell line with the defective cell,
    LCD line inspection method comprising the step of identifying a line electrode exhibiting a low measurement current compared to other line electrodes.
  17. The method of claim 15,
    Identifying the LCD cell line with the defective cell,
    If all of the line electrodes have the same measured current, determining that there are no defective cells; And
    If the measured current of some of the line electrodes is lower than the measured current of the other line electrodes, the LCD cell line corresponding to the some of the line electrodes includes determining the cell line with the defective cells Way.
  18. The method of claim 15,
    Checking the location of the defective cell,
    If it is determined that there is a defective cell in only one X-axis cell line among the X-axis cell lines or that there is a defective cell in only one Y-axis cell line among the Y-axis cell lines, the X-axis cell line with the defective cell Identifying the location of the defective cell at the intersection of the Y-axis cell line; And
    When it is confirmed that there are defective cells in at least two X-axis cell lines and at least two Y-axis cell lines, a current is detected at the Y-axis line electrode by applying a current to only the X-axis cell line in which the defective cells exist. Checking the position of the defective cell through the inspection method of the LCD panel comprising the.
  19. The method of claim 15,
    Checking the location of the defective cell,
    And applying a current to only the X-axis cell line having the defective cell to determine the position of the defective cell through the current detected by the Y-axis line electrode.
  20. The method of claim 15,
    Checking the location of the defective cell,
    And applying a current to only the Y-axis cell line having the defective cell to determine the position of the defective cell through the current detected by the X-axis line electrode.
KR1020060078526A 2006-08-21 2006-08-21 Probe card, method of manufacturing the same and method of testing lcd pannel using the same KR20080017120A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104101744B (en) * 2013-04-10 2017-05-24 佛山市国星半导体技术有限公司 Probe clamp, and LED rapid lightening testing apparatus and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104101744B (en) * 2013-04-10 2017-05-24 佛山市国星半导体技术有限公司 Probe clamp, and LED rapid lightening testing apparatus and method

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