KR20080012455A - Printed circuit board forming bottom solder resister - Google Patents

Abstract

A board with a bottom solder resister is provided to prevent damage to a bonding surface between the board and a chip device by uniformly transmit external pressure to be applied to the board. At least one chip device(140) is mounted on a top surface of a board layer(110). A bottom solder resister(120) including a linear solder resister is formed on a bottom surface of the board layer, the linear solder resister being formed superposed at least two times in the area which is not deviated from a mounted region of the chip device. The solder resister has a thickness of 10um to 20um. The solder resister is formed in a lattice shape in the mounting region of the chip device.

Description

Printed Circuit Board forming bottom solder resister

1 is a top view illustratively showing a substrate structure constituting a conventional single module package.

Figure 2 is a side cross-sectional view illustratively showing the structure of the bottom solder resist formed on the bottom of the substrate constituting a conventional single module package.

3 is a flowchart illustrating a manufacturing process of a substrate on which a bottom solder resist is formed according to an embodiment of the present invention.

4 is a top view illustrating a structure of a substrate on which a bottom solder resist is formed according to an embodiment of the present invention.

5 is a side cross-sectional view illustratively showing a structure of a bottom solder resist of a substrate according to an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

100: substrate on which bottom solder resist is formed

110: substrate layer 120 bottom solder resist

130: pattern 140: chip element

150: ground floor

The present invention relates to a substrate on which a bottom solder resist is formed.

The term resist is used in the PCB manufacturing process to mean "films that protect against any treatment or reaction." For example, "corrosion resist" is a protective film against corrosion, and serves to protect the conductive portion to be left during chemical treatment, and "plating resist" refers to a film that protects a particular area from being plated.

Solder Resister (SR) refers to a film that covers wiring patterns to prevent unwanted connection by soldering during component mounting. It also plays a role and is usually formed in paint form.

Since the wiring pattern is made by corrosion of the copper foil coated on the substrate, in principle, it can be said to be a spiral without an insulation coating. With the development of technologies such as SIP (System In Package), the gaps between wiring patterns on the substrate are formed to be narrower, which causes problems such as short circuits and misconnections between the wirings.

In order to prevent such defects, a solder resist (mask) for shielding a region other than the mounting region (solder region) of the component is applied to coat the spiral wiring, and this application process is often referred to as a "printing process".

In general, when manufacturing a single module package using a technology such as SIP, chip devices are mounted on the upper surface of the substrate, and ground patterns, routing patterns, bonding patterns, transmission patterns, pin patterns, etc. Similar to that described above, a bottom solder resist is formed on the pattern to protect the pattern.

1 is a top view illustrating a structure of a substrate 10 constituting a conventional single module package, and FIG. 2 is a bottom solder resist 12 formed on a bottom surface of the substrate 10 constituting a conventional single module package. It is a side cross-sectional view showing an example of the structure.

Referring to FIG. 1, the bare dies are arranged on the upper surface of the substrate layer 11, and various patterns 13 and ground patterns are formed on the circumferential side and the bottom surface of the substrate layer 11. (Included in Fig. 15) is formed, and the bottom solder resist 12 is shown projected on the upper surface side in a form of a checkerboard shape as a linear shape.

2 is a side cross-sectional view of a part of a mounting area of the mounting area of the chip device 14 shown in FIG. 1. In the related art, the mounting area of the chip device 14 and the bottom solder resist 12 may be formed. It can be seen that the positions are designed without considering each other.

That is, when the bottom solder resist 12 is disposed at the center of the mounting region of the chip element 14 and pressure is applied from the top after the chip element 14 is mounted, the chip element 14 is damaged (Chip crack) or It may be a cause of potential progression defects such as a space between the chip element 14 and the substrate layer 11.

For example, if the mounting area of the chip element 14 is designed to ignore the position of the bottom solder resist 12 on the bottom side, a thickness of about 1 ton is applied from the top when the transfer molding process is performed. The chip element 14 and the substrate layer 11 may be exposed to an unbalanced pressing environment due to the step difference caused by the bottom solder resist 12 and may be easily damaged.

The present invention provides a substrate in which the positions of the chip element mounting region and the bottom solder resist are mutually considered and adjusted.

The substrate on which the bottom solder resist is formed is a substrate layer; At least one chip device mounted on an upper surface of the substrate layer; And a linear solder resist formed on a bottom surface of the substrate layer and formed to overlap at least twice in a range without departing from the mounting area of the chip device.

In addition, the solder resist of the substrate on which the bottom solder resist is formed according to the present invention are arranged regularly in a grid form having a horizontal gap between the horizontal side and the vertical side of a predetermined value, the chip element is mounted at least one of the grid form It is arranged and designed on the substrate to correspond to the area.

In addition, a bottom ground layer is formed between the substrate layer and the solder resist provided on the substrate on which the bottom solder resist is formed.

Hereinafter, a substrate in which a bottom solder resist is formed according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a flowchart illustrating a manufacturing process of a substrate on which a bottom solder resist is formed according to an embodiment of the present invention, and FIG. 4 is a substrate on which a bottom solder resist is formed according to an embodiment of the present invention (hereinafter, “ A top view is shown illustratively of the structure of " substrate "

Referring to FIG. 3, there are illustrated two processes in which the substrate 100 according to the present invention is manufactured. The process illustrated in FIG. 3 (a) is based on a surface mounting technique (SMT). It is a substrate fabrication process, and the process illustrated in FIG. 3 (b) shows a substrate fabrication process based on a chip on film (COF) technology.

The substrate 100 according to the present invention relates to a layout design of a mounting area of the chip element 140 mounted on the upper surface of the substrate layer 110 and a bottom solder resist 120 formed on the bottom surface of the substrate layer 110. It is a substrate that can be implemented through any of these processes, including the above two processes.

In addition, the substrate layer 110 used to manufacture the substrate 100 according to the present invention may be made through various materials such as epoxy resin, Teflon resin, BT range, phenol resin, composite member, ceramic, metal, etc. In describing the embodiments of the present invention, a multilayered low temperature co-fired ceramic (LTCC) substrate layer is used.

First, referring to FIG. 3A, the substrate layer 110 having a multi-layer structure is formed, and the chip element 140 is surface mounted on the upper surface of the substrate layer 110, and the LTCC substrate layer is 800 to 1000 ° C. FIG. It is manufactured using the co-firing method of ceramic and metal at the temperature.

At this time, the glass and ceramics having low melting point are mixed to form a green sheet having a proper dielectric constant, and the conductive paste containing silver or copper as a main material is printed and laminated thereon to form the substrate layer 110. do.

The substrate layer 110 may be highly integrated and light and thin in size by forming passive elements such as a capacitor, a resistor, and an inductor in the substrate.

When the green sheet is dried (S100), a via hole is formed through punching and etching, and conductor printing is performed on the via hole to improve the binding force with the inner surface of the via hole and to electrically connect the pattern formed on the green sheet (S105). ).

Subsequently, a pattern 130, a device, or the like of a ground pattern, a bonding pattern, a line pattern, and the like are formed on each green sheet, and the green sheets are stacked to form a multi-layered substrate layer 110.

At this time, the ground layer 150 of the predetermined region is formed on the bottom surface of the substrate layer 110, and the ground layer 150 is formed to correspond to the die region of the chip device 140 (S110).

In this way, when the substrate layer 110 is produced, the substrate layer 110 is mounted on the jig (S115), the cream solder is printed on the upper surface of the substrate layer 110, the printing process of the cream solder, the substrate layer This is done by placing a metal mask (a groove is formed corresponding to the soldering region) over the 110 and squeezing the cream solder applied onto the metal mast (S120).

In the printing process, the print quality is affected by the amount of squeegee of the cream solder, and the cream solder (also called a solder paste) used in the printing process is printed by kneading lead powder and flux in the form of a paste. It is a member whose viscosity is adjusted to be good.

Here, when Pb Free method is used, tin (Sn), tin-copper (Sn-Cu) alloy, tin-silver (Sn-Ag) alloy, tin-silver-copper (Sn-Ag-Cu) alloy instead of lead Or the like can be used.

When the cream solder is printed, the chip device 140 is mounted using a component mounter and die-bonds the chip device 140, and then a reflow process is performed (S125).

The reflow process is a process in which a solder portion of the chip element 140 is fixed to a lead area while melting the cream solder by applying heat to the printed cream solder.

Subsequently, the cleaning process is performed to remove solder residues around the chip device 140 such as solder balls, and the wire bonding process is performed (S130).

Subsequently, an insulating member is coated, such as a solder resist, to coat the electrically exposed part and a curing process in an oven to firmly fix the chip element 140, the various patterns 130, and the bonding part.

In processing the coating process, a bottom solder resist 120 is formed under the ground layer 150. The bottom solder resist 120 is a linear having a predetermined width, and unlike the prior art, the bottom solder resist 120 is formed. It is designed to fit the mounting area.

That is, the bottom solder resist 120 is formed to overlap at least two times in a lattice form as shown in FIG. 4 without departing from the mounting area of the chip device 140 (S135).

Subsequently, the substrate 100 according to the present invention is molded by a transfer molding process to form a single package (S140). Transfer molding is performed by mounting a substrate on a mold die in a predetermined form and transferring a certain viscosity. It refers to a molding technology in which a compound having a hardened state is filled with heat and pressure.

In this way, the transfer molding technique can be used to form a molding part without additional structures such as a molding support, where pressure of about 1 ton is applied.

However, the bottom solder resist 120 forms a lattice to support the substrate layer 110 and the chip device 140 in at least two portions, so that a crack or deterioration between the substrate layer 110 and the chip device 140 may occur. This can be prevented from occurring.

Next, the case of a COF process is demonstrated with reference to FIG.3 (b) drawing.

When the substrate layer 110 is formed through the aforementioned steps S100 to S110 (S200), a bump region is formed in the mounting region of the chip device 140, and the substrate layer 110 is mounted on the jig (S205).

When the substrate layer 110 is mounted, an insulating tape is attached and the chip element 140 is mounted (S210).

When the chip device 140 is mounted, a copper foil pattern having a predetermined width is bound on the insulating tape through an adhesive member, and a solder resist is coated on a region other than the lead region connected to the chip device 140 among the copper foil patterns. (The coating process is processed) (S215).

When the coating process of the upper surface of the substrate layer 110 is processed, the bottom solder resist 120 is formed on the bottom side, and is designed to be arranged in accordance with the mounting area of the chip element 140 as a linear shape having a predetermined width as described above.

The bottom solder resist 120 has a lattice shape as shown in FIG. 4 and is formed to overlap at least two times in a range not departing from the mounting region of the chip device 140 (S220).

Thereafter, the bump of the chip device 140 and the lead region of the substrate layer 110 are connected to each other so as to be electrically connected (S225).

The COF process may be performed together with the surface mounting process described above.

Hereinafter, the structure of the bottom solder resist 120 will be described in more detail with reference to FIG. 5.

5 is a side cross-sectional view illustrating a structure of a bottom solder resist 120 of a substrate according to an embodiment of the present invention.

The bottom solder resist 120 is formed to have a thickness of about 10 μm to 20 μm (typically, may be formed to a thickness of about 17.35 μm), and as described above, an area in which any one chip element 140 is mounted. (When vertically projected to the bottom of the substrate layer) It is formed in a lattice form inside.

The bottom solder resist 120 is formed by overlapping at least two times on the horizontal side and the vertical side in the lattice form, and according to the embodiment of the present invention shown in FIGS. 4 and 5, the chip device 140. Two grid areas are formed on the mounting area.

Therefore, since the bottom solder resist 120 supports the substrate layer 110 and the chip device 140 at six places, the pressure is evenly distributed without forming a step by the pressure from the top when the transfer molding process is performed. Dispersion prevents damage to the substrate layer 110 and the chip device 140.

In addition, in the arrangement design considering the mounting area of the bottom solder resist 120 and the chip element 140 together, the bottom solder resist 120 has a lattice form having a predetermined value interval between the horizontal side and the vertical side, respectively. The mounting region of the chip device 140 may be arranged and arranged based on the intersection of the bottom solder resist 120 arranged regularly.

Although the present invention has been described above with reference to the embodiments, these are only examples and are not intended to limit the present invention, and those skilled in the art to which the present invention pertains may have an abnormality within the scope not departing from the essential characteristics of the present invention. It will be appreciated that various modifications and applications are not illustrated. For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

According to the substrate on which the bottom solder resist is formed according to the present invention, when external pressure is applied from the upper side as in the transfer molding process, the phenomenon in which pressure is unbalanced by the bottom solder resist is eliminated, so that the chip element itself is broken or There is an effect that can prevent damage to the bonding surface of the substrate and the chip element.

In addition, according to the present invention, when the communication module is manufactured through the SIP technology, the resistance of the chip element and the substrate to external pressure is increased, so that the cause of the defect can be eliminated at the source, thereby reducing the production cost and the production time. It has an effect.

Claims (6)

Substrate layer; At least one chip device mounted on an upper surface of the substrate layer; And A bottom solder resist is formed on the bottom surface of the substrate layer, and includes a bottom solder resist including a linear solder resist formed to overlap at least twice within a range without departing from the mounting area of the chip device. The method of claim 1, wherein the solder resist The bottom solder resist is formed substrate, characterized in that formed in a thickness of 10 μm to 20 μm. The method of claim 1, wherein the solder resist The bottom solder resist is formed substrate, characterized in that formed in the lattice shape in the mounting area of the chip element. The method of claim 3, wherein the solder resist In forming the lattice, the bottom solder resist is formed substrate, characterized in that formed at least two times overlapping on the horizontal side and vertical side. The method of claim 1, The solder resists are arranged regularly in a lattice form in which the horizontal side and the vertical side each have a predetermined value interval, And the chip device is disposed on the substrate such that at least one of the grating shapes corresponds to a mounting area. The method of claim 1, And a bottom ground layer formed between the substrate layer and the solder resist.

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