KR20080006894A - Display device and method for manufacturing the same - Google Patents

Abstract

A display device and a manufacturing method thereof are provided to crystallize an amorphous semiconductor layer and then to pattern the crystallized semiconductor layer, thereby forming the semiconductor with plural island types. A polycrystalline semiconductor is formed on a substrate. A data line(171) is formed on a polycrystalline semiconductor and includes a source electrode. A drain electrode(175) is formed on the polycrystalline semiconductor and located oppositely to a source electrode(173). A gate line including a gate electrode(124) is formed on the source electrode and the drain electrode and overlapped with the polycrystalline semiconductor. A pixel electrode(191) is connected with the drain electrode. A resistant contact member is located between the polycrystalline semiconductor and the source/drain electrodes and has the same plane as the polycrystalline semiconductor. A buffer layer is formed at the lower portion of the polycrystalline semiconductor. A light emission member is formed on the pixel electrode. A common electrode is formed on a light emission member.

Description

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a layout view of a display device according to an exemplary embodiment.

FIG. 2 is an enlarged cross-sectional view of a pixel of the display device of FIG. 1;

3 to 8 are cross-sectional views sequentially illustrating a method of manufacturing the display device of FIGS. 1 and 2 according to an exemplary embodiment of the present invention.

9 is an equivalent circuit diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.

10 is a layout view of an organic light emitting diode display according to an exemplary embodiment.

FIG. 11 is a cross-sectional view of the organic light emitting diode display of FIG. 10 taken along the line XI-XI. FIG.

12 and 13 are cross-sectional views illustrating a method of manufacturing an organic light emitting diode display according to an exemplary embodiment of the present invention.

14, 16, 18, 20, and 22 are layout views sequentially illustrating a method of manufacturing an organic light emitting diode display according to an exemplary embodiment of the present invention.

FIG. 15 is a cross-sectional view of the organic light emitting diode display of FIG. 14 taken along the line XV-XV. FIG.

FIG. 17 is a cross-sectional view of the organic light emitting diode display of FIG. 16 taken along the line XVII-XVII. FIG.

19 is a cross-sectional view of the organic light emitting diode display of FIG. 18 taken along a line XIX-XIX.

FIG. 21 is a cross-sectional view of the organic light emitting diode display of FIG. 20 taken along a line XXI-XXI.

FIG. 23 is a cross-sectional view of the organic light emitting diode display of FIG. 22 taken along the line XXIII-XXIII.

<Description of Drawing>

110: insulating substrate 121: gate line

124: gate electrode 124a: switching gate electrode

124b: drive gate electrode 127: sustain electrode

129: end of gate line

140: gate insulating film 154a: switching semiconductor

154b: driving semiconductors 163a, 163b, 165a, and 165b: ohmic contacts

171: data line 172: driving voltage line

173: source electrode 175: drain electrode

173a: switching source electrode 173b: drive source electrode

175a: switching drain electrode 175b: driving drain electrode

179: end of data line 81, 82: contact auxiliary member

85: connecting member

181, 182, 184, 185, 185a, 185b: contact hole

191: pixel electrode 270: common electrode

361: partition 370: organic light emitting member

Qs: switching transistor Qd: driving transistor

LD: organic light emitting diamond Vss: common voltage

Cst: retaining capacitor

The present invention relates to a display device and a method of manufacturing the same.

In general, a display device such as a liquid crystal display (LCD), an organic light emitting diode display (OLED display), an electrophoretic display, or the like, includes a plurality of pairs of electric field generating electrodes It includes an electro-optical active layer contained in. The liquid crystal display device includes a liquid crystal layer as the electro-optical active layer, and the organic light emitting display device includes an organic light emitting layer as the electro-optical active layer.

One of the pair of field generating electrodes is typically connected to a switching element to receive an electrical signal, and the electro-optical active layer converts the electrical signal into an optical signal to display an image.

The display device includes a thin film transistor (TFT), which is a three-terminal element, as a switching element and / or a driving element, and includes a gate line and a pixel for transmitting a scan signal for controlling the thin film transistor. A data line for transmitting a signal to be applied to the electrode is provided in the flat panel display.

Such thin film transistors include semiconductors. Semiconductors can be divided into amorphous semiconductors and polycrystalline semiconductors according to the crystal state.

Since amorphous semiconductors can form thin films at low temperatures, they are mainly used in display devices using glass having a low melting point as a substrate. However, amorphous semiconductors have poor field effect mobility and stability.

In contrast, polycrystalline semiconductors have high field effect mobility and stability.

However, polycrystalline semiconductors have limitations in application to large area display devices due to difficulty in crystallization. Therefore, thin film transistors including polycrystalline semiconductors require structures and processes different from thin film transistors including amorphous semiconductors. In this case, the structure and the process are complicated, which significantly increases manufacturing time and manufacturing cost.

Accordingly, the technical problem to be solved by the present invention is to solve the problem, and to increase the field effect mobility and stability while simplifying the structure and process of the display device including the polycrystalline semiconductor.

A display device according to an exemplary embodiment of the present invention includes a polycrystalline semiconductor formed on a substrate, a data line formed on the polycrystalline semiconductor and including a source electrode, a drain electrode formed on the polycrystalline semiconductor and facing the source electrode, A gate line formed on the source electrode and the drain electrode and including a gate electrode overlapping the polycrystalline semiconductor, a pixel electrode connected to the drain electrode, between the polycrystalline semiconductor and the source electrode, and between the polycrystalline semiconductor and the And an ohmic contact member positioned between the drain electrodes and having substantially the same planar shape as the polycrystalline semiconductor except between the source electrode and the drain electrode.

The display device may further include a buffer layer formed under the polycrystalline semiconductor.

The display device may further include a light emitting member formed on the pixel electrode and a common electrode formed on the light emitting member.

According to an embodiment of the present invention, a method of manufacturing a display device includes sequentially depositing an amorphous semiconductor layer and an amorphous semiconductor layer doped with impurities on a substrate, and crystallizing the amorphous semiconductor layer and the amorphous semiconductor layer doped with impurities. Patterning the crystallized semiconductor layer and the doped semiconductor layer to form a polycrystalline semiconductor and an ohmic contact layer, forming a data line and a drain electrode including a source electrode on the ohmic contact layer, the data Etching the ohmic contact layer using a line and the drain electrode as a mask, forming a gate line including a gate electrode on the data line and the drain electrode, and forming a pixel electrode connected to the drain electrode Steps.

Crystallizing the amorphous semiconductor layer and the amorphous semiconductor layer doped with impurities may be performed by solid phase crystallization (SPC).

The method may further include forming a gate insulating film on the entire surface of the substrate before forming the gate line.

The method may further include forming a buffer layer on the entire surface of the substrate before the stacking of the amorphous semiconductor layer.

The method may further include forming an insulating film having an opening after the forming of the pixel electrode, forming a light emitting member in the opening, and forming a common electrode on the light emitting member and the insulating film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a layout view of a display device according to an exemplary embodiment. FIG. 2 is an enlarged cross-sectional view of a pixel of the display device of FIG. 1.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention is connected to a plurality of gate lines 121 and data lines 171 that cross each other and is arranged in a matrix form. A plurality of pixels P is included.

The gate lines 121 extend substantially in the row direction and are substantially parallel to each other, and the data lines 171 extend substantially in the column direction and are substantially parallel to each other. The gate line 121 transfers a scan signal and the data line 171 transfers an image signal.

The plurality of pixels P defined by the gate line 121 and the data line 171 together form a display area D for displaying an image. The remaining portion except the display area D is called a peripheral area. One end portion of the gate line 121 and the data line 171 extends to the peripheral area beyond the display area D in order to receive an external signal.

The pixel P includes a thin film transistor Q which is a switching element, and the thin film transistor Q turns on or off an image signal according to a scan signal.

The structure of the pixel P of the display device of FIG. 1 will be described in detail with reference to FIG. 2.

A buffer layer 111 is formed on an insulating substrate 110 made of transparent glass or plastic. The buffer layer 111 may be made of an insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx).

An island polycrystalline semiconductor 154 is formed on the buffer layer 111. The polycrystalline semiconductor 154 may be polycrystalline silicon.

The data line 171 and the drain electrode 175 are formed on the polycrystalline semiconductor 154.

The data line 171 includes an end portion (not shown) having a large area for connection between a source electrode 173 extending toward the polycrystalline semiconductor 154 and another layer or an external driving circuit. When a data driving circuit (not shown) generating a data signal is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is island-shaped and separated from the data line 171. The source electrode 173 and the drain electrode 175 face each other with respect to the polycrystalline semiconductor 154.

The data line 171 and the drain electrode 175 may include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, and molybdenum ( It may be made of molybdenum-based metals such as Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties.

The data line 171 and the drain electrode 175 are inclined with respect to the surface of the substrate 110 and the inclination angle is preferably about 30 to 80 degrees.

A plurality of pairs of ohmic contacts 163 and 165 are formed between the source electrode 173 and the polycrystalline semiconductor 154 and between the drain electrode 175 and the polycrystalline semiconductor 154, respectively. The ohmic contacts 163 and 165 may be island-shaped, and may be made of polycrystalline silicon doped with a high concentration of impurities such as phosphorus (P).

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the data line 171 and the drain electrode 175.

The gate line 121 is formed on the gate insulating layer 140.

The gate line 121 includes a wide end portion (not shown) for connecting a gate electrode 124 overlapping the polycrystalline semiconductor 154 with another layer or an external driving circuit. When a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The gate line 121 may be made of a material of the same series as the data line 171.

The side surface of the gate line 121 is inclined with respect to the surface of the substrate 110 and the inclination angle is preferably about 30 to 80 degrees.

A passivation layer 180 is formed on the gate line 121 and the gate insulating layer 140. A plurality of contact holes (not shown) are formed in the passivation layer 180 to expose an end portion (not shown) of the gate line 121, and the data line 171 is formed in the passivation layer 180 and the gate insulating layer 140. The contact hole (not shown) which exposes the end part (not shown) of the () and the plurality of contact holes 185 which expose the drain electrode 175 are formed.

A plurality of pixel electrodes 191 are formed on the passivation layer 180.

The pixel electrode 191 is electrically connected to the drain electrode 175 through the contact hole 185, and is a transparent conductor such as ITO or IZO, or gold (Au), platinum (Pt), nickel (Ni), or copper. (Cu), tungsten (W) or alloys thereof, such as opaque conductors.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the polycrystalline semiconductor 154 form one thin film transistor Q, and a channel of the thin film transistor Q. ) Is formed in the polycrystalline semiconductor 154 between the source electrode 173 and the drain electrode 175. In this case, the portions of the source electrode 173 and the drain electrode 175 facing each other may be bent to increase the channel width to improve current characteristics.

Although only one thin film transistor is illustrated in the present exemplary embodiment, at least one thin film transistor and a signal line for driving the thin film transistor may be further included.

As described above, the display device according to the exemplary embodiment may have high carrier mobility and stability by forming a channel of a thin film transistor in a polycrystalline semiconductor. In addition, by having a high charge mobility it is also possible to integrate the driving circuit in the display panel.

Next, a method of manufacturing the display device of FIGS. 1 and 2 will be described with reference to FIGS. 3 to 8.

3 to 8 are cross-sectional views sequentially illustrating a method of manufacturing the display device of FIGS. 1 and 2 according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a silicon oxide, an amorphous silicon, and an amorphous silicon doped with impurities are sequentially chemically vapor deposited (CVD) on the entire surface of the substrate 110 to form a buffer layer 111 and an amorphous silicon layer 150a. And an amorphous silicon layer 160a doped with impurities.

Next, as shown in FIG. 4, the doped amorphous silicon layer 160a and the amorphous silicon layer 150a are crystallized at once to form the doped polycrystalline semiconductor layer 160b and the polycrystalline semiconductor layer 150b. do. In this case, the crystallization may be performed by a method such as solid phase crystallization (SPC), liquid phase crystallization (LPR), or excimer laser annealing (ELA), among which a solid phase crystallization method is preferable. Do. After solid phase crystallization, it is preferable to perform rapid thermal annealing (RTA) in parallel.

Next, as shown in FIG. 5, the doped polycrystalline semiconductor layer 160b and the polycrystalline semiconductor layer 150b are photo-etched at once to form the doped polycrystalline semiconductor 164 and the polycrystalline semiconductor 154. do.

Next, as shown in FIG. 6, the conductive layer is stacked on the polycrystalline semiconductor layer 160b and the buffer layer 111 doped with impurities, and photo-etched to drain the data line 171 and the drain electrode including the source electrode 173. 175 is formed.

Subsequently, a pair of ohmic contacts 163 and 165 are dry-etched by using the data line 171 and the drain electrode 175 as a mask to dry-etch the polycrystalline semiconductor 164 doped with impurities to form a pair of the polycrystalline semiconductor 154. Expose some.

Next, as shown in FIG. 7, the gate insulating layer 140 is stacked on the entire surface including the data line 171 and the drain electrode 175, and a gate line including the gate electrode 124 is disposed thereon (not shown). To form.

Next, as shown in FIG. 8, after the passivation layer 180 is stacked on the entire surface of the substrate, the passivation layer 180 and the gate insulating layer 140 are photo-etched together to form a plurality of contact holes 185.

Next, as shown in FIG. 2, a conductive layer such as ITO is stacked on the passivation layer 180 and photo-etched to form the pixel electrode 191.

As described above, according to one embodiment of the present invention, the amorphous semiconductor layer is first crystallized and then patterned into an island-type polycrystalline semiconductor. In this case, since the substrate is fixed by the amorphous semiconductor layer formed on the entire surface of the substrate and the amorphous semiconductor layer doped with impurities in the crystallization step, it is possible to prevent the substrate from shrinking or expanding by the applied heat.

In addition, according to one embodiment of the present invention, since the amorphous semiconductor layer is first crystallized to form a conductive layer such as a gate line or a data line, there is no limitation in using a low melting point conductor such as aluminum as a material of the gate line or data line.

In addition, unlike conventional polycrystalline thin film transistor processes, no additional steps such as ion doping are required, thereby reducing manufacturing cost and manufacturing time.

 Hereinafter, an organic light emitting diode display, which is one of the display devices described above, will be described with reference to FIGS. The content overlapping with the above-described embodiment is omitted.

9 is an equivalent circuit diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.

Referring to FIG. 9, the organic light emitting diode display according to the present exemplary embodiment includes a plurality of signal lines 121, 171, and 172, and a plurality of pixels PX connected to them and arranged in a substantially matrix form.

The signal line includes a plurality of gate lines 121 for transmitting a gate signal (or scan signal), a plurality of data lines 171 for transmitting a data signal, and a plurality of driving voltage lines 172 for transmitting a driving voltage. It includes. The gate lines 121 extend substantially in the row direction, and are substantially parallel to each other, and the data line 171 and the driving voltage line 172 extend substantially in the column direction, and are substantially parallel to each other.

Each pixel PX includes a switching transistor Qs, a driving transistor Qd, a storage capacitor Cst, and an organic light emitting diode OLED. It includes.

The switching transistor Qs has a control terminal, an input terminal, and an output terminal. The control terminal is connected to the gate line 121, and the input terminal is a data line 171. ) And the output terminal is connected to the driving transistor Qd. The switching transistor Qs transfers the data signal applied to the data line 171 to the driving transistor Qd in response to the scan signal applied to the gate line 121.

The driving transistor Qd also has a control terminal, an input terminal and an output terminal, the control terminal being connected to the switching transistor Qs, the input terminal being connected to the driving voltage line 172, and the output terminal being the organic light emitting diode. It is connected to (LD). The driving transistor Qd flows an output current I _LD whose magnitude varies depending on the voltage applied between the control terminal and the output terminal.

The capacitor Cst is connected between the control terminal and the input terminal of the driving transistor Qd. The capacitor Cst charges the data signal applied to the control terminal of the driving transistor Qd and maintains it even after the switching transistor Qs is turned off.

The organic light emitting diode LD has an anode connected to the output terminal of the driving transistor Qd and a cathode connected to the common voltage Vss. The organic light emitting diode LD displays an image by emitting light having a different intensity depending on the output current I _LD of the driving transistor Qd.

The switching transistor Qs and the driving transistor Qd are n-channel field effect transistors (FETs). However, at least one of the switching transistor Qs and the driving transistor Qd may be a p-channel field effect transistor. In addition, the connection relationship between the transistors Qs and Qd, the capacitor Cst, and the organic light emitting diode LD may be changed.

Hereinafter, the structure of the OLED display of FIG. 9 will be described with reference to FIGS. 10 and 11.

FIG. 10 is a layout view of an organic light emitting diode display according to an exemplary embodiment. FIG. 11 is a cross-sectional view of the organic light emitting diode display of FIG. 10 taken along the line XI-XI.

A buffer layer 111 made of silicon oxide or silicon nitride is formed on the insulating substrate 110.

The switching semiconductor 154a and the driving semiconductor 154b are formed on the buffer layer 111. The switching semiconductor 154a and the driving semiconductor 154b are islands and are separated from each other. The switching semiconductor 154a and the driving semiconductor 154b may be made of polycrystalline silicon.

The data line 171, the driving voltage line 172, the switching drain electrode 175a, and the driving drain electrode 175b are formed on the switching semiconductor 154a, the driving semiconductor 154b, and the substrate 110.

The data line 171 mainly extends in the vertical direction and includes an end portion 179 having a large area for connecting the switching source electrode 173a extending toward the switching semiconductor 154a with another layer or an external driving circuit.

The driving voltage line 172 transfers a driving voltage and is substantially parallel to the data line 171. Each driving voltage line 172 includes a driving source electrode 173b extending toward the driving semiconductor 154b.

The switching drain electrode 175a and the driving drain electrode 175b are island shaped. The switching drain electrode 175a faces the switching source electrode 173a over the switching semiconductor 154a, and the driving drain electrode 175b faces the driving source electrode 173b over the driving semiconductor 154b.

Between the switching semiconductor 154a and the switching source electrode 173a, between the switching semiconductor 154a and the switching drain electrode 175a, between the driving semiconductor 154b and the driving source electrode 173b, and between the driving semiconductor 154b and the driving drain. A plurality of pairs of ohmic contacts 163a, 165a, 163b, and 165b are formed between the electrodes 175b, respectively. The ohmic contacts 163a, 165a, 163b, and 165b may be made of polycrystalline silicon doped with a high concentration of impurities such as phosphorus (P).

A gate insulating layer 140 made of silicon nitride is formed on the data line 171, the driving voltage line 172, the switching drain electrode 175a, the driving drain electrode 175b, and the substrate 110.

The gate line 121 and the driving gate electrode 124b are formed on the gate insulating layer 140.

The gate line 121 mainly extends in the horizontal direction and intersects the data line 171 and the driving voltage line 172. The gate line 121 includes an end portion 129 having a large area for connecting the switching gate electrode 124a extending toward the switching semiconductor 154a with another layer or an external driving circuit.

The driving gate electrode 124b has an island shape and includes a storage capacitor 127 extending in the vertical direction and overlapping the driving voltage line 172.

The passivation layer 180 is formed on the gate line 121, the driving gate electrode 124b, and the gate insulating layer 140.

The passivation layer 180 is formed with a plurality of contact holes 184 and 181 exposing the driving gate electrode 124b and the end portion 129 of the gate line 121, respectively, and the passivation layer 180 and the gate insulating layer 140. A plurality of contact holes 185a, 185b, and 182 exposing the switching drain electrode 175a, the driving drain electrode 175b, and the end portion 179 of the data line 171 are formed.

 The pixel electrode 191, the connection member 85, and the contact auxiliary members 81 and 82 are formed on the passivation layer 180.

The pixel electrode 191 is electrically connected to the driving drain electrode 175b through the contact hole 185b.

The connection member 85 connects the switching drain electrode 175a and the driving gate electrode 124b through the contact holes 184 and 185a.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portions 129 and 179 of the gate line 121 and the data line 171 and the external device.

The pixel electrode 191, the connection member 85, and the contact assistants 81 and 82 may be made of a transparent conductor such as ITO or IZO, and in the case of top emission, aluminum or an aluminum alloy, high work It may be made of an opaque conductor such as gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tungsten (W) or alloys thereof having a work function.

A partition 361 is formed on the pixel electrode 191, the connection member 85, and the contact auxiliary members 81 and 82. The partition 361 defines an opening 365 by surrounding the edge of the pixel electrode 191 like a bank. The partition 361 may be made of an organic insulator such as acrylic resin, polyimide resin, or an inorganic insulator such as silicon oxide (SiO ₂ ) or titanium oxide (TiO ₂ ). It may be, and may be two or more layers. The partition 361 may also be made of a photosensitive material containing black pigment, in which case the partition 361 serves as a light blocking member and the forming process is simple.

An organic light emitting member 370 is formed in the opening 365 on the pixel electrode 191 defined by the partition 361.

The organic light emitting member 370 may have a multilayer structure including an auxiliary layer (not shown) for improving the light emitting efficiency of the light emitting layer in addition to the light emitting layer (not shown) for emitting light.

The light emitting layer may be made of a polymer material or a low molecular material or a mixture thereof that uniquely emits light of any one of primary colors such as three primary colors of red, green, and blue. Polymeric materials include, for example, polyfluorene derivatives, (poly) paraphenylenevinylene derivatives, polyphenylene derivatives, polyvinylcarbazole, polythiophene Derivatives and the like. In addition, low molecular weight materials include anthracene such as 9,10-diphenylanthracene, butadiene such as tetraphenylbutadiene, tetratracene, and distyrylarylene. ) Derivatives, benzazole derivatives and carbazole derivatives. Or the above-mentioned high molecular material or low molecular material as a host material, for example, xanthene, perylene, coumarin, rhodamine, rubrene, dish Aminomethylenepyran compound, thiopyran compound, (thia) pyrilium compound, periflanthene derivative, indenoperylene derivative, carbostyryl Dopant such as a compound, nile red, and quinacridone may be used to increase luminous efficiency. The organic light emitting diode display displays a desired image by using a spatial sum of primary color light emitted from the emission layer. The secondary layer includes an electron transport layer (not shown) and a hole transport layer (not shown) to balance electrons and holes, and an electron injection layer to enhance injection of electrons and holes ( electron injecting layer (not shown) and hole injecting layer (hole injecting layer) (not shown) and the like, and may include one or two or more layers selected from them. The hole transport layer and the hole injection layer are made of a material having a work function that is about the middle of the pixel electrode 191 and the light emitting layer, and the electron transport layer and the electron injection layer have a work function that is about the middle of the common electrode 270 and the light emitting layer. Is made with. For example, the hole transport layer or the hole injection layer may include diamines, MTDATA ([4,4 ', 4 "-tris (3-methylphenyl) phenylamino] triphenylamine), TPD (N, N'-diphenyl-N, N'-di ( 3-methylphenyl) -1,1'-biphenyl-4,4'-diamine), 1,1-bis (4-di-p-tolylaminophenyl) cyclohexane (1,1-bis (4-di-p -tolylaminophenyl) cyclohexane), N, N, N ', N'-tetra (2-naphthyl) -4,4-diamino-p-terphenyl (N, N, N', N'-tetra (2- naphthyl) -4,4-diamino-p-terphenyl), 4,4 ', 4-tris [(3-methylphenyl) phenylamino] triphenylamine (4,4', 4-tris [(3-methylphenyl) phenylamino ] triphenylamine, polypyrrole, polyaniline, a mixture of polyethylenedioxythiophene and polystyrenesulfonic acid (poly- (3,4-ethylenedioxythiophene: polystyrenesulfonate, PEDOT: PSS) can be used.

The organic light emitting member 370 may implement a desired color for each pixel by arranging light emitting layers emitting colors such as red, green, and blue colors for each pixel, and vertically or horizontally arrange the red, green, and blue light emitting layers on one pixel. By forming a white light emitting layer to form a color filter for implementing the colors of red, green and blue on the bottom or top of the white light emitting layer may implement a desired color. In this case, the color filter may be positioned under the light emitting layer in the case of the bottom emission structure, and may be positioned above the light emitting layer in the case of the top emission structure.

In addition to the three-color structure including the red, green, and blue pixels, the four-color structure including the red, green, blue, and white pixels may be arranged in the form of a stripe or a checkerboard to improve luminance.

The common electrode 270 is formed on the organic light emitting member 370. The common electrode 270 is formed on the entire surface of the substrate, and pairs with the pixel electrode 191 to send a current to the organic light emitting member 370.

In the organic light emitting diode display, the switching gate electrode 124a connected to the gate line 121, the switching source electrode 173a and the switching drain electrode 175a connected to the data line 171 are the switching semiconductor 154a. ) And a switching TFT Qs, and a channel of the switching TFT Qs is formed in the switching semiconductor 154a between the switching source electrode 173a and the switching drain electrode 175a. The driving gate electrode 124b connected to the switching drain electrode 175a, the driving source electrode 173b connected to the driving voltage line 172, and the driving drain electrode 175b connected to the pixel electrode 191 are driven. The driving thin film transistor Qd is formed together with the semiconductor 154b, and a channel of the driving thin film transistor Qd is formed in the driving semiconductor 154b between the driving source electrode 173b and the driving drain electrode 175b. do.

As described above, in the organic light emitting diode display according to the exemplary embodiment of the present invention, the channel of the driving thin film transistor is formed in the polycrystalline semiconductor to have high charge mobility and stability, thereby increasing the amount of current flowing through the light emitting device. The brightness can be increased. In addition, the channel of the driving thin film transistor is formed in the polycrystalline semiconductor to prevent the threshold voltage shift caused by the continuous application of the positive voltage during driving, thereby preventing image sticking and shortening the lifespan. can do.

Although only one switching thin film transistor and one driving thin film transistor are shown in the present embodiment, at least one thin film transistor and a plurality of wirings for driving the same are further included, so that the organic light emitting diode LD and the driving transistor may be driven even for a long time. It is possible to prevent or compensate for deterioration of the Qd so as to shorten the lifespan of the organic light emitting display device.

The pixel electrode 191, the organic light emitting member 370, and the common electrode 270 form an organic light emitting diode LD, and the pixel electrode 191 is an anode and the common electrode 270 is a cathode. Alternatively, the pixel electrode 191 becomes a cathode and the common electrode 270 becomes an anode. In addition, the storage electrode 127 and the driving voltage line 172 overlapping each other form a storage capacitor Cst.

Next, a method of manufacturing the organic light emitting display device of FIGS. 10 and 11 will be described in detail with reference to FIGS. 12 to 22.

12 and 13 are cross-sectional views illustrating a method of manufacturing an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIGS. 14, 16, 18, 20, and 22 are exemplary embodiments of the present invention. FIG. 15 is a cross-sectional view illustrating a method of manufacturing an organic light emitting diode display, and FIG. 15 is a cross-sectional view of the organic light emitting diode display of FIG. 14 taken along the line XV-XV, and FIG. 17 is a cross-sectional view of the organic light emitting diode display of FIG. 16. FIG. 19 is a cross-sectional view of the organic light emitting diode display of FIG. 18 taken along a line XIX-XIX, and FIG. 21 is a cross-sectional view of the organic light emitting diode display of FIG. 20 along the line XXI-XXI. FIG. 23 is a cross-sectional view of the organic light emitting diode display of FIG. 22 taken along a line XXIII-XXIII.

First, as shown in FIG. 12, a silicon oxide, an amorphous silicon, and an amorphous silicon doped with impurities are sequentially deposited on the substrate 110 to form a buffer layer 111, an amorphous semiconductor layer 150a, and an amorphous semiconductor layer doped with impurities. To form 160a.

Next, as shown in FIG. 13, the impurity doped amorphous semiconductor layer 160a and the amorphous semiconductor layer 150a are crystallized at once to form the impurity doped polycrystalline semiconductor layer 160b and the polycrystalline semiconductor layer 150b. do. At this time, the crystallization may be performed by a method such as solid phase crystallization, liquid crystallization or excimer laser heat treatment, and among these, the solid phase crystallization method is preferable. It is preferable to perform rapid heat treatment (RTA) in parallel after the solid phase crystallization.

Next, as shown in FIGS. 14 and 15, the island-shaped switching semiconductor 154a, the driving semiconductor 154b, and the impurities are photographed by etching the doped polycrystalline semiconductor layer 160b and the polycrystalline semiconductor layer 150b. Doped polycrystalline semiconductors 164a and 164b are formed.

Next, as illustrated in FIGS. 16 and 17, the conductive layer is stacked on the polycrystalline semiconductor layers 164a and 164b and the buffer layer 111 doped with impurities and photo-etched to switch the switching source electrode 173a and the end portion 179. The data line 171 including the (), the driving voltage line 172 including the driving source electrode 173b, the switching drain electrode 175a, and the driving drain electrode 175b are formed.

Subsequently, the polycrystalline semiconductors 164a and 164b doped with impurities may be dry-etched using the data line 171, the driving voltage line 172, the switching drain electrode 175a, and the driving drain electrode 175b as a mask to form a plurality of resistive pairs. The contact members 163a, 165a, 163b, and 165b are formed to expose a portion of the switching semiconductor 154a and the driving semiconductor 154b.

Next, as shown in FIGS. 18 and 19, a gate insulating layer 140 is stacked on the entire substrate.

Subsequently, the conductive layer is stacked on the gate insulating layer 140 and photo-etched to form the gate line 121 and the driving gate electrode 124b including the switching gate electrode 124a and the end portion 129.

Next, as shown in FIGS. 20 and 21, the protective layer 180 is stacked on the entire surface of the substrate and photo-etched to form a plurality of contact holes 181, 182, 184, 185a, and 185b.

Next, as shown in FIGS. 22 and 23, an ITO layer is stacked on the passivation layer 180 and then photo-etched to form the pixel electrode 191, the connection member 85, and the contact assistants 81 and 82. .

Next, as shown in FIGS. 10 and 11, after the photosensitive organic layer is coated on the pixel electrode 191, the connection member 85, the plurality of contact auxiliary members 81 and 82, and the passivation layer 180, exposure and development are performed. As a result, a partition 361 having a plurality of openings 365 is formed.

Subsequently, a light emitting member 370 including a hole transport layer (not shown) and a light emitting layer (not shown) is formed in the opening 365. The light emitting member 370 may be formed by a solution process or deposition, such as an inkjet printing method, among which an inkjet head (not shown) is moved and an opening ( Inkjet printing method of dropping the solution into the ink is preferred, followed by a drying step after the formation of each layer.

Finally, the common electrode 270 is formed on the partition 361 and the light emitting member 370.

As described above, according to the exemplary embodiment of the present invention, the amorphous semiconductor layer is first crystallized and then patterned to form a plurality of island-like semiconductors. In this case, since the substrate is fixed by the amorphous semiconductor layer formed on the entire surface of the substrate and the amorphous semiconductor layer doped with impurities in the crystallization step, the substrate may be prevented from shrinking or expanding by the heat applied during the crystallization.

In addition, according to an embodiment of the present invention, since the amorphous semiconductor layer is first crystallized and a conductive layer such as a gate line or a data line is formed, the gate line or the data line may be prevented from being melted by the heat applied during the crystallization. Therefore, there is no limitation in using a low melting conductor such as aluminum as the material of the gate line or the data line.

In addition, unlike conventional polycrystalline thin film transistor processes, no additional steps such as ion doping are required, thereby reducing manufacturing cost and manufacturing time.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

By including a polycrystalline semiconductor, it is possible to increase charge mobility and stability and to reduce manufacturing time and manufacturing cost according to the structure and process of the thin film transistor described above.

Claims (8)

A polycrystalline semiconductor formed on a substrate, A data line formed on the polycrystalline semiconductor and including a source electrode, A drain electrode formed on the polycrystalline semiconductor and facing the source electrode, A gate line formed on the source electrode and the drain electrode and including a gate electrode overlapping the polycrystalline semiconductor; A pixel electrode connected to the drain electrode, and An ohmic contact member positioned between the polycrystalline semiconductor and the source electrode and between the polycrystalline semiconductor and the drain electrode and having substantially the same planar shape as the polycrystalline semiconductor except between the source electrode and the drain electrode. Display device comprising a. In claim 1, And a buffer layer formed under the polycrystalline semiconductor. In claim 1, A light emitting member formed on the pixel electrode, and Common electrode formed on the light emitting member Display device further comprising. Sequentially depositing an amorphous semiconductor layer and an amorphous semiconductor layer doped with impurities on the substrate, Crystallizing the amorphous semiconductor layer and the amorphous semiconductor layer doped with the impurity, Patterning the crystallized semiconductor layer and the doped semiconductor layer to form a polycrystalline semiconductor and an ohmic contact layer, Forming a data line and a drain electrode including a source electrode on the ohmic contact layer; Etching the ohmic contact layer using the data line and the drain electrode as a mask to form a plurality of ohmic contacts; Forming a gate line including a gate electrode on the data line and the drain electrode, and Forming a pixel electrode connected to the drain electrode Method of manufacturing a display device comprising a. In claim 4, Crystallizing the amorphous semiconductor layer and the amorphous semiconductor layer doped with the impurity is performed by a solid phase crystallization method. In claim 5, And forming a gate insulating film on the entire surface of the substrate before forming the gate line. In claim 5, And forming a buffer layer on the entire surface of the substrate before the laminating the amorphous semiconductor layer. In claim 4, After forming the pixel electrode Forming an insulating film having an opening, Forming a light emitting member in the opening, and Forming a common electrode on the light emitting member and the insulating layer Method of manufacturing a display device further comprising.

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