KR20070119893A - Multilayer chip capacitor - Google Patents

Abstract

A multilayer chip capacitor is provided to prevent a short-circuit between external electrodes due to a solder by forming three electrodes at most on one side of a capacitor body. A multilayer chip capacitor includes a capacitor body, plural inner electrodes(201-204), and at least four external electrodes. Plural dielectric layers are laminated to form the capacitor body. The inner electrodes are separated from each other in the capacitor body by the dielectric layer. Each of the inner electrodes includes at least one lead. The external electrodes are formed on an outer surface of the capacitor body and connected to the inner electrodes through the leads. The number of the external electrodes formed on one side surface of the capacitor body is equal to or smaller than three.

Description

Multilayer Chip Capacitors

1A is an exploded perspective view illustrating an internal electrode structure of a conventional stacked chip capacitor.

FIG. 1B is a view illustrating an external shape of the stacked chip capacitor of FIG. 1A.

2 is a perspective view illustrating a state in which a conventional multilayer chip capacitor is mounted on a printed circuit board (PCB).

3 is a plan view illustrating a top surface of a stacked chip capacitor according to an exemplary embodiment of the present invention.

4 is a plan view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 3.

5 is a plan view illustrating a top surface of a stacked chip capacitor according to another exemplary embodiment of the present invention.

6 is a plan view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 5.

7 is a plan view showing a top surface of a stacked chip capacitor according to still another embodiment of the present invention.

FIG. 8 is a plane view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 7.

9 is a plan view illustrating a top surface of a stacked chip capacitor according to still another embodiment of the present invention.

FIG. 10 is a plan view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 9.

11 is a plan view illustrating a top surface of a stacked chip capacitor according to still another embodiment of the present invention.

FIG. 12 is a plan view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 11.

13 is a plan view illustrating an internal electrode structure according to various embodiments of the present disclosure.

<Description of the symbols for the main parts of the drawings>

100, 200, 300, 400, 500: Stacked Chip Capacitors

151-152, 251-254, 351-354, 451-454, 551-554: dielectric layer

101 to 102, 201 to 204, 301 to 304, and 401 to 404: internal electrodes

161a, 162a, 162b, 261a, 261b, 262a, 263a, 264a: lead

150, 250, 350, 450, 550: capacitor body

131-134, 231-236, 331-336, 431-438, 531-540: external electrode

TECHNICAL FIELD The present invention relates to stacked chip capacitors, and more particularly, to a highly reliable stacked chip capacitor which exhibits an appropriately reduced equivalent serial inductance (ESL) and is advantageous for miniaturization of decoupling capacitor elements.

Stacked chip capacitors are useful as decoupling capacitors for supplying stable voltages to high frequency circuits such as CPUs. As the speed of the CPU increases, the power required to drive increases, requiring a larger number of stacked chip capacitors for decoupling. In addition, with the development of portable electronic devices (portable devices) and the miniaturization of the CPU, the mounting area of the stacked chip capacitor is limited. Smaller capacitors are advantageous for mounting multiple stacked chip capacitors in a limited mounting area. Smaller capacitors also reduce ESL, making miniaturized capacitors more reliable to power the CPU. U. S. Patent No. 5,880, 925 discloses an internal electrode structure capable of implementing low ESL.

However, when the size of the stacked chip capacitor is smaller, the area of the external electrode must be smaller, so that a uniform external electrode forming process (that is, uniform application of the external electrode paste) becomes very difficult. In addition, when the distance between the external electrodes is close to the CPU circuit board, the adjacent external electrodes may be connected by solder to cause short defects.

FIG. 1A is an exploded perspective view illustrating an internal electrode structure of a conventional stacked chip capacitor, and FIG. 1B is a view illustrating an appearance of the stacked chip capacitor of FIG. 1A. Referring to FIG. 1A, internal electrodes 14 are formed on dielectric layers 11a and 11b. The internal electrode 14 is divided into a first internal electrode 12 and a second internal electrode 13 having different polarities. The first internal electrode 12 and the second internal electrode 13 are alternately stacked alternately with each other to form a capacitor body (see 50 in FIG. 1B). Each of the internal electrodes 12, 13 has four leads 16, 17, and the leads 16 of the first internal electrode 12 are adjacent to the leads 17 of the second internal electrode 13. It is arranged in a bare array.

Referring to FIG. 1B, external electrodes 31 and 32 are formed on the side surface of the capacitor body 50. As shown, 'four' external electrodes are disposed on each side of the two sides of the main body 50 facing each other. Each of the internal electrodes 12, 13 is connected to the external electrodes 31, 32 via leads 16, 17.

FIG. 2 is a diagram illustrating a state in which the stacked chip capacitor 10 of FIG. 1B is mounted on a submount such as a PCB. Referring to FIG. 2, the capacitor 10 is mounted on a PCB 80 having a conductive path (not shown), so that external electrodes 31 and 32 of the capacitor 10 are connected to the conductive path. . Solders 41 and 42 are used to connect the external electrodes 31 and 32 to the conductive paths, and are heterogeneous by the solders 41 and 42 when the distance d between adjacent external electrodes 31 and 32 is narrow. The external electrodes 31 and 32 of polarity may be shorted. The risk of such a short failure increases as the size of the capacitor 10 decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a high reliability stacking chip capacitor for decoupling, which is advantageous for miniaturization of the device and has an appropriately reduced ESL.

In order to achieve the above technical problem, the stacked chip capacitor according to the present invention,

A capacitor body formed by stacking a plurality of dielectric layers;

A plurality of internal electrodes separated by the dielectric layer in the capacitor body, each of the internal electrodes having one or more leads;

At least four external electrodes formed on an outer surface of the capacitor body and connected to the internal electrodes through the leads,

Three or less external electrodes are formed on one side of the capacitor body.

According to an aspect of the present invention, the plurality of internal electrodes are divided into a plurality of first internal electrodes and a second internal electrode which are repeatedly stacked alternately with each other, and each of the internal electrodes includes two leads extending from opposite sides facing each other. The lead of the first internal electrode is disposed adjacent to the lead of the second internal electrode. In this case, the capacitor is a four-terminal capacitor having a total of four external electrodes, and has two external electrodes on each of two opposite sides of the capacitor body. The lead of one side of the opposite side may be offset with respect to the lead of the other side.

According to another aspect of the present invention, four internal electrodes arranged up and down adjacently and having different electrode patterns form one block, and the blocks are repeatedly stacked in succession up and down.

In one embodiment, the stacked chip capacitor may be a six-terminal capacitor having a total of six external electrodes. In this case, three external electrodes may be disposed on each of two opposite sides of the capacitor body. Alternatively, two external electrodes may be disposed on each of two opposite sides of the capacitor body, and one additional external electrode may be disposed on each of the remaining two sides. Each of the internal electrodes can have one or two leads.

In another embodiment, the stacked chip capacitor may be an eight-terminal capacitor having a total of eight external electrodes. In this case, three external electrodes may be disposed on each of two opposite sides of the capacitor body, and one additional external electrode may be disposed on each of the remaining two sides. Each of the internal electrodes can have one or two or three leads.

In another embodiment, the stacked chip capacitor may be a 10-terminal capacitor having a total of 10 external electrodes. In this case, three external electrodes may be disposed on each of two opposite sides of the capacitor body, and two additional external electrodes may be disposed on each of the remaining two sides. Each of the internal electrodes can have one or two or three leads.

According to the invention, there are at most three external electrodes on one side of the capacitor body. Therefore, even if the size of the capacitor element is small, it is possible to effectively suppress the short failure phenomenon between the external electrodes due to the solder generated in the conventional capacitor (see FIGS. 1A, 1B and 2). In addition, the application process of the external electrode (application of the conductive paste material for forming the external electrode, etc.) during the capacitor manufacturing process becomes very easy. This makes it suitable for device miniaturization and low ESL.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.

3 is a plan view illustrating a top surface of a stacked chip capacitor according to an exemplary embodiment of the present invention, and FIG. 4 is a plan view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 3.

First, referring to FIG. 3, the stacked chip capacitor 100 has a capacitor body 150 and four external electrodes 131, 132, 133, and 134 formed on an outer surface thereof (ie, corresponding to a 4-terminal capacitor). Two external electrodes 131 and 132 or 133 and 134 having different polarities are formed on each of the two opposite sides of the capacitor body 150. The capacitor body 150 is formed by stacking dielectric layers (see 151 and 152 of FIG. 4). The main body 150 has a rectangular parallelepiped shape, and the aspect ratio (vertical / horizontal = A / B) is smaller than 1 as shown. In the main body 150, a plurality of internal electrodes are separated by a dielectric layer.

As shown, only two external electrodes 131 to 134 are disposed on one surface of the capacitor body 150. Therefore, even if the size of the capacitor A × B is small (particularly, the length of the long side B is small), the distance D between the adjacent external electrodes 131 and 132 or 133 and 134 is determined. We can secure enough. Therefore, it is possible to suppress the difficulty of the external electrode forming process and the short defect occurring between adjacent external electrodes (see FIG. 2), which have been a problem in the past.

As CPUs become smaller and faster, the size of stacked chip capacitors for decoupling is becoming smaller. In addition, small stack chip capacitors are advantageous for low ESL implementation. Therefore, in order to suppress the application process of the external electrode and the short defect between the external electrodes, securing a sufficient distance D between the adjacent external electrodes 131 and 132 or 133 and 134 is critically required. The present invention provides the advantages of meeting these needs.

4 is a plan view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 3. Referring to FIG. 4, a first internal electrode 101 and a second internal electrode 102 are formed on each of the dielectric layers 151 and 152. The first internal electrode 101 and the second internal electrode 102 are separated by the dielectric layers 151 and 102, and are repeatedly stacked alternately with each other in the capacitor body (see 150 in FIG. 3). Polarities of the first internal electrode 101 and the second internal electrode 102 are opposite to each other.

Referring to FIG. 4A, the first internal electrode 101 has two leads 161a and 161b extending from side surfaces (long sides) facing each other. Through these leads 161a and 161b, the first internal electrode 101 is connected to the corresponding external electrode (see 131 and 133 of FIG. 3). In particular, the lead 161a extending to one side is offset from the lead 161b extending to the other side.

Referring to FIG. 4B, the second internal electrode 102 has two leads 162a and 162b extending from side surfaces (long sides) facing each other. Through these leads 162a and 162b, the first internal electrode 102 is connected to the corresponding external electrode (see 132 and 134 in Fig. 3). In particular, the lead 162a extending to one side is offset with respect to the lead 162b extending to the other side.

As shown in FIG. 4, in the capacitor body, the leads 161a and 161b of the first internal electrode 101 are disposed adjacent to the leads 162a and 162b of the second internal electrode 102. As the leads of different polarities are arranged adjacent to each other, currents in different directions (see arrows) flow in the leads of different polarities adjacent to each other (eg, 161a and 162a). As a result, the magnetic flux is canceled in adjacent leads of different polarities (eg, 161a and 162a), and the ESL of the entire capacitor is reduced.

The embodiment described above is a four terminal capacitor having only two types of internal electrode patterns (ie, first and second internal electrodes), but the present invention is not limited thereto. The invention can also be applied to a six-terminal, eight-terminal, or ten-terminal capacitor, examples of which are shown in FIGS. In the embodiments shown in Figs. 5 to 13, four internal electrodes arranged up and down adjacently and having different electrode patterns form one block, and the blocks are repeatedly stacked 'up and down' successively.

In the present specification, the term 'other' electrode pattern corresponds to a case in which the rotational position of the electrode pattern with respect to the vertical axis is different even if the shape of the electrode pattern is different as well as the shape of the electrode pattern is the same. In addition, in this specification, "blocks are successively" repeated "stacked" means that the same blocks are stacked in succession. Therefore, one block is repeated up and down as it is without rotation or inversion, thereby forming the entire internal electrode arrangement.

5 is a plan view illustrating a top surface of a stacked chip capacitor according to another exemplary embodiment of the present invention, and FIG. 6 is a plan view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 5.

Referring to FIG. 5, the stacked chip capacitor 200 may include a capacitor body 250 and six external electrodes 231 to 236 formed on the outer surface thereof, thus corresponding to the six-terminal capacitor. Three external electrodes are formed on each of the two opposite sides of the capacitor body 250. On each side, external electrodes of different polarities are alternately arranged. The main body 250 is formed by stacking dielectric layers (see reference numerals 251 to 254 of FIG. 6).

As shown, only three external electrodes 231 to 236 are disposed on one side of the capacitor body 250. Therefore, even if the capacitor is miniaturized, the distance D between the adjacent external electrodes (eg, 236 and 235) can be sufficiently secured. Therefore, it is possible to suppress the difficulty of the external electrode forming process and the short defect generation between adjacent external electrodes, which has been a problem in the past.

Referring to FIGS. 6A to 6D, four internal electrodes 201 to 204 formed on the dielectric layers 251 to 254 are sequentially stacked to form one block. In this case, the four internal electrodes 201 to 204 have different electrode patterns. The blocks are repeatedly stacked in succession up and down to form a capacitor body (see reference numeral 250 in FIG. 5).

Referring to FIGS. 6A to 6D, each of the internal electrodes 201 to 204 formed on the dielectric layers 251 to 254 has one or two leads. Reference numerals 261a, 261b, 262a, 263a, and 264a denote the leads of the corresponding internal electrodes, respectively. Each internal electrode 201-204 is connected to its external electrode (see 231-236 in FIG. 5) through its lead. The internal electrodes 201 to 204 are separated by the dielectric layers 251 to 254 within the body 250, and internal electrodes having different polarities are alternately stacked.

6A to 6D illustrate an example of an internal electrode structure capable of implementing the capacitor of FIG. 5. Therefore, in order to implement the capacitor of FIG. 5, an internal electrode having an electrode pattern different from that of the electrode patterns illustrated in FIGS. 6A to 6D may be used, and another arrangement method may be adopted.

7 is a plan view illustrating a top surface of a stacked chip capacitor according to still another embodiment of the present invention, and FIG. 8 is a plan view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 7. Although this embodiment also shows a six-terminal capacitor, it differs from the embodiment of FIG. 5 in the position of an external electrode.

Referring to FIG. 7, the stacked chip capacitor 300 has a capacitor body 350 and six external electrodes 331 ˜ 336 formed on an outer surface thereof (therefore, corresponding to a six terminal capacitor). Two external electrodes are formed on each of the two opposite sides of the capacitor body 350, and one additional external electrode is disposed on each of the remaining two sides. The main body 350 is formed by stacking dielectric layers (see 351 to 354 of FIG. 8).

As shown, at most two external electrodes 331 ˜ 336 are disposed on one surface of the capacitor body 350. Therefore, even if the capacitor is miniaturized, it is possible to sufficiently secure the distance between the external electrodes (eg, 336 and 335) adjacent to each other. Therefore, it is possible to suppress the difficulty of the external electrode forming process and the short defect generation between adjacent external electrodes, which has been a problem in the past.

Referring to FIGS. 8A to 8D, four internal electrodes 301 to 304 formed on the dielectric layers 351 to 354 are sequentially stacked to form one block. In this case, the four internal electrodes 301 to 304 have different electrode patterns. This block is repeatedly stacked in succession up and down to form a capacitor body (see 350 in FIG. 7).

Referring to FIGS. 8A to 8D, each of the internal electrodes 301 to 304 formed on the dielectric layers 351 to 354 has one or two leads. Reference numerals 361a, 361b, 362a, 362b, 363a, and 364a denote the leads of the corresponding internal electrodes, respectively. Each inner electrode 301-304 is connected to the corresponding outer electrode (refer to reference numerals 331-336 of FIG. 7) through its lead. The internal electrodes 301 to 304 are separated by the dielectric layers 351 to 354 in the body 350, and internal electrodes having different polarities are alternately stacked. FIG. 8 illustrates an example of an internal electrode structure of the capacitor of FIG. 7, and another electrode pattern or an internal electrode arrangement may be used to implement the capacitor of FIG. 7.

9 is a plan view illustrating a top surface of a stacked chip capacitor according to still another embodiment of the present invention, and FIG. 10 is a plan view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 9.

Referring to FIG. 9, the stacked chip capacitor 400 may include a capacitor body 450 and eight external electrodes 431 to 438 formed on an outer surface thereof, thus corresponding to an eight-terminal capacitor. Three external electrodes are formed on each of the two opposite sides of the capacitor body 450, and one additional external electrode is disposed on each of the remaining two sides. The main body 450 is formed by stacking dielectric layers (see reference numerals 451 to 454 in FIG. 10).

As shown, three external electrodes 431 to 438 are disposed on one side of the capacitor body 450 and one on the neighboring side. Therefore, even if the capacitor is miniaturized, the distance between the external electrodes (for example, 437 and 436) adjacent to each other can be sufficiently secured. Therefore, it is possible to suppress the difficulty of the external electrode forming process and the short defect generation between adjacent external electrodes, which has been a problem in the past.

Referring to FIGS. 10A to 10D, four internal electrodes 401 to 404 formed on the dielectric layers 451 to 454 are sequentially stacked to form one block. In this case, the four internal electrodes 401 to 404 have different electrode patterns. This block is repeatedly stacked in succession up and down to form a capacitor body (see 450 in FIG. 9).

Referring to FIGS. 10A to 10D, each of the internal electrodes 401 to 404 formed on the dielectric layers 451 to 454 has one, two, or three leads. Reference numerals 461a, 461b, 461c, 462a, 462b, 463a, 464a, and 464b denote the leads of the corresponding internal electrodes, respectively. Each inner electrode 401-404 is connected to the corresponding outer electrode (see reference numerals 431-438 in FIG. 9) through its lead. The internal electrodes 401 to 404 are separated by the dielectric layers 451 to 454 in the body 450, and internal electrodes having different polarities are alternately stacked. FIG. 10 illustrates an example of an internal electrode structure of the capacitor of FIG. 9, and another electrode pattern or an internal electrode arrangement may be used to implement the capacitor of FIG. 9.

11 is a plan view illustrating a top surface of a stacked chip capacitor according to still another embodiment of the present invention, and FIG. 12 is a plan view illustrating an example of an internal electrode structure of the stacked chip capacitor of FIG. 11.

Referring to FIG. 11, the stacked chip capacitor 500 has a capacitor body 550 and ten external electrodes 531 to 540 formed on an outer surface thereof (therefore, corresponding to a 10 terminal capacitor). Three external electrodes are formed on each of the two opposite sides of the capacitor body 550, and two additional external electrodes are disposed on each of the remaining two sides. The main body 550 is formed by stacking dielectric layers (see 551 to 554 in FIG. 12).

As shown, three external electrodes 531 to 540 are disposed on one side of the capacitor body 550 and two on the neighboring side. Therefore, even if the capacitor is miniaturized, the distance between the adjacent external electrodes (eg, 538 and 537) can be sufficiently secured. Therefore, it is possible to suppress the difficulty of the external electrode forming process and the occurrence of short defects between adjacent external electrodes, which has become a problem in the past.

Referring to FIGS. 12A to 12D, four internal electrodes 501 to 504 formed on the dielectric layers 551 to 554 are sequentially stacked to form one block. In this case, the four internal electrodes 501 to 504 have different electrode patterns. This block is repeatedly stacked in succession up and down to form a capacitor body (see 550 in FIG. 11).

12A to 12D, each of the internal electrodes 501 to 504 formed on the dielectric layers 551 to 554 has one, two, or three leads. Reference numerals 561a, 561b, 561c, 562a, 562b, 563a, 563b, 564a, 564b, and 564c denote the leads of the corresponding internal electrodes, respectively. Each inner electrode 501 to 504 is connected to the corresponding outer electrode (see 531 to 540 in Fig. 11) through its lead. The internal electrodes 501 to 504 are separated by the dielectric layers 551 to 554 in the body 550, and internal electrodes having different polarities are alternately stacked.

FIG. 12 illustrates an example of an internal electrode structure of the capacitor of FIG. 11, and an electrode pattern or an internal electrode arrangement scheme according to another example may be used to implement the capacitor of FIG. 11.

13 (a) to 13 (c) show other examples of the internal electrode structure that can be applied to the 10-terminal stacked chip capacitor shown in FIG. In the three examples shown in Figs. 13A to 13C, four internal electrodes having different electrode patterns are arranged vertically adjacent to each other to form one block. The blocks are arranged vertically and vertically to form the main body of the capacitor (see 550 in Fig. 11). To implement the 10-terminal stacked chip capacitor of FIG. 11, other internal electrode structures other than the embodiment shown in FIG. 13 may be used.

The present invention is not limited by the above-described embodiment and the accompanying drawings, but is intended to be limited by the appended claims, and various forms of substitution, modification, and within the scope not departing from the technical spirit of the present invention described in the claims. It will be apparent to those skilled in the art that changes are possible.

As described above, according to the present invention, there are at most three external electrodes on one side of the capacitor body. Therefore, even if the size of a capacitor element is small, the short defect phenomenon between external electrodes by solder at the time of mounting on a PCB can be suppressed effectively. In addition, the coating process of the external electrode in the capacitor manufacturing process is very easy. This makes it suitable for device miniaturization and low ESL. As a result, a large number of decoupling capacitors can be mounted with a high reliability in a limited mounting area, and high power power can be supplied more stably to high frequency circuits such as a CPU.

Claims (15)

A capacitor body formed by stacking a plurality of dielectric layers; A plurality of internal electrodes separated by the dielectric layer in the capacitor body, each of the internal electrodes having one or more leads; And At least four external electrodes formed on an outer surface of the capacitor body and connected to the internal electrodes through the leads, Stacked chip capacitors, characterized in that no more than three external electrodes on one side of the capacitor body. The method of claim 1, The plurality of internal electrodes may be divided into a plurality of first internal electrodes and a second internal electrode repeatedly stacked alternately with each other, and each of the internal electrodes may have two leads extending from opposite sides of the first internal electrode. And a lead disposed adjacent to the lead of the second internal electrode. The method of claim 2, The stacked chip capacitor is a four-terminal capacitor, and the stacked chip capacitor, characterized in that it has two external electrodes on each of the two opposite sides of the capacitor body. The method of claim 2, The lead of one side of the opposite side of the stacked chip capacitor, characterized in that offset with respect to the lead of the other side. The method of claim 1, 4. The stacked chip capacitor of claim 4, wherein four internal electrodes arranged up and down adjacent to each other and having different electrode patterns form one block, and the blocks are repeatedly stacked in succession up and down. The method of claim 5, The multilayer chip capacitor is a multilayer chip capacitor, characterized in that the six-terminal capacitor. The method of claim 6, Stacked chip capacitors, characterized in that three external electrodes are disposed on each of the two opposite sides of the capacitor body. The method of claim 6, Two external electrodes are disposed on each of the two opposite sides of the capacitor body, and one additional external electrode is disposed on each of the remaining two sides. The method of claim 6, And each of the internal electrodes has one or two leads. The method of claim 5, The multilayer chip capacitor is a multilayer chip capacitor, characterized in that the eight-terminal capacitor. The method of claim 10, Three external electrodes are disposed on each of the two opposite sides of the capacitor body, and one additional external electrode is disposed on each of the remaining two sides. The method of claim 10, Stacked chip capacitors, characterized in that each internal electrode has one, two or three leads. The method of claim 5, The multilayer chip capacitor is a multilayer chip capacitor, characterized in that the 10-terminal capacitor. The method of claim 13, And three external electrodes on each of two opposite sides of the capacitor body, and two additional external electrodes on each of the remaining two sides. The method of claim 13, And each of the internal electrodes has one, two, or three leads.

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