KR20070110263A - Circuits including switches for electronic devices and methods of using the electronic devices - Google Patents

Abstract

A circuit for an electronic device includes a select unit, a data holder unit, an electronic component, a transistor, and a switch. The control terminal of the switch is coupled to a first select line, the first terminal of the switch is connected to a first electrode of the electronic component, and the second terminal of the switch is connected to a reference voltage line. A method of using an electronic component that includes such a circuit includes writing data to a pixel and driving the electronic component. The select unit and the switch are configured to turn on at substantially a same time, and the select unit and the switch are configured to turn off at substantially a same time during writing and driving, respectively.

Description

CIRCUITS INCLUDING SWITCHES FOR ELECTRONIC DEVICES AND METHODS OF USING THE ELECTRONIC DEVICES}

TECHNICAL FIELD The present invention generally relates to circuits and electronic devices, and more particularly, to circuits including switches for electronic devices and methods of using such electronic devices.

Electronic devices, including organic electronic devices, continue to be used more widely in everyday life. Examples of organic electronic devices include organic light-emitting diodes (OLEDs). Active Matrix OLED (AMOLED) displays include pixels, each with its own pixel circuit. A large number of pixel circuits have been proposed. The basic circuit design includes a two-transistor, one-capacitor (2T-1C) design. This transistor can be n-channel, p-channel, or a combination thereof. One transistor is a selection transistor and the other transistor is a driving transistor. In general, the transistor is a thin-film transistor (TFT). The TFT and the organic active layer deteriorate with time.

One pixel design proposed to compensate for this degradation involves adding another transistor in series with the drive transistor. In some instances, where an n-channel transistor is used, the additional transistor has its drain region connected to the _Vdd power line and its source region connected to the drain region of the drive transistor. The source region of the drive transistor is connected to the anode of the OLED and the cathode of the OLED is connected to the V _ss power line. While on, additional transistors add resistance to the conduction path through the drive transistor and the OLED. The added resistance increases power consumption and generates more heat that must be dissipated without increasing the emission intensity of the OLED.

1 illustrates a pixel circuit 100 and FIG. 2 illustrates a corresponding timing diagram for the pixel circuit of FIG. 1. Referring to FIG. 1, this pixel circuit includes a select transistor 102, a capacitor 104, a drive transistor 106 and an OLED 108, which are constructed similarly to the 2T-1C pixel circuit. Node 105 is between select transistor 102 and drive transistor 106. The driving transistor 106 is a double-gated transistor, and the third transistor 122 has its drain connected to the node 107. The voltages for V _dd , V _ss , and signal line 162 are at approximately constant voltages. For example, V _dd may be approximately + 13V, V _ss may be approximately −5V, and signal line 162 may be at approximately −12V.

This timing diagram shows the voltage of a selected portion of the circuit for one frame time. The first part of the frame time is used to adjust the voltage in the circuit, the second part is used to write data to the pixel, and the third part allows the pixel (ie OLED) to emit.

During the first portion of the frame time, the top gate (TG) 166 of the drive transistor 106 goes into a low-state (eg, a negative voltage), which turns off the drive transistor 106, That is, no significant current flows from its drain to its source. Select line (SL) 142 is turned on to activate select transistor 102 for the entire row of the display panel, and signal line (G) 164 is turned on to turn on third transistor 122. Activate. The voltages at nodes 105 and 107 are clamped to the voltages of data line (DL) 144 and signal line 162 respectively. The voltage across capacitor 104 is thus the voltage difference between DL 144 and signal line 162. After a period of time, the upper gate (TG) 166 goes high (eg, zero or positive potential) and the signal (G) 164 goes off to deactivate the third transistor 122. . The voltage V _C across the electrode of the capacitor 104 is reduced and the voltage at the node 107 is increased to stabilize at a voltage equal in magnitude but opposite in polarity to the threshold voltage of the driving transistor 106. For example, when the threshold voltage of the driving transistor 106 is 2V, the voltage of the node 107 is less than 2V.

During the second part, data is written to the pixel. The signal on the DL 144 is sent to the node 105. SL 142 receives the on pulse for a relatively short time. TG 166 is off-state, so no significant current flows through drive transistor 106, and node 107 is at its potential (eg, less than 2V). During the third part (after this third part, all data has been recorded for all rows (or for all columns, depending on the layout orientation)), the TG 166 is in a high state (zero or positive potential). While activating the drive transistor 106, while the transistor 102 is in the off-state and keeps the node 105 separated from the DL 144. OLED 108 emits due to the current defined by (V _{node 105} -V _{node 107} -V _{th - OLED} ) during the recording period.

The pixel circuit 100 suffers from at least one or both of two problems: low intensity and having to drive the electronic circuit more strongly. A separate voltage regulation step is used. This adjustment step biases a portion of the pixel circuit 100 so that the OLED 108 no longer emits radiation until all data has been written to the array (until the end of the second portion). The time the array emits is less than half the frame time. Although the various periods are generally shorter than the period that a person can visually respond, the user may perceive the display to be darker, or the OLED 108 may be more during radiation to make the display appear to have the appropriate emission intensity. It may have to be driven strongly. Driving the OLED 108 more strongly increases the rate of degradation of the drive transistor 106, the organic layer within the OLED 108, or both.

The circuit for an electronic device includes a selection unit including a control terminal, a first terminal, and a second terminal. The control terminal is connected to a first selection line and the first terminal of the selection unit is connected to a data line. The circuit also includes a data holder unit comprising a first terminal and a second terminal. The first terminal of the data holder unit is connected to the second terminal of the selection unit. The circuit also includes an electronic device comprising a first electrode and a second electrode, which is connected to a first power line. The circuit also includes a transistor comprising a first gate electrode, a first source / drain region, and a second source / drain region. The first gate electrode is connected to the first terminal of the data holder unit and the second terminal of the selection unit. The first source / drain region is connected to a first electrode of the electronic device and coupled to a second terminal of the data holder unit. The second source / drain region is connected to a second power line. Within the circuit, the transistor is the only transistor in which both its source / drain regions are in the conduction path between the first power line and the second power line. The circuit also includes a switch comprising a control terminal, a first terminal, and a second terminal. The control terminal of the switch is connected to the first selection line, the first terminal of the switch is connected to a first electrode of the electronic element, and the second terminal of the switch is connected to a reference voltage line. The selection unit and the switch are configured to turn on at about the same time, and the selection unit and the switch are configured to turn off at about the same time.

A method of using an electronic device, the electronic device comprising: a selection unit connected to a selection line and a data line; A data holder unit connected to the selection unit; An electronic device connected to a first power supply line, and a transistor connected to the data holder unit, the selection unit, and the electronic device and coupled to a second power supply line; And a switch coupled to the select line and coupled to the electronic device and a reference voltage line. The transistor includes a first source / drain region and a second source / drain region. Within a pixel, the transistor is the only transistor in which both its source / drain regions are in the conduction path between the first power line and the second power line. The method of using an electronic device including the pixel includes writing data to the pixel. Writing the data includes turning on the selection unit and the switch at about the same time, and turning off the transistor. The method also includes driving the electronic device. Driving the electronic device includes turning off the selection unit and the switch at about the same time, and turning on the transistor.

The foregoing general description and the following detailed description are exemplary and explanatory only and do not limit the invention as defined in the appended claims.

1 and 2 are circuit diagrams and timing diagrams for pixel circuits.

3 and 5 are timing diagrams for circuits and circuits including switches in accordance with one embodiment of the present invention.

4 is a circuit diagram of a circuit including a switch according to an alternative embodiment of the present invention.

6-14 are cross-sectional views of double gate TFTs that can be used as drive transistors in the pixel circuit of FIG.

15 and 16 are plan views of adjacent pixels connected to different select lines (terminals of switches associated with pixels connected to one select line connected to the other select line).

The invention is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

Those skilled in the art will appreciate that elements in the figures are shown for simplicity and clarity and are not drawn to scale. For example, the size of any of the components in the figures may be enlarged with respect to other components to help enhance understanding of embodiments of the present invention.

The circuit for an electronic device includes a selection unit including a control terminal, a first terminal, and a second terminal. The control terminal is connected to a first selection line and the first terminal of the selection unit is connected to a data line. The circuit also includes a data holder unit comprising a first terminal and a second terminal. The first terminal of the data holder unit is connected to the second terminal of the selection unit. The circuit also includes an electronic device comprising a first electrode and a second electrode, which is connected to a first power line. The circuit also includes a transistor comprising a first gate electrode, a first source / drain region, and a second source / drain region. The first gate electrode is connected to the first terminal of the data holder unit and the second terminal of the selection unit. The first source / drain region is connected to a first electrode of the electronic device and coupled to a second terminal of the data holder unit. The second source / drain region is connected to a second power line. Within the circuit, the transistor is the only transistor in which both its source / drain regions are in the conduction path between the first power line and the second power line. The circuit also includes a switch comprising a control terminal, a first terminal, and a second terminal. The control terminal of the switch is connected to the first selection line, the first terminal of the switch is connected to a first electrode of the electronic element, and the second terminal of the switch is connected to a reference voltage line. The selection unit and the switch are configured to turn on at about the same time, and the selection unit and the switch are configured to turn off at about the same time.

In another embodiment, the transistor includes a second gate electrode coupled to the signal line. In another embodiment, the second terminal of the data holder unit is connected to the first electrode of the electronic element. In a more specific embodiment, the second source / drain region of the transistor is connected to the second power line.

In another embodiment, the channel region of the transistor is formed using a-Si, CGS, LTPS, or a combination thereof. In another embodiment, each of the selection unit and the switch comprises a transistor. In another embodiment, the control terminal of the switch is connected to the first selection line.

In another embodiment, the circuit further includes a second selection line different from the first selection line, wherein the reference voltage line is the second selection line. In another embodiment, the reference voltage line and the first power line are at approximately the same potential. In a more specific embodiment, this circuit further includes an inverter having an input terminal and an output terminal. The input terminal is connected to the first selection line, and the output terminal is connected to the control terminal of the switch.

In another embodiment, the reference voltage line is configured to be at a voltage such that no significant current flows through the electronic device when the switch is closed.

In another embodiment, the electronic device comprises a pixel array, each pixel comprising the circuitry. In another embodiment, the organic electronic device includes the circuit.

A method of using an electronic device, the electronic device comprising: a selection unit connected to a selection line and a data line; A data holder unit connected to the selection unit; An electronic device connected to a first power supply line, and a transistor connected to the data holder unit, the selection unit, and the electronic device and coupled to a second power supply line; And a switch coupled to the select line and coupled to the electronic device and a reference voltage line. The transistor includes a first source / drain region and a second source / drain region. Within a pixel, the transistor is the only transistor in which both its source / drain regions are in the conduction path between the first power line and the second power line. The method of using an electronic device including the pixel includes writing data to the pixel. Writing the data includes turning on the selection unit and the switch at about the same time, and turning off the transistor. The method also includes driving the electronic device. Driving the electronic device includes turning off the selection unit and the switch at about the same time, and turning on the transistor.

In another embodiment, the transistor includes a first gate electrode connected to the selection unit and a second gate electrode connected to a signal line. Turning off the transistor includes transmitting a signal along the signal line to the second gate electrode, the signal having a voltage sufficient to turn off the transistor. In another embodiment, the switch has a control terminal connected to the select line. In a more specific embodiment, the switch has a first terminal connected to a first electrode of the electronic device, and the switch has a second terminal connected to a second electrode or another selection line of the electronic device.

In another embodiment, the switch is connected to only one pixel. In another embodiment, during writing, a significant amount of charge is dissipated across the electronic device. In another embodiment, the electronic device includes an organic active layer.

In another embodiment, the selection unit and the switch are configured to turn on at about the same time, and the selection unit and the switch are configured to turn off at about the same time. In another embodiment, the frame time is the sum of the write time for writing data and the drive time for driving the electronic device, wherein the drive time is at least one half of the frame time.

In another embodiment, the electronic device does not emit a significant amount of radiation during writing.

This detailed description first describes definitions and explanations of terms, followed by circuit diagrams, timing diagrams, dual-gate TFTs, other physical layout considerations, other embodiments, and finally advantages.

1. Definition and Explanation of Terms

Before referring to the details of the embodiments described below, some terms are defined or explained. The term "amorphous silicon (a-Si)" is intended to mean one or more layers of silicon that do not have a distinguishable crystal structure.

The terms "array", "peripheral circuit" and "remote circuit" are intended to mean different regions or components of an electronic device. For example, an array can include pixels, cells, or other structures within an ordered arrangement (usually designated columns and rows). Pixels, cells, or other structures within the array may be controlled locally by peripheral circuitry that may be on the same substrate as the array but external to the array itself. The remote circuit is generally remote from the peripheral circuitry and can send signals to or receive signals from the array (typically through the peripheral circuit). The remote circuit can also perform functions independent of the array. The remote circuit may or may not be on the substrate having the array.

The term "black layer" is intended to mean a layer that transmits only about 10% of the radiation at the target wavelength or spectrum.

The term "capacitive electronic device" is intended to mean an electronic device configured to function as a capacitor when shown in the circuit diagram. Examples of capacitive electronic devices include capacitor or transistor structures.

The term "charge carrier" is intended to mean the smallest unit of charge in the context of an electronic device or circuit. Charge carriers may include n-type charge carriers (eg, electrons or negatively charged ions), p-type charge carriers (eg, hole or positively charged ions), or any combination thereof. Can be.

The term "channel region" is intended to mean the region between the source / drain regions of the field effect transistor, and the biasing of this channel region through the gate electrode of the field effect transistor is a carrier or flow of carrier between the source / drain regions. Affects the lack of

The term " circuit " is intended to mean, in its entirety, an assembly of electronic devices which, when properly connected to and supplied with a suitable potential (s), perform a function. The TFT driving circuit for the organic electronic element is an example of a circuit.

The term "conductive path" is intended to mean the part of the circuit through which the charge carriers can flow. The source / drain regions of the transistors follow the conduction path, because when the transistors are on, electrons, holes or both can flow between them. Note that the gate electrode does not follow this conducting path because the charge carriers cannot pass through the gate dielectric layer of the transistor.

The term "connected", with respect to an electronic device, a circuit, or a portion thereof, means that any combination of two or more electronic devices, circuits or at least one electronic device and at least one circuit does not have any intermediate electronic device between them. It is to mean that. Parasitic resistance, parasitic capacitance, or both are not considered electronic devices for the purposes of this definition. In one embodiment, the electronic elements are connected when they are electrically shorted to each other and at about the same voltage. Note that these electronic devices can be connected to each other using optical fiber lines to allow optical signals to be transmitted between the electronic devices.

The term "CGS" (continuous grain silicon) is intended to mean polysilicon of the type in which the individual crystals are oriented in a direction parallel to the channel length of the field effect transistor. Oriented crystals reduce the frequency at which charges meet grain boundaries, resulting in higher overall mobility of the channel region compared to randomly oriented polysilicon channels.

The term "coterminous" is intended to mean having the same or coincident boundaries.

The term "coupled" means two or more electronic devices, circuits, systems or (1) at least one electronic device, such that a signal (eg, current, voltage, or optical signal) can be transmitted from one side to the other; (2) at least one circuit, or (3) any combination of at least one system. Non-limiting examples of “coupled” include electronic device (s), circuit (s), or electronic device (s) or circuits having switch (s) (eg, transistor (s)) connected therebetween. It may include a direct link between the (s).

The term "data holder unit" is intended to mean an electronic device or a collection of electronic devices configured to hold data at least temporarily. The image holder unit is an example of a data holder unit, where the data corresponds to at least a portion of the image.

The term "data line" is intended to mean a signal line having a main function of transmitting one or more signals containing information.

The term "effective gate width" is intended to mean the width of a portion of the conductor separated from the channel region only by the gate dielectric layer (s) of the field effect transistor. In one embodiment, the effective gate width is equal to the physical width of the conductor, and in other embodiments, the effective gate width is part of the conductor's physical width, but not all of it.

The term "electronic device" is intended to mean the lowest level unit of a circuit that performs an electrical function. Electronic devices may include transistors, diodes, resistors, capacitors, inductors, and the like. Electronic devices include parasitic resistance (e.g., resistance of wiring) or parasitic capacitance (e.g. capacitive coupling between two conductors connected to different electronic devices if a capacitor between the conductors is unintentional or accidental). I never do that.

The term “electronic device” as a whole is intended to mean a collection of circuits, organic electronic devices, or combinations thereof that, when properly connected to and supplied with a suitable voltage (s), perform their functions. The electronic device may include or be part of a system. Examples of electronic devices include displays, sensor arrays, computer systems, avionics systems, automobiles, cellular phones, other consumer or industrial electronics, and the like.

The term "field effect transistor" is intended to mean a transistor whose current transfer characteristics are affected by the voltage at the gate electrode. Field effect transistors are junction field effect transistors (JFETs) or metal-insulator-semiconductor field effect transistors (MISFETs) [metal-oxide-semiconductor field effect transistors (MOSFETs), metal-nitride- Oxide-semiconductor (MNOS) field effect transistors, and the like. The field effect transistor may be n-channel (n-type carriers flow in the channel region) or p-channel (p-type carriers flow in the channel region). Field effect transistors are enhancement-mode transistors (channel regions have different conductivity types compared to the source / drain regions of the transistors) or depletion-mode transistors (channels and sources / drains of the transistors). Regions have the same conductivity type).

The term "inverter" is intended to mean a circuit that receives an input signal in one of two binary states (0 or 1, low or high, false or true, etc.) and generates an output signal in the opposite state.

The term "LTPS" (low-temperature polysilicon) is intended to mean one or more polysilicon layers deposited or processed at a temperature no greater than 550 ° C. One example of a process for forming LTPS is Sequential Lateral Solidification (SLS), where a modified excimer laser crystallization (ELC) process is used to form larger size oriented grains, The result is higher mobility of the charge carriers compared to conventional ELC techniques forming LTPS.

The term “n + doped” or “p + doped” refers to a material, layer, or region when the metal-containing material or layer is in contact with such doped material, layer or region. It is intended to mean that such a material, layer or region comprises a sufficient amount of n-type or p-type dopant to form this ohmic contact. In one embodiment, the n + doped region has at least 1 × 10 ¹⁹ minus charged carriers / cm ³ .

The term "organic active layer" is intended to mean one or more organic layers, and at least one of these organic active layers, alone or when in contact with another material, may form a rectifying junction.

The term "organic electronic device" is intended to mean a device comprising one or more semiconductor layers or semiconductor materials. An organic electronic device is a device that (1) converts electrical energy into radiation (e.g., a light emitting diode, a light emitting diode display, a diode laser, or a lighting panel), and (2) an electronic process to Devices for detecting (e.g. photodetectors, photoconductive cells, photoresistors, optical switches, phototransistors, optical tubes, infrared (IR) detectors, or biosensors), (3) radiation to electrical energy Devices (eg, photovoltaic devices or solar cells), (4) devices (eg, transistors or diodes) comprising one or more electronic elements comprising at least one organic semiconductor layer, or item (1) ), But is not limited to any combination of the devices in (4). The term "physical channel length" is intended to mean the actual distance between the source / drain regions of a transistor.

The term "physical gate width" is intended to mean the actual width of the gate electrode of the transistor.

The term "pixel" is intended to mean a portion of an array corresponding to one electronic device and, if present, its corresponding electronic device (s) dedicated to that particular one electronic device. In one embodiment, the pixel has an OLED and its corresponding pixel drive circuit. It should be noted that the pixels used herein may be pixels or subpixels, as these terms are used outside the present specification by those skilled in the art.

The term "pixel circuit" is intended to mean a circuit within a pixel. In one embodiment, pixel circuits may be used in displays or sensor arrays.

The term "pixel driving circuit" is intended to mean a circuit in a pixel or subpixel array that controls the signal (s) for just one pixel. Note that the driving circuit that controls the signal (s) for only one subpixel, not the entire pixel, is still referred to as the pixel driving circuit, as used herein.

The term "polysilicon" is intended to mean a silicon layer consisting of randomly oriented crystals.

The term "power line" is intended to mean a signal line having a primary function of transmitting power.

The term "radiation-emitting component" is intended to mean an electronic device that, when properly biased, emits radiation at a target wavelength or wavelength spectrum. This radiation may be in the visible light spectrum or outside the visible light spectrum (ultraviolet (UV) or infrared (IR)). The light emitting diode is an example of a radiation-emitting device.

The term "radiation-responsive component" is intended to mean an electronic device capable of sensing or otherwise reacting to radiation at a target wavelength or wavelength spectrum. The radiation can be in the visible light spectrum or outside the visible light spectrum (UV or IR). IR sensors and photovoltaic cells are examples of photo-sensing devices.

The term "rectified junction" means a junction formed by a junction in a semiconductor layer or an interface between a semiconductor layer and another material, in which one type of charge carriers flows more easily in one direction through the junction as compared to the opposite direction. It is for. The pn junction is an example of a rectifying junction that can be used as a diode.

The term "reference voltage line" is intended to mean a signal line having a primary function of providing a reference voltage.

The term "scan line" is intended to mean a selection line whose activation is done as a function of time.

The term “semiconductor” is intended to mean a material that can contain or have a rectifying junction formed therein or when such material is in contact with another material (eg, a metal-containing material).

The term “selection line” refers to a series of signals that have a primary function of transmitting one or more signals used to activate one or more electronic elements, one or more circuits, or any combination thereof when a particular signal line is activated. Intended to mean that particular signal line in a line, and other electronic element (s), circuit (s), or any combination thereof associated with another signal line in the series of signal lines, when that particular signal line is activated It is not activated. Signal lines in a series of signal lines may or may not be activated as a function of time.

The term "selection unit" is intended to mean one or more electronic elements, one or more circuits, or a combination thereof controlled by a signal on a selection line.

The term "signal" is intended to mean a current, voltage, light signal, or any combination thereof. The signal can be a voltage or current from a power source, or can represent data or other information by itself or in combination with other signal (s). The optical signal may be based on pulses, intensities, or a combination thereof. The signal can be nearly constant (eg, supply voltage) or can change over time (eg, one voltage for on and another voltage for off).

The term "signal line" is intended to mean a line through which one or more signals can be transmitted. The signal transmitted can be nearly constant or change. The signal line may include a control line, a data line, a scan line, a selection line, a power line, or any combination thereof. Note that signal lines can serve one or more major functions.

The term "significant amount of radiation" means a sufficiently detectable amount of radiation sufficient for a person skilled in the art to determine that radiation is being emitted. For example, when the electronic device 328 is an OLED, a significant amount of radiation represents the lowest design emission intensity that should be emitted from the electronic device 328 at the target emission wavelength or spectrum of the electronic device 328. More specifically, when the electronic device is designed for 256 levels of intensity, 1/256 of the maximum design intensity represents the lower limit for a significant amount of radiation.

The term "significant current" means an amount of current sufficient for the electronic device to operate in its intended function. For example, when the electronic device is an OLED, a significant current is an amount of current sufficient to cause the OLED to emit a detectable amount of radiation at the OLED's target emission wavelength or spectrum. Leakage current through the electronic device is not a significant current for the purposes of this specification.

The term "source / drain region" is intended to mean a region of a field effect transistor that injects charge carriers into or receives charge carriers from the channel region. The source / drain region may include a source region or a drain region according to the flow of current through the field effect transistor. The source / drain region may function as a source region when current flows in one direction through the field effect transistor, and may function as a drain region when current flows in the opposite direction through the field effect transistor.

The term "switch" is intended to mean one or more electronic devices configured to operate as switches when shown in the circuit diagram. Examples of switches include diode and transistor structures, mechanical (eg passive) switches, electromechanical switches (eg relays), and the like. In one embodiment, the switch includes terminals through which current flows and controls that can be used to enable or regulate the current flowing through the switch or to prevent current from flowing through the switch.

The term "thin film transistor" or "TFT" is intended to mean a field effect transistor in which at least the channel region of the field effect transistor is generally not a single crystal semiconductor material. In one embodiment, the channel region of the TFT comprises a-Si, polycrystalline silicon, continuous-crystalline silicon, or a combination thereof.

As used herein, the terms “comprises”, “comprising”, “includes”, “comprising”, “haves”, “haves”, or any other variations thereof are non-exclusive. -exclusive inclusion. For example, a method, process, article, or apparatus that includes a series of components is not necessarily limited to those components, and is not explicitly listed or otherwise essential to such method, process, article, or apparatus. It may include components. In addition, unless expressly stated otherwise, “or” refers to an inclusive or, not an exclusive or. For example, condition A or B is: A is true (or present) and B is false (or nonexistent), A is false (or nonexistent) and B is true (or present), and Both A and B are satisfied by any of being true (or present).

Moreover, for the sake of clarity, the use of "a singular tubular" is used to describe one or more articles referred to by "a singular tubular" to provide a general sense of the scope of the embodiments described herein. Thus, whenever a "singular tubular" is used herein, it should be read to include one or at least one, and the singular also includes the plural unless it is obvious that it is meant in the opposite way. The phrase "X is selected from A, B and C" is equivalent to the phrase "X is selected from the group consisting of A, B and C", meaning that X is A, X is B or X is C. . The phrase "X is selected from 1 to n" is intended to mean that X is 1 or X is 2 or X is n.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, suitable methods and materials are described below. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety. In case of conflict, the present specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and not intended to be limiting.

Group numbers corresponding to the columns in the periodic table of elements use the "New Notation" convention in the CRC Handbook of Chemistry and Physics, 81th edition (2000).

If not described herein, many details regarding particular materials, processing operations, and circuits are conventional and can be found in textbooks and other sources within the field of organic light emitting displays, photodetectors, semiconductors, and microelectronic circuits. Details regarding radiation-emitting elements, pixels, subpixels, and pixel and subpixel circuits will be mentioned before moving on to details of radiation-sensing elements and circuits.

2. Schematic Diagram

The electronic device includes a pixel array. Each of the pixels may include the circuit 300 shown in FIG. 3. In one embodiment, circuit 300 is a pixel circuit. In another embodiment, the electronic device includes a monochrome display, so each pixel includes one circuit 300. In yet another embodiment, the electronic device comprises a full color display comprising three subpixels. Each subpixel includes one circuit 300. For simplicity, regardless of whether the circuit of FIG. 3 is used for a pixel or for a subpixel, the term 'pixel circuit', as used herein, refers to a driver circuit for a pixel or subpixel. .

The circuit 300 includes a selection unit 322. The selection unit 322 may include a control terminal connected to the selection line SL 362, a first terminal connected to the data line DL 364, and a first terminal of the data holder unit 324 at the node 325. And a second terminal connected to the first gate electrode of the driving transistor 326 and the first terminal of the switch 342. The SL 362 provides a control signal for the selection unit 322, and the DL 364 provides a data signal to be delivered to the data holder unit 324 when the selection unit 322 is activated. In one embodiment, the selection unit 322 comprises a switch. In a more specific embodiment, the switch may comprise a field effect transistor, where its gate electrode is connected to the SL 362, the first source / drain region is connected to the DL 364, and the second source The / drain area is connected to the data holder unit 324. In other embodiments, other transistors (including JFETs and bipolar transistors), switches, or any combination thereof may be used within the selection unit 322. In still other embodiments, more or other electronic element (s) may be used within the selection unit 322.

The circuit 300 also includes a data holder unit 324. The data holder unit 324 includes a first terminal and a second terminal. The first terminal of the data holder unit 324 is connected to the node 325. The second terminal of the data holder unit 324 is, at the node 327, a first source / drain region of the driving transistor 326, a first electrode of the electronic element 328, and a first terminal of the switch 342. Is connected to. The second terminal of the data holder unit 324 is also connected to the V _dd line 368. In one particular embodiment, data holder unit 324 includes a capacitive electronic device. The first electrode of the capacitive electronic device is connected to the node 325, and the second electrode of the capacitive electronic device is connected to the node 327. In an alternate embodiment (not shown), an optional anti-degradation unit may comprise at least one of the data holder unit 324 and the power lines (eg, V _ss line 366, V _dd line ( 368) or both).

The circuit 300 further includes a drive transistor 326. The driving transistor 326 includes a first gate electrode, a second gate electrode, a first source / drain region, and a second source / drain region. The second gate electrode of the driving transistor is connected to the signal line (TG) 384. The first source / drain region of the driving transistor 326 is connected to the node 327, and the second source / drain region of the driving transistor 326 is connected to the V _dd line 368. In an alternative embodiment (not shown), the drive transistor 326 is coupled to an optional deterioration prevention unit.

Circuit 300 further includes electronic device 328. The electronic device 328 includes a first electrode and a second electrode connected to the V _ss line 366. In one embodiment, the first electrode is an anode and the second electrode is a cathode. In another embodiment, electronic device 328 is an organic emission-emitting electronic device, such as an OLED. The remainder of the circuit 300 is well suited to providing a variable current source for driving the electronic device 328. Thus, one or more electronic devices that are current driven may be used in place of or in conjunction with electronic device 328. Note that one or more electronic devices may or may not include a diode.

In one embodiment, the conduction path includes drive transistor 326 and electronic device 328, which is the only transistor between V _dd line 368 and V _ss line 366. More specifically, the first and second source / drain regions of the drive transistor 326 are along the conduction path between the V _dd line 368 and the V _ss line 366.

Circuit 300 further includes a switch 342. The switch 342 includes a control terminal connected to the SL 362, a first terminal connected to the node 327, and a second terminal connected to the voltage reference V _ref line 382. SL 362 provides a control signal to switch 342 and V _ref line 382 provides a voltage to node 327. In a particular embodiment, V _ref line 382 is not connected to DL 362, so that data can be written to the pixel at the same time that the voltage at node 327 is being adjusted. In another embodiment, the reference voltage line is configured to be at a voltage such that no significant current flows through the electronic device 328 when the switch 342 is closed. In one embodiment, the switch 342 includes a field effect transistor, where its gate electrode is connected to the SL 362, the first source / drain region is connected to the node 327, and the second source. The / drain region is connected to the V _ref line 382. In one particular embodiment, the control terminal of the switch 342 is connected to the SL 362. In other embodiments, other transistors (including JFETs and bipolar transistors), switches, or any combination thereof may be used within switch 342. In still other embodiments, more or other electronic element (s) may be used within the switch 342.

In one embodiment, the selection unit 322, the data holder unit 324, the electronic device 328, the drive transistor 326, and the switch 342 may all be in an array, as shown in FIG. 3. . In other embodiments, any or all of the electronic devices and units in circuit 300, other than electronic device 328, may be external to the array.

Signal line 384 may be at a negative voltage, a positive voltage, or zero volts depending on the operation of the pixel or subpixel, which will be described in more detail below. V _ref line 382 may be at negative voltage, positive voltage, zero volts, or in electrical stray state when switch 342 is off. When switch 342 is on, V _ref line 382 is at a voltage less than or equal to the voltage of V _ss line 366, in one embodiment. In another embodiment, V _ref line 382 is always at a substantially constant voltage when circuit 300 is in operation. In another embodiment, all unselected select lines in the array (ie, select lines other than the active select line (s) in which data is being written) may or may not be maintained at V _ref .

The drive transistor 326, the selection unit 322, the switch 342, or any combination thereof can include a field effect transistor. In the circuit 300 shown in FIG. 3, all transistors are n-channel transistors. Any one or more of the n-channel transistors for the selection unit 322, the switch 342, or a combination thereof may be replaced with any one or more p-channel transistors. In one particular embodiment, the field effect transistors in selection unit 322 and switch 342 are of the same type (both n-channel or p-channel, both in incremental mode or depletion mode), and thus the signal on SL 362 Simultaneously turns on or off the field effect transistors in the selection unit 322 and the switch 342.

An alternative circuit 400 is shown in FIG. 4. Circuit 400 is similar to circuit 300, but switch 442 operates in a mode that is substantially the opposite of switch 342. In one particular embodiment, the n-channel transistor of switch 342 is replaced by a p-channel transistor at switch 442. Switch 342 is coupled to SL 362, but inverter 462 is between SL 362 and switch 442. In this embodiment, the input terminal of inverter 462 is connected to SL 362 and the output terminal of inverter 462 is connected to the control terminal of switch 442. Inverter 462 allows the same signal on SL 362 to turn on both selection unit 322 and switch 442 or to turn off both selection unit 322 and switch 442. In one embodiment, inverter 462 is conventional and may or may not be located within the array or within each pixel or subpixel.

3. Timing Diagram

Operation of the circuit 300 is described with respect to the timing diagram of FIG. The circuit 300 can be operated to include a recording portion and a radiation portion (also called a holding (exposure portion)). Although not shown in FIG. 5, the threshold-adjust portion is not essential but optional. 5 is a timing diagram with voltage, signal (eg, 0 or 1), and current for portions of circuit 300 in accordance with one non-limiting embodiment. In this embodiment, the array has 320 rows. The recording portion is 1/320 or approximately 0.3% of the frame time, which is considerably smaller than half of the frame time. The emissive portion is almost greater than the rest of the frame time or 99% of the frame time. During the writing portion, the electronic element 328 does not emit a significant amount of radiation. For example, when electronic device 328 is an OLED, electronic device 328 does not emit radiation at the target emission wavelength or spectrum of electronic device 328.

In one embodiment, the voltage on V _ss line 366, V _dd line 368, and V _ref line 382 is nearly constant. The actual voltage used for V _ss line 366, V _dd line 368, and V _ref line 382 is not critical, but the difference between the voltages may be important. In a particular embodiment, the voltage difference between the voltages on V _dd line 368 and V _ss line 366 is in the range of approximately 5-20 volts, and V _ref line 382 has a voltage in the following range.

내지

볼트

To

volt

는 전자 소자(328)의 문턱 전압이다. 일 실시예에서, V_ref는 방사 부분 동안에 대략

내지 노드(327)에서의 최대 전압일수 있다. 특정 실시예에서,

는 대략 2 내지 2.5 볼트의 범위(이 이하에서는 상당한 전류가 전 자 소자(328)를 통해 흐르지 않으며 방사 방출이 일어나지 않음)에 있으며, 노드(327)는 대략 6V에 이를 수 있다. 따라서, V_ref는 V_ss보다 대략 2.5V 높은 것부터 V_ss보다 대략 6V 낮은 것의 범위에 있을 수 있다. 특정 실시예에서, 방사 부분 동안에, V_ref는 대략 V_ss + 2.5V 내지 -(V_dd-V_ss)/2 볼트의 범위에 있다.

Is the threshold voltage of the electronic device 328. In one embodiment, V _ref is approximately during the radiating portion.

To the maximum voltage at node 327. In certain embodiments,

Is in the range of approximately 2 to 2.5 volts (hereinafter no significant current flows through the electronic element 328 and no radiated emission occurs) and the node 327 can reach approximately 6V. Therefore, V _ref may be in the range of what approximately 2.5V approximately 6V lower than the higher starting with V _ss than V _ss. In a particular embodiment, during the radiating portion, V _ref is in the range of approximately V _ss + 2.5V to-(V _dd -V _ss ) / 2 volts.

In one embodiment, SL 362 is one of several select lines corresponding to a row of pixels in the electronic device. In a particular embodiment, line 382 is connected to a selection line along adjacent pixel rows, such as a selection line for the previous (n-1) row or the next (n + 1) row. In this embodiment, the voltage at the adjacent unselected select line is V _ref . For example, the scan pulse for the selected select line during the write portion may be approximately + 20V, and the unselected select line during the same write portion is approximately −5V. Thus, in one embodiment, during the frame time (approximately 16.65 ms long), each select line is at approximately + 20V (on-state, write portion) for approximately 52 microseconds and approximately -5V (off for approximately 16.6 ms). -State, radiation part. In other embodiments, other voltages, frame time lengths, on-states and off-states may be used. An exemplary physical layout for achieving this circuit is described later in this specification.

During the recording portion, the SL 362 is activated (“1” shown in FIG. 5) and allows the signal on the DL 364 to pass through the selection unit 322. The voltage on node 325 is approximately equal to the voltage on DL 364. SL 362 also provides a control signal for switch 342. The voltage on node 327 is approximately equal to the voltage on V _ref line 382. Node 327 has a voltage that is approximately equal to V _ref at the end of the recording portion, which in one embodiment may be a negative voltage. The voltage difference across the terminals of the data holder unit 324 is the voltage difference between the node 325 and the node 327, which may be similar to the difference between the voltage on the DL 364 and the voltage on the V _ref line 382. have. The signal on TG 384 becomes a negative voltage, which turns off drive transistor 326. Thus, little current flows between the V _dd line 368 and the V _ss line 366 during the recording portion. In one embodiment, little current flows through the electronic element 328 during the recording portion.

During the radiating portion, the SL 362 is deactivated (“0” shown in FIG. 5), so the selection unit 322 and the switch 342 are turned off. In one particular embodiment, SL 362 is at approximately V _ref during the radiating portion. The signal at TG 384 becomes zero volts or a positive voltage, which turns on drive transistor 326. Current flows from the V _dd line 368 through the driving transistor 326 and the electronic device 328 to the V _ss line 366. The electronic device 328 emits radiation as an intensity that is a function of the voltage at one or both of the first and second gate electrodes of the drive transistor 326. In one embodiment, the voltage at node 327 increases when drive transistor 326 is turned on. The voltage between the terminals of the data holding unit 324 remains about the same as the voltage at the end of the writing period. The voltage at the nodes 325 and 327 increases by a value corresponding to the voltage across the electrodes of the electronic device 328. The emission intensity of the electronic device 328 is thus determined by V _data , regardless of the previous voltage between the electrodes of the electronic device 328.

The operation of the pixel using the circuit 300 continues by alternating the write and emit portions for additional frame time.

The operation of circuit 400 is nearly identical. Inverter 462 may cause a delay between the time that selection unit 322 turns on and the time that switch 442 turns on. However, this delay is only a few nanoseconds and is minor compared to the recording portion (which in one embodiment may be approximately 52 microseconds) (eg less than 0.3% of the recording portion).

In another embodiment, a threshold voltage adjustment procedure may be performed to remove charges that may be trapped in one or both of the gate dielectric layers in the drive transistor 326. An exemplary threshold voltage procedure is a method of operating an electronic device that includes a parallel conducting path and a circuit including a parallel conducting path, filed July 16, 2004. Parallel Conduction Paths, "US Patent Application No. 10 / 892,992 to Matthew Stevenson et al., And the name of the invention filed July 16, 2004, describe" a circuit for driving an electronic device and an electronic device having the The method is described in more detail in US Patent Application No. 10 / 893,211 to Zhining Chen et al., "Circuit For Driving an Electronic Component and Method of Operating an Electronic Device Having the Circuit," both of which are assigned to the current assignee of the present application. It is.

4. Double-gate TFT

The drive transistor 326 shown in FIG. 3 is a double-gate thin film transistor (TFT). 6-14 illustrate exemplary process sequences used to form portions of drive transistor 326 and electronic device 328. 6 illustrates a cross-sectional view of a portion of a substrate 600 of an electronic device. The substrate may be rigid or flexible, and may include one or more layers of organic, inorganic, or both organic and inorganic materials. In one embodiment, the substrate may include a transparent material that allows at least 70% of the radiation incident on the substrate 600 to be transmitted.

The black layer 622 and the first gate electrode 624 are formed on the substrate 600. In one embodiment, the black layer 622 and the first gate electrode 624 can be formed using conventional deposition and optional patterning sequences. For example, the layers for black layer 622 and first gate electrode 624 may be deposited as patterned layers using a stencil mask. In another embodiment, the layers for the black layer 622 and the first gate electrode 624 may be sequentially deposited over the substrate 600, and the black layer 622 and the first gate electrode 624 may be conventionally deposited. Can be patterned using a lithography process. In another embodiment, the black layer 622 can be formed on top of almost all of the substrate 600 and the first gate electrode 624 can be deposited as a patterned layer on top of the black layer 622. have. The first gate electrode 624 can function as a hard mask during the etching step to remove a portion of the black layer 622 not covered by the first gate electrode 624. In another embodiment, the black layer 622 may be omitted, and the first gate electrode 624 may be formed on the surface of the substrate 600. After reading this specification, skilled artisans will appreciate that many other techniques may be used to form the black layer 622 and the first gate electrode 624.

The black layer 622 allows for an improved contrast ratio of the electronic device when used in ambient light conditions. The material and thickness of the black layer is referred to as May 7, 2004, entitled "Array Comprising Organic Electronic Devices With a Black Lattice and Process For". Forming the Same, "US Patent Application No. 10 / 840,807 to Gang Yu et al.

The first gate electrode 624 may include one or more layers comprising at least one element selected from Groups 4 to 6, 8, 10 to 14 or any combination thereof of the periodic table. In one embodiment, the first gate electrode 624 may comprise Cu, Al, Ag, Au, Mo, or any combination thereof. In another embodiment, where the first gate electrode 624 includes two or more layers, one of the layers may include Cu, Al, Ag, Au, Mo, or any combination thereof, and the other The layer may comprise Mo, Cr, Ti, Ru, Ta, W, Si, or any combination thereof. Note that conductive metal oxide (s), conductive metal nitride (s), or combinations thereof may be used in place of or in conjunction with any of the elemental metals or alloys thereof. In one embodiment, the first gate electrode has a thickness in the range of approximately 100 to 500 nm. In one embodiment, this thickness is approximately 300 nm.

The first gate dielectric layer 722, the first semiconductor layer 742, and the second semiconductor layer 744 are sequentially formed on the substrate 600 and the first gate electrode 624, as shown in FIG. 7. do. Each of the first gate dielectric layer 722, the first semiconductor layer 742, and the second semiconductor layer 744 may be formed using conventional deposition techniques.

The first gate dielectric layer 722 may include one or more of silicon dioxide, alumina, hafnium oxide, silicon nitride, aluminum nitride, silicon oxynitride, other conventional gate dielectric materials used in the semiconductor art, or any combination thereof. It may comprise a layer. In another embodiment, the thickness of the first dielectric layer 722 is in the range of approximately 50-5000 nm.

Each of the first and second semiconductor layers 742 and 744 may include one or more materials conventionally used as semiconductors in electronic devices. In one embodiment, the first semiconductor layer 742, the second semiconductor layer 744, or both, are amorphous silicon (a-Si), low-temperature polysilicon (LTPS), continuous grain silicon, Continuous grain silicon), or a combination thereof (eg, deposited). In another embodiment, other Group 14 elements (eg, carbon, germanium), alone or in combination (with or without silicon), the first semiconductor layer 742, the second semiconductor layer 744. Or both. In still other embodiments, the first and second semiconductor layers 742 and 744 may be III-V (Group 13-15) semiconductors (eg, GaAs, InP, GaAlAs, etc.), II-VI ( Group 2-16 or Group 12-16) semiconductors (eg, CdTe, CdSe, CdZnTe, ZnSe, ZnTe, etc.), or any combination thereof.

In one embodiment, the first semiconductor layer 742 comprises silicon as the only semiconductor material, and the second semiconductor layer 744 is a semiconductor other than Ge, silicon germanium (SiGe), silicon carbide (SiC), or silicon. Material (alone or mixed with silicone). The importance of other materials in the first and second semiconductor layers 742, 744 will become apparent later during the patterning sequence herein.

The first semiconductor layer 742 is undoped or doped with a p-type dopant, for example, at a concentration no greater than approximately 1 × 10 ¹⁸ atoms / cm ³ . The second semiconductor layer 744 includes an n-type or p-type dopant at a concentration greater than that of the first semiconductor layer 742. In one embodiment, the second semiconductor layer 744 is n + or p + doped to form ohmic contacts with subsequent metal-containing structures. In another embodiment, the dopant concentration in the second semiconductor layer 744 is less than 1 × ^{10 19} atoms / cm ³ , and a Schottky contact is formed when contacted with a subsequently formed metal-containing structure. Conventional n-type dopants (phosphorus, arsenic, antimony, etc.) or p-type dopants (boron, gallium, aluminum, etc.) may be used. Such dopants may be included during deposition or added during separate doping sequences (eg, implantation and annealing). First and second semiconductor layers 742 and 744 are formed using conventional deposition and doping techniques. In one embodiment, the thickness of the first semiconductor layer 742 is in the range of about 100 to 250 nm and the thickness of the second semiconductor layer 744 is in the range of about 10 to 100 nm. After reading this specification, skilled artisans will appreciate that other thicknesses may be used to achieve the desired electronic properties of drive transistor 326.

The first and second semiconductor layers 742, 744 are patterned as shown in FIG. 8 using conventional lithography techniques. The structure formed in FIG. 8 has a pair of edges 822, 824. Note that the first and second semiconductor layers 742, 744 are coterminous at the edges 822, 824, respectively. In another embodiment, the first and second semiconductor layers 742, 744 are patterned using a stencil mask to form the patterned first and second semiconductor layers 742, 744, as shown in FIG. 8. Is deposited as a layer.

First and second source / drain contact structures 922 and 924 are formed over portions of the first gate dielectric layer 722 and the first and second semiconductor layers 742 and 744. First and second source / drain contact structures 922 and 924 may be formed using conventional techniques. In one embodiment, the stencil mask may be used during the deposition operation to form the first and second source / drain contact structures 922, 924. In other embodiments, first and second source / drain contact structures 922, 924 are conventional lithography for depositing one or more layers on top of almost all of substrate 600 and for patterning the layer (s). It is formed by using technology. Any of the materials and thicknesses described with respect to the first gate electrode 624 can be used for the first and second source / drain contact structures 922, 924.

From a plan view of the electronic device, an exposed portion of the second semiconductor layer 744 is between the first and second source / drain contact structures 922, 924. In one embodiment, the spacing between the first and second source / drain contact structures 922, 924 is approximately the minimum dimension for the design rule used. In one embodiment, when the 4-micrometer design rule is used, the space between the first and second source / drain contact structures 922, 924 is approximately 4 micrometers. In another embodiment, the spacing between the first and second source / drain contact structures 922, 924 is greater than the minimum dimension for the design rule. After reading this specification, skilled artisans will be able to select the spacing between drain and source contacts that best meets the requirements or requirements of a particular transistor design.

The exposed portion of the second semiconductor layer 744 is then removed to form the opening 1002, as shown in FIG. 10. In this embodiment, the drain and source contact structures 922 and 924 are part of the hard mask used to remove the exposed portions of the second semiconductor layer 744. Thus, the channel region for the drive transistor 326 is self-aligned with the source / drain contact structures 922, 924. Etching may be performed using wet or dry etching techniques. In one embodiment, the etchant used may allow the second semiconductor layer 744 to be selectively removed (ie, etched at a higher rate) with respect to the first and second source / drain contact structures 922, 924. To make it possible.

In one embodiment, a halogen-containing plasma may be used by performing a dry etching technique to remove the exposed portions of the second semiconductor layer 744. The feed gas may include a halogen-containing gas such as a fluorine-containing gas. The halogen-containing gas can be carbon fluoride having the formula C _a F _b H _c , where a is 1 or 2, b is at least 1, when a is 1 b + c is 4 and a is 2 b + c is 4 or 6. In another embodiment, the fluorine-containing gas is F ₂ , HF, SF ₆ , NF ₃ , fluorine-containing interhalogen (ClF, ClF ₃ , ClF ₅ , BrF ₃ , BrF ₅ , IF ₅ ), or And any mixture thereof. In another embodiment, the halogen-containing gas is a chlorine-containing gas comprising Cl ₂ , HCl, BCl ₃ , a chlorine-containing interhalogen compound (ClF, ClF ₃ , ClF ₅ ), or any mixture thereof. In another embodiment, the halogen-containing gas is a bromine-containing gas comprising Br ₂ , HBr, BBr ₃ , bromine-containing interhalogen compounds (BrF ₃ , BrF ₅ ), or any mixture thereof. In another embodiment, the halogen-containing gas is an iodine-containing gas comprising I ₂ , HI, or any mixture thereof. In another embodiment, the halogen-containing gas is any mixture of gases described in this paragraph.

The feed gas may include any one or more oxygen-containing gases, such as O ₂ , O ₃ , N ₂ O, or other oxygen-containing gases conventionally used to generate oxygen plasmas in the semiconductor art. The feed gas may also include one or more inert gases (eg, noble gas, N ₂ , CO ₂ , or any combination thereof).

Etching may be performed in an etch chamber. During etching, the pressure is in the range of approximately 7.5 to 5000 mTorr. At these pressures, the feed gas (es) may flow at a rate ranging from approximately 10 to 1000 sccm (standard cubic centimeters per minute). In other embodiments, the pressure may be in the range of about 100 to 500 mTorr and the feed gas (s) may flow at a rate in the range of about 100 to 500 sccm. Voltage and power may be applied to generate the plasma. Power is generally a linear function or nearly linear function of the surface area of a substrate. Thus, power density (power per board unit area) is given. The voltage is in the range of about 10 to 1000 V and the power density is in the range of about 10 to 5000 mW / cm ² . In one embodiment, the voltage may be in the range of approximately 20 to 300 V and the power density may be in the range of approximately 50 to 500 mW / cm ² .

Etching may be performed as a timed etch or using endpoint detection with timed overetch. When the first and second semiconductor layers 742 and 744 are generally silicon, timed etching may be used. If different materials are used for the first and second semiconductor layers 742, 744, endpoint detection may be used. For example, in one embodiment, where the second semiconductor layer 744 comprises silicon germanium, endpoint detection may be due to the absence of germanium in the waste from the etching chamber after the first semiconductor layer 742 is exposed. Can be based. In another embodiment, where the second semiconductor layer 744 includes germanium and little silicon, endpoint detection may be based on the presence of silicon in the waste from the etch chamber after the first semiconductor layer 742 is exposed. Can be. If etching occurs more slowly, timed overetching may be used to ensure that a portion of the second semiconductor layer 744 is removed from the area of the substrate 600. In one embodiment, the power density during etching may be reduced during overetching to improve the selectivity of the second semiconductor layer 744 for the first semiconductor layer 742 and other portions of the electronic device exposed to the etch plasma. have.

The selected wet chemical etchant is based in part on the composition of the second semiconductor layer 744 and other portions of the electronic device exposed during etching. In one embodiment, the etchant may comprise a base (eg, KOH, tetramethyl ammonium hydroxide, etc.) or a combination of an oxidant (eg, HNO ₃ ) and HF. Timed etching is generally used for wet chemical etching.

After etching is complete, part of the first semiconductor layer 742 may be removed or not removed at all. In one embodiment, only about 50 nm of the first semiconductor layer 742 is removed.

At this point in the process, first and second source / drain structures 1022, 1024 are formed. First source / drain structure 1022 includes a first source / drain contact structure 922 and a portion of the second semiconductor layer 744 beneath it. The second source / drain structure 1024 includes a second source / drain contact structure 924 and a portion of the second semiconductor layer 744 beneath it.

In one embodiment, the selection unit 322 and the switch 342 include field effect transistors. At this point in the process, transistors for selection unit 322 and switch 342 are formed, but are not shown in FIG.

The second gate dielectric layer 1122 may include a first gate dielectric layer 722, a first source / drain contact structure 922, a second source / drain contact structure 924, and a first semiconductor. Formed on top of layer 742. The second gate dielectric layer 1122 may include any one or more layers that may include one or more materials, as previously described with respect to the first gate dielectric layer 722. In one embodiment, the second gate dielectric layer has a thickness in the range of approximately 50-500 nm. In other embodiments, the first and second gate dielectric layers 722, 1122 have substantially the same composition and thickness as compared to each other. In other embodiments, the first and second gate dielectric layers 722, 1122 have different compositions, thicknesses, or compositions and thicknesses relative to each other.

As shown in FIG. 11, the second gate electrode 1124 is formed over the second gate dielectric layer 1122. In one embodiment, the second gate electrode 1124 is over a portion of the first source / drain contact structure 922, the second source / drain contact structure 924, and the first semiconductor layer 742. As described in connection with the first gate electrode 724, the second gate electrode 1124 may be formed using any one or more of the prior art. The first and second gate electrodes 724 and 1124 may be formed using the same or different techniques. The second gate electrode 1124 may include one or more layers and may include any one or more of the materials described with respect to the first gate electrode 624. The thickness may be in the range described above with respect to the first gate electrode 624. In other embodiments, the first and second gate electrodes 624 and 1124 have substantially the same composition and thickness as compared to each other. In other embodiments, the first and second gate electrodes 624, 1124 have different compositions, thicknesses, or compositions and thicknesses relative to each other. In one embodiment, the layer (s) for the second gate electrode 1124 are opaque to radiation emitted from the pixel (s), thus covering the channel region of the driving transistor 326 and from the radiation emitting pixel (s). A radiation shielding layer is formed to help prevent radiation of the light source from reaching the channel region of the driving transistor 326.

FIG. 12 shows an enlarged view of a portion of the drive transistor 326 shown in FIG. The channel region 1242 for the drive transistor 326 is the region of the first semiconductor layer 742 between the first and second source / drain structures 1022, 1024. In this embodiment, channel region 1242 has a physical channel length 1202 as shown in FIG. Second gate electrode 1124 has an effective gate width 1222 and a physical gate width 1224, as indicated by the arrow dimensions in FIG. 12.

In one embodiment, the physical channel length 1202 is only 2 microns larger than the effective gate width 1222. In another embodiment, the physical channel length 1202 is approximately twice the effective gate width 1222 + the thickness of the second gate dielectric layer 1122. In another embodiment, the difference between the physical channel length 1202 and the effective gate width 1222 is less than twice the minimum dimension of the design rule used to design the TFT. In another embodiment, the physical channel length 1202 does not exceed twice the minimum dimension of the design rule used to design the TFT. In another embodiment, the physical channel length 1242 is less than the physical gate width 1224.

As shown in FIG. 13, an insulating layer 1322 is formed over the substrate 600. Insulating layer 1322 may include one or more layers of one or more of the materials described with respect to first gate dielectric layer 722. In one embodiment, insulating layer 1322 has a thickness in the range of approximately 100-5000 nm. Insulating layer 1322 may be formed using conventional deposition techniques, spin-coating techniques, or printing techniques.

A contact opening 1324 is formed through the insulating layer 1322 and the second gate dielectric layer 1122 to expose a portion of the first source / drain structure 1022. A first electrode 1342 for the electronic device 328 is formed in the contact opening and extends over a portion of the substrate 600 away from the drive transistor 326 as shown in FIG. 13. First electrode 1342 may include one or more layers of one or more materials conventionally used for anodes in conventional OLEDs. First electrode 1342 may be formed using conventional deposition techniques or by conventional deposition and patterning sequences.

In one embodiment, the first electrode 1342 transmits at least 70% of the radiation emitted or reacted by the subsequently formed organic active layer (s). In one embodiment, the thickness of the first electrode 1342 is in the range of approximately 100-200 nm. If radiation does not need to be transmitted through the first electrode 1342, this thickness may be greater, such as up to 1000 nm or even thicker.

Subsequently, the organic layer 1430 and the second electrode 1442 are formed on the substrate 600, as shown in FIG. 14. The organic layer 1430 may include one or more layers. The organic layer 1430 includes an organic active layer 1434 and may optionally include any one or more of a charge injection layer, a charge transfer layer, a charge blocking layer, or any combination thereof. An optional charge injection layer, charge transport layer, charge blocking layer, or any combination thereof may be provided between the organic active layer 1434 and the first electrode 1342, between the organic active layer 1434 and the second electrode 1442. Or combinations thereof. In one embodiment, the hole-transport layer 1432 is between the first electrode 1342 and the organic active layer 1434. Formation of organic layer 1430 is performed using any one or more conventional techniques used to form organic layers in OLEDs. The hole transport layer 1432 has a thickness in the range of approximately 50 to 200 nm, and the organic active layer 1434 has a thickness in the range of approximately 50 to 100 nm. In one embodiment, only one organic active layer is used in the array. In other embodiments, different organic active layers may be used for different parts of the array.

Second electrode 1442 comprises one or more layers of one or more materials used for the cathode in a conventional OLED. Second electrode 1442 is formed using one or more conventional deposition or conventional deposition and lithography techniques. In one embodiment, the second electrode 1442 has a thickness in the range of approximately 100-5000 nm. In a particular embodiment, the second electrode 1442 may be a common cathode for the array.

Other circuits not shown in FIG. 14 may be formed using any number of the above or additional layers. Although not shown, additional insulating layer (s) and interconnect layer (s) may be formed in the peripheral area (not shown) that may be outside the array to allow for circuitry. Such circuits may include row or column decoders, strobes (eg, row array strobes, column array strobes), or sense amplifiers. As another alternative, such a circuit may be formed before, during or after the formation of any of the layers shown in FIG. In one embodiment, second electrode 1442 is part of V _ss line 366 and second source / drain contact structure 924 is part of V _dd line 368. In one embodiment, the first gate electrode 624 is connected to the second terminal of the selection unit 322 and the first terminal of the data holder unit 324, the second gate electrode 1124 being the TG 384. Is part of.

A lid (not shown) having a desiccant (not shown) is attached to the substrate 600 at a location outside the array (not shown) to form a substantially completed device. There may or may not be a gap between the second electrode 1442 and the desiccant. The materials used for the coverings and desiccants and the attachment process are conventional.

5. Other Physical Layout Considerations

The connection for V _ref can be implemented in a number of different ways. In one embodiment, the terminal of switch 342 is connected to a direct current voltage via line 382. Line 382 can be implemented as a bus line using the same layer (s) as select line 342. In one particular embodiment, the length of line 382 is approximately parallel to the length of select line 362. In another embodiment, the terminal of switch 342 is connected to V _ss line 366. In one particular embodiment, prior to forming the second electrode 1442, to expose a portion of the first source / drain contact structure 922 that is part of or connected to the second terminal of the switch 342, An opening may be formed through the organic layer 1430, the insulating layer 1322, and the second gate dielectric layer 1122 (not shown). Openings may be formed using conventional lithography processes known in the semiconductor art. Subsequently, a layer (s) for the second electrode 1442 are formed and extend into the opening to contact the second terminal of the switch 342. In this particular embodiment, a portion of the layer (s) of the second electrode 1442 in the opening forms a line 382 as shown in FIG. 3.

In another embodiment, similar contact may be made to select lines of adjacent pixels along different rows. 15 and 16 show top views within an array of electronic devices for a particular layout to achieve this connection. FIG. 15 illustrates an electronic device after first and second semiconductor layers 744 and 742 are deposited and patterned. Dotted line 1500 indicates a boundary between two pixels. Below dashed line 1500, select line 362 is the select line for that pixel and not the select line for the pixel above dashed line 1500. Select line 362 has portions 1562 (one of which is shown in FIG. 15) that allows contact with select line 362. Above dotted line 1500, conductive portion 1544 is connected to another select line (not shown) for that pixel and not to select line 362 shown in FIG. 15. In this particular embodiment, conductive portion 1544 is a gate electrode for the transistor in switch 342.

In one embodiment, select line 362 and conductive portion 1544 are formed simultaneously with first gate electrode 624 (not shown in FIG. 15). In other embodiments, any one or more of select line 362, conductive portion 1544, and first electrode 624 may be formed at different times and may have the same or different composition. Although not shown in FIG. 15, first gate dielectric layer 722 is formed as described above and over select line 362 and conductive portion 1544 that includes portions 1562. The first and second semiconductor layers 742 and 744 are formed on the first gate dielectric layer 722 as described above. Portions 1542 of first and second semiconductor layers 742 and 744 correspond to locations where transistors for switches 342 are formed, and portions 1526 of first and second semiconductor layers 742 and 744. Corresponds to the position where the driving transistor 326 is formed.

Before the first and second source / drain contact structures 922 and 924 are formed, openings (not shown) are formed to expose portions 1562 along the selection line 362. When the first and second source / drain contact structures 922 and 924 are formed, another contact structure is formed and corresponds to line 382. The contact structure 1644 is in contact with one of the portions 1562 of the select line 362 and the portion of the second semiconductor layer 744 that is the second terminal of the switch 342. The portion of the second semiconductor layer 722 and the line 382 between the source / drain contact structures 922 and 924 expose portions of the first semiconductor layer 742 underneath, as described above. To be etched. As such, line 382 is connected to select lines for adjacent pixel columns.

Unselected select line 362 is at V _ref , and selected select line 362 has sufficient voltage to turn on select transistor 322 and switch 342 for selected select line 362. When the selected select line 362 is deselected, its voltage is changed to V _ref . When one of the unselected select lines 362 is selected, its voltage is changed to a value sufficient to turn on the select transistor 322 and switch 342 for the newly selected select line 362.

After reading this specification, skilled artisans will appreciate that many other physical layouts are possible. It is almost impossible to enumerate all conceivable physical layouts and implementations. Accordingly, many different physical layouts and implementations do not depart from the scope of the present invention.

6. Other Example

The above embodiments are well suited for AMOLED displays, including monochrome and full color displays. Still, the concepts described herein may be used in other types of radiation-emitting electronic devices. Other radiation-emitting electronic devices can include inorganic LEDs, including passive matrix displays, lighting panels, and III-V or II-VI-based inorganic radiation-emitting devices. In one embodiment, the radiation-emitting electronic device may emit radiation in the visible light spectrum, and in another embodiment, the radiation-emitting electronic device may emit radiation outside the visible light spectrum (eg, UV or IR). .

In other embodiments, the concepts described herein may be extended to other types of electronic devices. In one embodiment, the sensor array may comprise an array of radiation-responsive electronic devices. In one embodiment, different radiation-reactive electronic devices can have the same or different active materials. The reaction of these active substances can change over time. In addition, some of the sensor arrays may have other portions that receive different wavelengths, different radiant intensities, or a combination thereof. Similar to electronic devices having radiation-emitting electronic devices, the lifetime of electronic devices having radiation-reactive electronic devices can have a longer useful life.

Different subpixels in the array may have different voltages for the power supply line or the reference voltage line. For example, in a full color display, all blue light emitting devices can have V _{dd - blue} , V _{ss - blue} and V _{ref - blue} , and all green light emitting devices have V _dd-green , V _{ss - green} and V _{ref. -} it may have a _green, all the red light emitting element is V _{dd -} may have a _red-red, V _{ss -} V _ref and _red. Each of V _{dd - blue} , V _{dd - green} and V _{dd - red} may be the same or different from each other. V _{ss - blue} , V _{ss - green} and V _{ss - red} may each be the same or different compared to each other. Each of V _{ref - blue} , V _{ref - green} and V _{ref - red} may be the same or different from each other. After reading this specification, one skilled in the art can determine the actual voltage to be used in a particular application.

Radiation to / from the electronic device may be transmitted through the substrate (“bottom radiation”) or through the lid (“top radiation”). The positions of the first and second electrodes can be reversed so that the cathode (s) are closer to the substrate as compared to the anode (s).

A substrate structure (not shown), such as a well structure or a cathode separator, may be formed after the first electrode 1342 and before the organic layer 1430. The substrate structure may or may not be subjected to surface treatment, such as fluorination or adding a surfactant to the surface of the substrate structure. Such substrate structure may or may not include a black layer to reduce the intensity of the radiation from the electronic device 328 or to prevent the radiation from substantially reaching the transistors in the circuit 300.

7. Advantage

Circuit 300 may turn on a pixel or subpixel during a significantly larger portion of frame time compared to circuit 100. For each pixel or subpixel, its electronic device 328 is only off during the time that the SL 364 activates the selection unit 322 and the switch 342 (which is a relatively small portion of the frame time). Unlike the circuit 100, the current through the electronic device 328 can be lower and still achieve the same emission intensity as seen by the human user of the display having the circuit 300. Lower currents reduce power requirements and heat generation, thus lowering the degradation rate of the organic active layer in the organic layer 1430, reducing the rate at which trapped charge accumulates in the first gate dielectric layer 722, Improves reliability and lifetime.

Channel region 1242 can be significantly shorter compared to other dual-gate TFT designs in which the source, drain, and top gate structures are formed simultaneously. In another design, the channel region has a physical channel length that is at least three times the minimum dimension of the design rule. For the 4-micrometer design rule, the physical channel length is approximately 12 micrometers. The width of the top gate electrode for a conventional double-gate TFT using a 4-micrometer design rule is approximately 4 micrometers, with its center at the top of the channel region. Thus, in the conventional double-gate TFT, most of the channel region (about 2/3) are not covered by the upper gate electrode. The additional channel length increases the resistance through the drive transistors, increases the size of the drive transistors and reduces the aperture ratio for the bottom emission display. Thus, drive transistor 326 using the embodiments described herein can be smaller, thus increasing aperture ratio and reducing power consumption, while emitting radiation intensity more than using conventional transistor designs. Keep it high or equal.

Note that not all of the above operations are required in the general description of the examples, that some portions of the specific operations may not be required, and that additional operations may be performed in addition to the above. In addition, the order in which each of the operations are enumerated is not necessarily the order in which they are performed. After reading this specification, skilled artisans will be able to determine which operations may be used for their particular requirements or desires.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.

Any one or more advantages, one or more other advantages, one or more solutions to one or more problems, or combinations thereof, are described above with respect to one or more specific embodiments. Nevertheless, these benefit (s), advantage (s), solution (s) for problem (s), or any component (s) that may bring or make any advantage, advantage or solution more prominent. Is not to be construed as an important, essential or indispensable feature or component of any or all claims. For simplicity, the various features of the invention described in connection with a single embodiment may also be provided separately or in any subcombination. In addition, references to values stated in ranges include all values within that range.

Claims (23)

As a circuit for an electronic device, The circuit, A selection unit comprising a control terminal, a first terminal, and a second terminal, wherein the control terminal is connected to a first selection line, and the first terminal of the selection unit is connected to a data line; A data holder unit comprising a first terminal and a second terminal, the first terminal of the data holder unit being connected to a second terminal of the selection unit; An electronic device comprising a first electrode and a second electrode, the electronic device being connected to a first power line; A transistor comprising a first gate electrode, a first source / drain region, and a second source / drain region, wherein the first gate electrode is connected to a first terminal of the data holder unit and a second terminal of the selection unit; The first source / drain area is connected to a first electrode of the electronic device and is coupled to a second terminal of the data holder unit, and the second source / drain area is connected to a second power line. In the circuit, the transistor is the only transistor in both its source / drain region in the conduction path between the first power line and the second power line; and A switch comprising a control terminal, a first terminal, and a second terminal, the control terminal of the switch being connected to the first selection line, the first terminal of the switch being connected to the first electrode of the electronic device; The second terminal of the switch is connected to a reference voltage line; And the selection unit and the switch are configured to turn on at about the same time and the selection unit and the switch are configured to turn off at about the same time. The circuit of claim 1, wherein the transistor comprises a second gate electrode coupled to a signal line. The circuit of claim 1, wherein the second terminal of the data holder unit is connected to a first electrode of the electronic element. 4. The circuit of claim 3, wherein the second source / drain region of the transistor is connected to the second power line. The circuit of claim 1, wherein the channel region of the transistor is formed using a-Si, CGS, LTPS, or a combination thereof. The circuit of claim 1, wherein each of the selection unit and the switch comprises a transistor. The circuit of claim 1, wherein the control terminal of the switch is connected to the first selection line. The method of claim 1, further comprising a second selection line different from the first selection line, And the reference voltage line is the second select line. The circuit of claim 1, wherein the reference voltage line and the first power line are at approximately the same potential. 10. The apparatus of claim 9, further comprising an inverter having an input terminal and an output terminal, The input terminal is connected to the first selection line, And the output terminal is connected to a control terminal of the switch. The circuit of claim 1, wherein the reference voltage line is configured to be at a voltage such that no significant current flows through the electronic device when the switch is closed. An electronic device comprising a pixel array, Wherein each pixel comprises the circuit of claim 1. An organic electronic device comprising the circuit of claim 1. As a method of using an electronic device, The electronic device, A selection unit connected to the selection line and the data line, A data holder unit connected to the selection unit, An electronic device connected to the first power line, A transistor comprising a first source / drain region and a second source / drain region, the transistor being coupled to the data holder unit, the selection unit and the electronic device, the transistor being coupled to a second power line, Within the pixel, the transistor is the only transistor in both its source / drain region in the conduction path between the first power line and the second power line; and A switch coupled to the select line and coupled to the electronic device and a reference voltage line, The method, Writing data to the pixel, wherein the writing comprises: Turning on the selection unit and the switch at about the same time, and Turning off the transistor; and Driving the electronic device, wherein driving comprises: Turning off the selection unit and the switch at about the same time, and And turning on the transistor. The semiconductor device of claim 14, wherein the transistor comprises a first gate electrode connected to the selection unit and a second gate electrode connected to a signal line, Turning off the transistor includes transmitting a signal along the signal line to the second gate electrode; And the signal has a voltage sufficient to turn off the transistor. The method of claim 14, wherein the switch has a control terminal connected to the selection line. The method of claim 16, wherein the switch has a first terminal connected to the first electrode of the electronic device, And the switch has a second terminal connected to a second electrode or another select line of the electronic device. 15. The method of claim 14 wherein the switch is connected to only one pixel. 15. The method of claim 14, wherein during writing, a significant amount of charge is dissipated across the electronic device. The method of claim 14, wherein the electronic device comprises an organic active layer. 15. The device of claim 14, wherein the selection unit and the switch are configured to turn on at about the same time, And the selection unit and the switch are configured to turn off at about the same time. 15. The apparatus of claim 14, wherein the frame time is a sum of a writing time for recording data and a driving time for driving the electronic element, And the driving time is at least one half of the frame time. 15. The method of claim 14, wherein the electronic device does not emit a significant amount of radiation during writing.

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