KR20070074955A - Manufacturing method of semiconductor device using sp3-rich amorphous carbon as hard mask - Google Patents

Manufacturing method of semiconductor device using sp3-rich amorphous carbon as hard mask Download PDF

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KR20070074955A
KR20070074955A KR1020060003135A KR20060003135A KR20070074955A KR 20070074955 A KR20070074955 A KR 20070074955A KR 1020060003135 A KR1020060003135 A KR 1020060003135A KR 20060003135 A KR20060003135 A KR 20060003135A KR 20070074955 A KR20070074955 A KR 20070074955A
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amorphous carbon
hard mask
film
semiconductor device
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KR100827528B1 (en
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임희열
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주식회사 하이닉스반도체
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    • E03WATER SUPPLY; SEWERAGE
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    • E03F5/04Gullies inlets, road sinks, floor drains with or without odour seals or sediment traps
    • E03F5/06Gully gratings
    • EFIXED CONSTRUCTIONS
    • E03WATER SUPPLY; SEWERAGE
    • E03FSEWERS; CESSPOOLS
    • E03F5/00Sewerage structures
    • E03F5/04Gullies inlets, road sinks, floor drains with or without odour seals or sediment traps
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    • EFIXED CONSTRUCTIONS
    • E03WATER SUPPLY; SEWERAGE
    • E03FSEWERS; CESSPOOLS
    • E03F5/00Sewerage structures
    • E03F5/04Gullies inlets, road sinks, floor drains with or without odour seals or sediment traps
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Abstract

A method for manufacturing a semiconductor device using sp3-rich amorphous carbon as a hard mask is provided to allow an alignment measurement even if the hard mask is thicker than a preset value. A layer to be etched is formed on a semiconductor substrate. An amorphous carbon film to be used as a first hard mask is deposited on the layer to be etched. A photoresist pattern is formed on the amorphous carbon film. The photoresist pattern is used as an etching mask so that the lower layers are sequentially etched to form a pattern of the layer to be etched. The amorphous carbon film includes a sp3 carbon element bonding structure whose molar fraction is equal to or larger than 45%. The amorphous carbon film is deposited by using a CVD(chemical vapor deposition) scheme in which CH4 + H2 gas is used as a carbon source, the temperature is equal to or lower than 200 degrees Celsius, the pressure ranges from 0.01 to 1 mtorr, and the ion energy ranges from 50 to 500 eV so that the carbon element bonding structure is changed from sp2 structure to sp3 structure.

Description

sp3 분율이 높은 비정질 탄소를 하드마스크로 이용하는 반도체 소자의 제조방법{Manufacturing method of semiconductor device using sp3-rich amorphous carbon as hard mask}Manufacturing method of semiconductor device using sp3-rich amorphous carbon as hard mask}

도 1은 sp2 탄소 결합을 갖는 구조를 나타낸다.1 shows a structure with sp2 carbon bonds.

도 2는 sp3 탄소 결합을 갖는 구조를 나타낸다.2 shows a structure with sp3 carbon bonds.

본 발명은 sp3 분율이 높은 비정질 탄소를 하드마스크로 이용하는 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 반도체 소자 제조 공정 중 하드마스크로 비정질 탄소 (amorphous carbon)를 화학기상 증착 방법 (Chemical Vapor Deposition: 이하 "CVD"라 약칭함)으로 증착할 때 탄소 원자 결합 구조가 sp2 구조에서 sp3 구조로 변경되도록 함으로써 하드마스크가 특정 두께 이상으로 도포된 경우에도 정렬 (alignment) 측정을 가능하게 하는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device using amorphous carbon having a high sp3 fraction as a hard mask, and more particularly, to chemical vapor deposition of amorphous carbon as a hard mask during a semiconductor device manufacturing process. (Hereinafter abbreviated as " CVD ") to change the carbon atom bonding structure from the sp2 structure to the sp3 structure, thereby enabling alignment measurement even when a hard mask is applied over a specific thickness. It relates to a manufacturing method.

90㎚ 이하의 미세 패턴 형성시 패턴의 쓰러짐 현상이 발생하는 것을 방지하기 위하여 포토레지스트 막의 두께를 100㎚ 이하까지 낮춰야 한다. 이 경우, 포토 레지스트 막은 하부층을 식각할 때에 충분히 견딜 정도의 두께가 되지 않기 때문에 새로운 하드마스크가 필요하게 되고, 이러한 하드마스크의 한 예로서 비정질 탄소막을 이용하였다.The thickness of the photoresist film should be lowered to 100 nm or less in order to prevent the collapse of the pattern when forming the fine pattern of 90 nm or less. In this case, since the photoresist film does not become sufficiently thick to etch the lower layer, a new hard mask is required, and an amorphous carbon film is used as an example of such a hard mask.

상기 비정질 탄소는 유기물과 같은 성질을 갖는 것으로, 하부층을 식각할 때에 충분한 선택비를 나타낼 뿐만 아니라 두껍게 코팅하는 것이 가능하기 때문에, 포토레지스트 막을 충분히 얇게 형성하여도 두꺼운 하부층을 식각할 수 있는 하드마스크로서의 사용이 가능하다. 이는 비정질 탄소가 400℃ 이상의 고온에서 견디기 때문에 비정질 탄소로 형성되는 하드마스크 상부에 또 다른 하드마스크의 역할을 하는 실리콘 산화질화막 (SiON)을 증착할 수 있어 가능한 것이다. 즉, 비정질 탄소와 실리콘 산화질화막의 적층 형태를 이용하여 식각 선택비를 조절함으로써 비정질 탄소 하드마스크의 두께를 충분히 두껍게 할 수 있고, 이에 따라 하부층의 타겟 물질을 충분히 식각할 수 있다.The amorphous carbon has the same properties as an organic material, and exhibits a sufficient selectivity when etching the lower layer, and can be coated thickly, so that even if the photoresist film is sufficiently thin, it can be etched as a hard mask. Can be used. This is possible because a silicon oxynitride film (SiON) serving as another hard mask can be deposited on the hard mask formed of amorphous carbon because the amorphous carbon withstands a high temperature of 400 ° C. or higher. That is, the thickness of the amorphous carbon hard mask can be sufficiently thick by controlling the etch selectivity using a stacked form of amorphous carbon and silicon oxynitride film, thereby sufficiently etching the target material of the lower layer.

그러나 비정질 탄소 하드마스크는 그 분자 구조에 의해서 두께가 두꺼워짐에 따라 불투명해져서 반도체 공정 측정상의 중요한 요소인 정렬 측정이 불가능해지므로 특정 두께 이상에서는 사용하지 못한다는 단점이 있다. 이는 비정질 탄소의 결합 구조가 전체적으로 sp2 구조로 이루어져 있고, 이러한 구조의 특성상 일정 두께를 넘어서게 되면 빛이 투과하지 못하는 불투명성을 가지게 되기 때문이다. 즉, 하부층으로 고유전 물질 (high k material)을 사용한 경우에는 하부층에 단차가 있는 경우는 3000Å까지, 단차가 없는 경우는 1500Å까지 그 식별이 가능하며, 저유전 물질 (low k material)을 사용한 경우에는 7000Å까지만 그 두께를 올릴 수 있 으므로, 전반적인 반도체 공정에서 하드마스크로 사용하기에는 한계가 있다.However, the amorphous carbon hard mask becomes opaque as its thickness increases due to its molecular structure, making alignment measurement, an important factor in semiconductor process measurement, impossible. This is because the bonding structure of the amorphous carbon is composed entirely of sp2 structure, and because of the nature of this structure has a opacity that the light does not transmit if it exceeds a certain thickness. In other words, when a high k material is used as a lower layer, it can be identified up to 3000Å when there is a step in the lower layer, and up to 1500 가 when there is no step, and when a low k material is used. Since the thickness can be increased up to 7000Å, there is a limit to use as a hard mask in the overall semiconductor process.

이에, 본 발명의 목적은 특정 두께 이상에서도 투명성을 유지하여 정렬 측정할 수 있는 비정질 탄소를 하드마스크로 이용하는 반도체 소자의 제조방법을 제공하는 것이다.Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device using amorphous carbon as a hard mask that can be aligned and measured while maintaining transparency even above a certain thickness.

상기와 같은 목적을 달성하기 위하여 본 발명에서는 반도체 소자 제조 공정 중 하드마스크로 비정질 탄소를 CVD 방법으로 증착할 때 탄소 원자 결합 구조가 sp2 구조에서 sp3 구조로 변경되도록 함으로써 하드마스크가 특정 두께 이상으로 도포된 경우에도 정렬 측정을 가능하게 하는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, in the present invention, when the amorphous carbon is deposited by the CVD method as a hard mask in the semiconductor device manufacturing process, the carbon atom bond structure is changed from the sp2 structure to the sp3 structure so that the hard mask is applied to a specific thickness or more. Even if the present invention provides a method for manufacturing a semiconductor device that enables alignment measurement.

이하 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail.

본 발명에서는, 반도체 기판 상부에 피식각층을 형성하는 단계;In the present invention, forming an etching target layer on the semiconductor substrate;

상기 피식각층 상부에 제1 하드마스크로서 탄소 원자 결합구조로서 sp3 구조가 지배적인 비정질 탄소막을 증착하는 단계;Depositing an amorphous carbon film having a sp3 structure as a carbon atom bonding structure as a first hard mask on the etched layer;

상기 비정질 탄소막 상부에 포토레지스트 패턴을 형성하는 단계; 및Forming a photoresist pattern on the amorphous carbon film; And

상기 포토레지스트 패턴을 식각 마스크로 하부의 층들을 순차적으로 식각하여 피식각층 패턴을 형성하는 단계를 포함하는 반도체 소자의 제조방법을 제공한다.A method of manufacturing a semiconductor device includes forming an etched layer pattern by sequentially etching the lower layers using the photoresist pattern as an etch mask.

이때 sp3 구조가 지배적이라는 의미는, 비정질 탄소막 내에 sp3 탄소 원자 결합구조가 45% 이상 포함되어 있는 것을 의미한다.In this case, the sp3 structure is dominant, meaning that at least 45% of the sp3 carbon atom bonding structure is included in the amorphous carbon film.

이때 상기 비정질 탄소막은 탄소원 CH4 + H2 가스, 온도 상온~200℃, 압력 0.01~1mTorr, 이온 에너지 50~500eV 조건의 화학기상 증착 (CVD) 방법으로 증착되어 탄소 원자 결합구조가 sp2 구조에서 sp3 구조로 변경된다.In this case, the amorphous carbon film is deposited by a chemical vapor deposition (CVD) method of a carbon source CH 4 + H 2 gas, a temperature from room temperature to 200 ° C., a pressure of 0.01 to 1 mTorr, and an ion energy of 50 to 500 eV. To a structure.

상기 포토레지스트 패턴을 형성하기 전에, 비정질 탄소막 상부에 제2 하드마스크막을 도포하는 단계를 더 포함할 수 있다.Before forming the photoresist pattern, the method may further include applying a second hard mask layer over the amorphous carbon layer.

제2 하드마스크 막은 실리콘 산화질화막, 실리콘 산화막 또는 실리콘 질화막 등을 사용할 수 있다.As the second hard mask film, a silicon oxynitride film, a silicon oxide film, a silicon nitride film, or the like may be used.

이때, 상기 제1 하드마스크막은 100~500㎚의 두께로 형성되고, 상기 제2 하드마스크막은 25~100㎚의 두께로 형성되며, 상기 포토레지스트 막은 100~500㎚의 두께로 형성되는 것이 바람직하다.In this case, the first hard mask film is formed to a thickness of 100 ~ 500nm, the second hard mask film is formed to a thickness of 25 ~ 100nm, the photoresist film is preferably formed to a thickness of 100 ~ 500nm. .

전술한 바와 같이, 비정질 탄소는 그 구조가 전형적인 판상 구조인 sp2로 대부분이 이루어져 있다. 이러한 구조는 탄소의 전형적인 흑연 (graphite) 구조로 적층 형태상 불투명성을 가지게 되고, 이로 인해 일정 두께 이상에서는 반도체 공정상의 정렬 측정이 불가능하다.As described above, the amorphous carbon is composed mostly of sp2 whose structure is a typical plate-like structure. This structure is a typical graphite (graphite) structure of carbon has a opacity in the form of a laminate, it is impossible to measure alignment in the semiconductor process above a certain thickness.

따라서, 본 발명에서는 현재 일반적으로 사용되고 있는 비정질 탄소의 지배적인 결합 구조인 sp2 구조를 증착 분위기를 조절하여 sp3가 지배적인 구조로 변경함으로써 구조적 특성을 이용하여 투명성을 확보하고자 하였다. sp3 구조는 현재 다이아몬드와 같은 탄소의 혼성 결합 구조로 sp2가 흑연의 2차원적인 구조인 반면 sp3는 정사면체의 3차원적 결합 구조로 경도가 증가할 뿐만 아니라 sp2 구조에 비하여 투명성이 매우 높다.Therefore, in the present invention, the sp2 structure, which is the dominant bonding structure of amorphous carbon, which is currently used in general, is modified to control the deposition atmosphere to change the structure of sp3 to the dominant structure, thereby securing transparency using structural characteristics. The sp3 structure is a hybrid bond structure of carbon such as diamond, and sp2 is a two-dimensional structure of graphite, whereas sp3 is a three-dimensional bond structure of tetrahedron, which not only increases hardness but also has higher transparency than sp2 structure.

이러한 sp2 구조의 sp3 구조로의 변경은 CVD 증착시 이온화된 탄소 이온이 기판과 어느 정도 세기로 충돌 (bombardment) 하는가에 따라서 sp3 구조의 형성이 좌우될 수 있다. 본 발명의 경우 sp3 분율이 높은 비정질 탄소막을 형성하기 위하여 상기한 바와 같이 기존의 CVD 조건에서 이온 에너지를 50~500eV 조건으로 함으로써 비정질 탄소막의 sp3 분율을 크게 높일 수 있다. The change of the sp2 structure into the sp3 structure may depend on the strength of the bombardment of the ionized carbon ions with the substrate during CVD deposition. In the present invention, in order to form an amorphous carbon film having a high sp3 fraction, the sp3 fraction of the amorphous carbon film can be greatly increased by setting ion energy at 50 to 500 eV under the conventional CVD conditions as described above.

이때 이온 에너지가 50eV 미만이면 이온 에너지에 의해 결정되는 충돌의 강도가 종래의 공정과 유사하여 sp3 구조가 잘 형성되지 않고, 500eV를 초과하는 이온 에너지가 가해지면 비정질 탄소막의 스트레스에 의한 접착력 문제가 발생하여 탄소막이 손상되므로 응용이 불가능하다.At this time, if the ion energy is less than 50 eV, the impact intensity determined by the ion energy is similar to the conventional process, so that the sp3 structure is not well formed, and when ion energy exceeding 500 eV is applied, a problem of adhesion due to the stress of the amorphous carbon film occurs. This is impossible because the carbon film is damaged.

또한, 기타 CVD 조건을 조절하면 사용하고자 하는 용도에 맞게 비정질 탄소의 구조적 특성을 변화시킬 수 있다.In addition, by adjusting other CVD conditions, the structural properties of amorphous carbon can be varied to suit the intended use.

이상에서 살펴본 바와 같이, 현재 반도체 공정에서 사용되고 있는 비정질 탄소 하드마스크의 지배적인 구조인 sp2 구조를 sp3가 지배적인 구조로 변형시킬 경우 필름의 투명도가 증가하여 반도체 공정상의 측정 요소인 정렬 측정이 쉬워지므로 기존에 사용되고 있는 비정질 탄소 하드마스크의 두께를 상향할 수 있으며 중첩 정확도 (overlay accuracy)가 향상된다. 또한, 비정질 탄소 하드마스크의 두께를 두껍게 할 수 있으므로 포토레지스트의 두께를 감소시킬 수 있어 경제적으로 유리 하고, 하드마스크를 이용하여 식각할 때 타겟 물질을 더욱 깊게 식각할 수 있으며, 하부층 재료의 두께에 따라 하드마스크의 두께를 조절할 수 있으므로 제2의 다른 하드마스크 없이도 식각 공정이 가능하다는 장점도 있다.As described above, when the sp2 structure, which is the dominant structure of the amorphous carbon hard mask currently used in the semiconductor process, is transformed into the dominant structure of the sp3, the transparency of the film is increased, so that alignment measurement, which is a measuring element in the semiconductor process, becomes easy. The thickness of the amorphous carbon hardmask used in the past can be increased and the overlay accuracy is improved. In addition, since the thickness of the amorphous carbon hard mask can be increased, the thickness of the photoresist can be reduced, which is economically advantageous, and the target material can be etched more deeply when etching using the hard mask, and the thickness of the underlying layer material can be increased. Accordingly, since the thickness of the hard mask may be adjusted, an etching process may be performed without using a second hard mask.

Claims (5)

반도체 기판 상부에 피식각층을 형성하는 단계;Forming an etched layer on the semiconductor substrate; 상기 피식각층 상부에 제1 하드마스크로서 비정질 탄소막을 증착하는 단계;Depositing an amorphous carbon film as a first hard mask on the etched layer; 상기 비정질 탄소막 상부에 포토레지스트 패턴을 형성하는 단계; 및Forming a photoresist pattern on the amorphous carbon film; And 상기 포토레지스트 패턴을 식각 마스크로 하부의 층들을 순차적으로 식각하여 피식각층 패턴을 형성하는 단계를 포함하는 반도체 소자의 제조방법에 있어서,In the method of manufacturing a semiconductor device comprising the step of sequentially etching the lower layer using the photoresist pattern as an etching mask to form an etched layer pattern, 상기 비정질 탄소막은 sp3 탄소 원자 결합구조를 45% 이상 포함한 것을 특징으로 하는 반도체 소자의 제조방법.The amorphous carbon film is a semiconductor device manufacturing method, characterized in that containing at least 45% sp3 carbon atom bonding structure. 제 1 항에 있어서,The method of claim 1, 상기 비정질 탄소막은 탄소원 CH4 + H2 가스, 온도 상온~200℃, 압력 0.01~1mTorr, 이온 에너지 50~500eV 조건의 화학기상 증착 (CVD) 방법으로 증착되어 탄소 원자 결합구조가 sp2 구조에서 sp3 구조로 변경되는 것을 특징으로 하는 반도체 소자의 제조방법.The amorphous carbon film is deposited by a chemical vapor deposition (CVD) method with a carbon source CH 4 + H 2 gas, a temperature from room temperature to 200 ° C., a pressure of 0.01 to 1 mTorr, and an ion energy of 50 to 500 eV. Method for manufacturing a semiconductor device, characterized in that is changed to. 제 1 항에 있어서,The method of claim 1, 상기 포토레지스트 패턴을 형성하기 전에, 비정질 탄소막 상부에 제2 하드마스크막을 도포하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방 법.Before forming the photoresist pattern, further comprising applying a second hard mask film over the amorphous carbon film. 제 3 항에 있어서,The method of claim 3, wherein 상기 제2 하드마스크 막은 실리콘 산화질화막, 실리콘 산화막 및 실리콘 질화막으로 이루어진 군에서 선택된 것을 특징으로 하는 반도체 소자 제조방법.The second hard mask film is a semiconductor device manufacturing method, characterized in that selected from the group consisting of silicon oxynitride film, silicon oxide film and silicon nitride film. 제 1 항 또는 제 3 항에 있어서,The method according to claim 1 or 3, 상기 제1 하드마스크막은 100~500㎚의 두께로 형성되고,The first hard mask film is formed to a thickness of 100 ~ 500nm, 상기 제2 하드마스크막은 25~100㎚의 두께로 형성되며,The second hard mask layer is formed to a thickness of 25 ~ 100nm, 상기 포토레지스트 막은 100~500㎚의 두께로 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The photoresist film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 100 ~ 500nm.
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US9899231B2 (en) 2015-01-16 2018-02-20 Samsung Electronics Co., Ltd. Hard mask composition for spin-coating
JP2018197630A (en) * 2017-05-24 2018-12-13 リンナイ株式会社 Bathroom air conditioning and bath system
US20210040618A1 (en) * 2018-05-03 2021-02-11 Applied Materials, Inc. Pulsed plasma (dc/rf) deposition of high quality c films for patterning
US11603591B2 (en) * 2018-05-03 2023-03-14 Applied Materials Inc. Pulsed plasma (DC/RF) deposition of high quality C films for patterning
US11501977B1 (en) * 2021-05-10 2022-11-15 Nanya Technology Corporation Semiconductor device and manufacturing method thereof
WO2024016381A1 (en) * 2022-07-20 2024-01-25 长鑫存储技术有限公司 Semiconductor structure and forming method therefor

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