KR20070054297A - Method for forming drain contact of semiconductor memory device - Google Patents

Abstract

The present invention relates to a method of forming a drain contact of a flash memory device, by dividing all the drain contacts into two groups instead of etching them all at once, thereby making the drain contact distance etched at the same time larger than the space between the actual drain contacts. It is a technique for preventing an attack on the drain contact.

Drain Contact, Space, Mask, Alpha Carbon Film

Description

Method for forming drain contact of flash memory device

1A to 1F are cross-sectional views illustrating a drain contact forming process of a flash memory device according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 11 device isolation film

12 sacrificial nitride film 13 first interlayer insulating film

14: second interlayer insulating film 15: hard mask film

15a: alpha carbon film 15b: SiON film

16: first drain contact hole 17: first polysilicon film

18 second drain contact hole 19 second polysilicon film

20: drain contact

The present invention relates to a method of forming a drain contact of a flash memory device, and more particularly, to a method of forming a drain contact of a flash device for preventing the upper portion of the drain contact from being attacked.

Among the nonvolatile memory devices, flash memory devices may be classified into NAND and NOR types according to the arrangement of memory cells.

NAND-type flash memory devices have one source contact and drain contact for a plurality of, for example, 16 or 32 strings.

Unlike source contacts having a line type structure, drain contacts having a hole type structure formed one per active type have a narrow process space between drain contacts.

Table 1 below shows spaces between drain contacts according to technology.

technology Pitch Active width Field space Drain contact space 70 nm 140 nm 50 nm 90 nm ~ 40 nm 60 nm 120 nm 50 nm 70 nm 20 ~ 30nm 50 nm 100 nm 50 nm 50 nm ~ 10nm 40 nm 60 nm 10-20 nm 45 nm 80 nm 50 nm 30 nm ~ 10nm 40 nm 40 nm ~ 10nm 30 nm 50 nm ~ 10nm

According to the table above, the space between the drain contacts is very narrow, 20 nm or less, for devices with technology of 50 nm or less. As such, when the space between the drain contacts is narrow, the photoresist and the hard mask used as the etch mask are severely lost during the drain contact etching process, resulting in a problem that the upper portion of the drain contact is attacked.

Accordingly, the present invention has been made to solve the above-described problems of the prior art, and a method of forming a drain contact of a flash memory device capable of preventing a phenomenon in which the upper portion of the drain contact is attacked by reducing mask loss during the drain contact etching. The purpose is to provide.

Another object of the present invention is to improve the reliability and yield of the device by improving the failure that the drain contact is attacked.

A drain contact forming method of a flash memory device according to the present invention includes forming an interlayer insulating film on a semiconductor substrate on which a plurality of drain regions are formed, and opening a portion of the drain regions in the interlayer insulating film. Forming a first polysilicon film on the entire surface of the first drain contact hole to fill the first drain contact hole, and patterning the first polysilicon film to form an upper portion of the drain region not opened by the first drain contact hole. Opening the interlayer dielectric layer, forming a second drain contact hole to open drain regions not opened by the first drain contact hole by etching the interlayer dielectric layer using the first polysilicon layer as a mask; Forming a second polysilicon film on the front surface to fill the second drain contact hole; And flatly removing the first and second polysilicon layers so as to remain only in the first and second drain contact holes to form a drain contact.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1A to 1F are cross-sectional views illustrating a drain contact forming process of a flash memory device according to the present invention.

First, as shown in FIG. 1A, an isolation layer 11 is formed on a semiconductor substrate 10 by a trench isolation process to define an active region and a field region, and although not shown, between the source region and the drain region D. Source select transistors and cell transistors and drain select transistors connected in series are formed.

Subsequently, a sacrificial nitride film 12 is formed on the entire surface.

The sacrificial nitride layer 12 serves as an etch stop layer during a subsequent contact etching process, and serves as a buffer when forming the sacrificial nitride layer 12 before forming the sacrificial nitride layer 12. It is good to form an oxide film further.

Then, an oxide film is deposited on the entire surface and planarized to form the first interlayer insulating film 13.

Subsequently, a source contact hole exposing the source region is formed, and a polysilicon film is embedded in the source contact hole to form a source contact.

Then, an oxide film is deposited on the first interlayer insulating film 13 including the source contact to form a second interlayer insulating film 14, and a hard mask film 15 is formed on the second interlayer insulating film 14. Form.

The hard mask layer 15 is alpha carbon (α) having a high etching selectivity with respect to the first and second interlayer dielectric layers 13 and 14, which are etched layers, in order to minimize the attack of the lower layer during the drain contact etching. -carbon, amorphous carbon) film 15a and SiON film 15b are formed by laminating.

The alpha carbon film 15a may be formed to a thickness of 1000 to 2000 GPa, and the SiON film 15b may be formed to a thickness of 200 to 400 GPa.

Subsequently, the first photoresist PR1 may be coated on the hard mask layer 15, and the first interlayer insulating layer 14 may be opened on some of the drain regions D of the drain regions D. One photoresist PR1 is patterned to define only some drain contacts rather than all drain contacts.

At this time, the drain contacts adjacent to each other are not defined at the same time. For example, define an even drain contact and not an odd drain contact, or conversely, an odd drain contact and an even drain contact are not defined.

Therefore, the inter-drain contact distance defined by the first photoresist PR1 is longer than the actual inter-drain contact space.

Next, as shown in FIG. 1B, the hard mask film 15 is patterned by an etching process using the patterned first photoresist PR1 as a mask, and the patterned first photoresist PR1 and the hard mask film are patterned. The second and first interlayer insulating layers 14 and 13 may be etched using the mask 15 to form a first drain contact hole 16 exposing some drain regions D. Referring to FIG.

The distance between the drain contacts defined by the first photoresist PR1 is longer than the actual drain contact space, and the hard mask film 15 has high etching selectivity with respect to the first and second interlayer insulating films 13 and 14. Since the ratio, the amount of the first photoresist PR1 and the hard mask layer 15 lost during the etching process of the first drain contact hole 16 may be reduced. Therefore, the second interlayer insulating layer 14 under the hard mask layer 15 is not attacked during the drain contact etching.

Subsequently, as shown in FIG. 1C, the first photoresist PR1 and the hard mask film 15 are removed. In particular, the alpha carbon film 15a of the hard mask film 15 is removed using an oxygen plasma (O ₂ plasma).

Subsequently, after the sacrificial nitride film 12 under the first drain contact hole 16 is removed by a cleaning process, the first poly has a thickness of 1000 to 2000 kPa on the entire surface thereof so that the first drain contact hole 16 is buried. The silicon film 17 is deposited.

Then, as shown in FIG. 1C, a second photoresist PR2 is applied on the first polysilicon film 17 and exposed so that drain contacts not defined by the first photoresist PR1 are defined. And patterning the second photoresist PR2 in a development process.

For example, if the even-numbered drain contact is defined by the first photoresist PR1, the second photoresist PR2 is patterned so that the odd-numbered drain contact can be defined, and vice versa. The second photoresist PR2 is patterned so that it can be defined.

Therefore, the drain contact distance defined by the second photoresist PR2 is longer than the actual drain contact space.

Subsequently, as illustrated in FIG. 1D, the first polysilicon layer 17 is patterned by an etching process using the patterned second photoresist PR2 as a mask.

As shown in FIG. 1E, the second photoresist PR2 is removed and the second and first interlayer insulating layers 14 and 13 are etched using the patterned first polysilicon layer 17 as a mask. The second drain contact hole 18 is formed, and the sacrificial nitride film 12 under the second drain contact hole 18 is removed by a cleaning process.

First and second interlayer insulating layers 13 and 14, wherein the drain contact distance defined by the second photoresist PR2 is wider than the actual drain contact space, and the first polysilicon film 17 is an etched layer. Since it has a high etching selectivity with respect to, the amount of the first polysilicon film 17 lost during the drain contact etching process is very small. Therefore, the attack of the second interlayer insulating film 14 under the first polysilicon film 17 can be prevented.

Subsequently, as illustrated in FIG. 1F, a second polysilicon film 19 is deposited on the entire surface to fill the second drain contact hole 18.

Subsequently, as illustrated in FIG. 1G, the second and first polysilicon layers 19 and 17 may be flatly removed to expose the second interlayer insulating layer 14, and thus the first and second drain contact holes 16 may be removed. The drain contact 20 is formed by leaving the first and second polysilicon films 17 and 19 only in the cavities 18.

As described above, the present invention has the following effects.

First, since the distance between the drain contacts which are simultaneously etched may be increased than the space between the drain contacts, the attack on the upper portion of the drain contact may be prevented during the etching of the drain contact.

Second, even when the space between the drain contacts is narrow, the problem of the upper part of the drain contact being attacked can be prevented, thereby improving the integration of the device.

Second, since the alpha carbon film and the polysilicon film having a high etching selectivity with respect to the etched layer are used as a mask of the drain contact etching process, an attack on the upper portion of the contact due to the mask loss can be prevented.

Claims (7)

Forming an interlayer insulating film on a semiconductor substrate having a plurality of drain regions formed thereon; Forming a first drain contact hole in the interlayer insulating layer to open some of the drain regions; Forming a first polysilicon film on the entire surface of the first drain contact hole to fill the first drain contact hole; Patterning the first polysilicon film to open the interlayer insulating film over the drain region not opened by the first drain contact hole; Etching the interlayer insulating layer using the first polysilicon layer as a mask to form a second drain contact hole to open drain regions not opened by the first drain contact hole; Forming a second polysilicon film on the entire surface of the second drain contact hole to be filled in; Forming a drain contact by flatly removing the first and second polysilicon layers so as to remain only in the first and second drain contact holes. The method of claim 1, And drain regions open by the first drain contact hole do not neighbor each other. The method of claim 1, The method of claim 1, wherein a hard mask layer is used as an etch mask to form the first drain contact hole. The method of claim 3, wherein And forming the hard mask film as a lamination film of an alpha carbon film and a SiON film. The method of claim 4, wherein And forming the alpha carbon film in a thickness of 1000 to 2000 microseconds. The method of claim 4, wherein And forming said SiON film at a thickness of 200 to 400 microseconds. The method of claim 1, And forming the first polysilicon film in a thickness of 1000 to 2000 microseconds.

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