KR20070031785A - Plasma CVD film formation apparatus provided with mask - Google Patents

Abstract

A plasma CVD apparatus for forming a thin film on a wafer having a diameter Dw and a thickness Tw includes a vacuum chamber, a shower plate, an upper plate, an upper mask member for covering an upper edge portion of a wafer, and a wafer. A side mask member for covering the side portions. The side mask member has an inner diameter of Dw + α, and the upper mask member is disposed at a distance of Tw + β between the bottom surface of the upper mask member and the wafer support surface of the upper plate. Where α is greater than zero and β is also greater than zero.

Description

Plasma CVD film formation apparatus provided with mask

1 is a schematic view showing a typical plasma CVD apparatus.

2 is a schematic view showing one embodiment of the present invention.

3 is a graph showing thickness distributions of films according to embodiments of the present invention when a silicon (Si) bevel mask and a ceramic bevel mask are used, respectively.

4 is a graph showing thickness distributions of films according to embodiments of the present invention when a flat ring and a trench type ring are used, respectively.

5 is a graph showing thickness distributions of films according to embodiments of the present invention when the interval α is set to 0.075 mm, 0.325 mm and 0.575 mm, respectively.

FIG. 6 is a graph showing thickness distributions of films according to embodiments of the present invention when shower plates having diameters of 250 mm, 220 mm and 200 mm, respectively, and with plasma-enhanced spikes are used with a trench type top plate.

7 is a schematic partial cross-sectional view showing one embodiment of the present invention.

8 is a schematic partial cross-sectional view showing an embodiment of the present invention.

9 is a graph showing thickness distributions of films according to embodiments of the present invention when a ceramic bevel mask is used without a mask.

10 is a graph showing thickness distributions of films according to embodiments of the present invention when the interval Ds is set to Dw, Dw + d, Dw + 2d and Dw + 3d, respectively.

11 is a schematic partial cross-sectional view showing an embodiment of the present invention.

12 is a graph showing the thickness distributions of the films according to embodiments of the present invention when shower plates having diameters of 250 mm, 220 mm and 200 mm, respectively, and with plasma-enhanced spikes are used with the flat type top plate.

13 is a chart showing partial cross-sectional views of various embodiments of the present invention.

Explanation of symbols on the main parts of the drawings

1: plasma CVD film forming apparatus 2: heater

3: upper plate 4: wafer

5 gas introduction part 6 reaction chamber

7: First RE Power Source 8: Second RF Power Source

9 upper electrode 10 exhaust part

21: shower plate 22: mask

23: mask support stand 24: edge portion of the upper plate

30 wafer 40 base member

41 gas discharge member 42 protrusion (plasma reinforced spike)

42: gas inlet 60, 60 ', 60 ": mask

61: upper mask member 62: side mask member

70, 70 ', 70 ", 71, 74: top plate

80, 80 ', 80 ", 90, 90', 90": ring structure

The present invention relates to a semiconductor manufacturing apparatus. More specifically, it relates to a plasma chemical vapor deposition (hereinafter referred to as "CVD") film forming apparatus specified by a structure near the top plate.

1 is a schematic diagram of a general plasma processing apparatus. The plasma processing apparatus 1 includes a reaction chamber 6, a gas introduction part 5, a circular upper electrode 9 and a lower electrode including an upper plate 3 and a heater 2. Gas is introduced through a gas introduction section 5 from a gas line (not shown). The circular upper electrode 9 is arranged just below the gas introduction section 5. The upper electrode 9 has a hollow structure, and a plurality of micropores is provided at the bottom thereof so that gas is injected toward the wafer 4. In this case, the upper electrode 9 has a structure capable of replacing the shower plate 11 having a plurality of gas inlets for maintenance and component cost reduction.

In addition, an exhaust port 10 is provided at the bottom of the reaction chamber. The exhaust unit 10 is connected to an external vacuum pump (not shown), whereby the inside of the reaction chamber 6 is evacuated. The upper plate 3 is disposed in parallel to the upper electrode 9. The wafer 4 is supported on the top plate 3, heated by the heater 2, and maintained at a given temperature (about -50 to 650 ° C.). The gas introduction part 5 and the upper electrode 9 are electrically insulated from the reaction chamber 6 and are connected to an external first radio-frequency power source 7. As shown the second RF power source 8 is also connected. Here, reference numeral 12 denotes a ground. Thus, the upper electrode 9 and the lower electrode function as RF electrodes, creating a plasma reaction field in the vicinity of the wafer 4. The type and characteristics of the film formed on the surface of the wafer 4 vary depending on the type and flow rate of the source gas, temperature, RF frequency, plasma spatial distribution, electrical potential distribution, and the like.

However, in the general technique, since a film is formed on the top and side edge portions of the wafer and particles are generated according to the process, it is necessary to prevent the film from being formed on these portions. U.S. Patent No. 4,932,358, Japanese Patent Application Laid-Open No. 4-268724 and U.S. Patent No. 5,304,248 disclose a method in which the edge of a wafer is covered by a shield or seal ring in relation to thermal CVD. The ring is in contact with at least a portion of the wafer.

However, if the method is used in plasma CVD by providing a ring (or mask) at the edge of the wafer, abnormal film growth occurs in the region adjacent to the mask, and thus, as an example, the thickness uniformity of the film may be degraded. Can be.

SUMMARY OF THE INVENTION A first object of the present invention for solving the above problems is to provide a plasma CVD film forming apparatus which prevents the film from being formed on the upper edge portion and the side portion of the wafer and also forms a film having uniform thickness and properties. It is.

A second object of the present invention is to provide a plasma CVD film forming apparatus having a low manufacturing cost and a simple configuration.

It is a third object of the present invention to provide a plasma CVD film formation method in which a film is not deposited on an edge portion of a wafer and realizes high film thickness uniformity.

The present invention may, in various embodiments, implement one or more of the above objects. However, the present invention is not limited to the above objects and embodiments, and may have effects different from the above objects.

According to one aspect of the present invention, a plasma CVD apparatus for forming a thin film on a wafer having a diameter of Dw and a thickness of Tw comprises: (i) a vacuum chamber, (ii) one of two electrodes and the vacuum chamber A shower plate installed within, (i) an upper plate which functions as the other electrode, is movable between an upper position and a lower position, and is installed to be substantially parallel to the shower plate so as to position the wafer thereon; (Iii) an upper mask member disposed at an interval of Tw + β from the wafer support surface of the upper plate to cover the edge portion of the upper surface of the wafer, wherein β is greater than 0 and the gap Tw + β ) Means the distance between the wafer support surface of the upper plate and the bottom surface of the upper mask member), and the upper mask portion Is positioned below the upper mask member to cover the side portion of the wafer when positioned at the upper position, and may include a side mask member having an inner diameter of Dw + α (where α is greater than zero). .

According to an embodiment of the present invention, the β may be about 0.05 to 0.75 mm. For example, the β may be 0.1 mm, 0.2 mm, 0.4 mm, 0.6 mm, 0.7 mm, or the like, and any value between these values may be used.

According to one embodiment of the present invention, the α may be about 0.03 to 4mm, preferably about 0.05 to 2mm. For example, the α may be 0.1 mm, 0.5 mm, 1.0 mm, 1.5 mm, or the like, and any value between these values may be used.

Unwanted film formation at the edge of the wafer can be effectively prevented by the upper and side mask members without compromising film thickness uniformity. The film thickness nonuniformity can be measured by comparing the thickness Tc at the center and the thickness Te near the edge. For example, film thickness nonuniformity can be measured as Te / Tc and maintained at about 10% or less. The wafer may be an oriental flat wafer having a flat portion along its outer edge. In this case, the wafer diameter Dw is defined as the largest diameter of the wafer.

One embodiment of the present invention may include the following embodiments. However, it is not limited to this.

The upper mask member may have a bulk resistivity of about 10 ⁻⁵ to 10 ³ Pa · cm. When a material such as silicon having the volume resistance is used as the upper mask member, formation of an unwanted film at the edge portion of the wafer can be prevented without lowering the film thickness uniformity. In this case, however, the silicon may be deteriorated by etching in the plasma cleaning process, and thus damage to the mask may occur. If a material such as ceramic (eg, Al ₂ O ₃ ) is used as the upper mask member, the problem of deterioration due to etching can be solved. For example, the upper mask member may have a volume resistance of about 10 ⁶ Pa · cm or more. However, the film thickness nonuniformity can be increased by, for example, about 15% by plasma CVD. Therefore, in this case, the shower plate may include a gas discharge member and a base member having a diameter Ds satisfying the following equation (1).

Dw-d <Ds <Dw + 3d ---- (1)

Here, d means the distance between the shower plate and the upper plate.

In addition, the diameter Ds of the shower plate may satisfy Dw-0.5d <Ds <Dw + 2.5d, Dw <Ds <Dw + 2d, Dw + 0.5d <Ds <Dw + 1.5d, and the like. Any range defined by the combination can be satisfied.

In the above, the enhanced plasma region can be sufficiently controlled, whereby the film uniformity can be improved. In this case, the d may be in the range of about 3 to 50 mm (eg, 7 to 25 mm or 10 to 20 mm).

In one embodiment of the present invention, the upper mask member and the side mask member may be provided integrally and constitute a bevel mask. In another embodiment, the side mask member may be part of the upper mask member. In another embodiment, the side mask member may be part of a dielectric ring structure installed at the edge of the top plate.

In one embodiment of the invention, the side mask member may be configured in whole or in part by the dielectric ring structure or the bevel mask. For convenience, the unitary member including the upper mask member may be referred to as a "bevel mask" or "mask". Thus, the bevel mask includes at least the upper mask member and may further include some or all of the side mask members.

When the side mask member is constituted by a part of the upper mask member, the top plate itself may be a dielectric (eg, AlN (aluminum nitride) top plate). In addition, the dielectric upper plate may be mounted on a separate block, and the block may be provided with a heater and an electrode. Alternatively, heaters and / or electrodes may be embedded within the dielectric top plate.

In one embodiment of the present invention, the gas discharge member may have a flat one surface. In another embodiment, the gas discharge member may be constituted by a plurality of gas inlets and plasma enhanced spikes protruding downward from a surface on which the plurality of gas inlets are formed. The gas discharge member has a diameter Ds, and Ds may be an outer diameter of a region defined by outermost spikes among the plasma enhanced spikes. In one embodiment, the region defined by the outermost inlets among the plurality of gas inlets may have a diameter Dh that satisfies Equation 2 below.

Ds-2d <Dh ---- (2)

Also, as an example, the diameter Dh may satisfy a condition of Ds-d <Dh.

The inlets may have a diameter of about 0.2 to 2.0 mm (eg, about 0.4 to 1.0 mm), and the spikes may have a length of about 1 to 10 mm (eg, about 2 to 6 mm). Can be. The shower plate with plasma enhanced spikes is disclosed in US patent application Ser. No. 11 / 061,986 filed Feb. 18, 2005 by ASM Japan KK, one of the applicants of the present invention, in one embodiment of the present invention. Can be used.

In one embodiment of the present invention, the top plate may exhibit conductivity. In addition, an outer annular recess may be formed around the edge of the top plate, and the wafer may be supported on a dielectric ring structure located on the annular recess. The dielectric ring structure may have an inner annular recess. The plane formed by the top edge surface of the dielectric ring structure may be located higher than the plane formed by the top surface of the conductive top plate. The dielectric ring structure may have an inner diameter of about 0.8 to 1.2 Dw (eg, about 0.9 to 1.1 times the wafer diameter (Dw)). In the above, the area of the enhanced plasma can be sufficiently controlled, whereby the film uniformity can be improved.

In one embodiment of the present invention, the upper mask member has a thickness of about 2 mm or less (eg, 0.3 mm, 0.5 mm, 1.0 mm, 1.5 mm and possible values selectable between them) at the inner edge portion. It may have an inwardly tapered portion (preferably annular). In one embodiment, the upper mask member is about 0.3 to 3 mm (eg, 0.5 mm, 1.0 mm, 1.5 mm, 2.0 mm, 2.5 mm and possibly between them) from the outermost edge of the wafer. The upper surface of the wafer in the range of numerical values).

In the above, where numerical ranges are defined by two numerical values, the numerical values may be included or excluded in the range.

In one embodiment of the present invention, the bevel mask may be made of aluminum, aluminum oxide, aluminum nitride, silicon, silicon oxide, silicon carbide, silicon nitride, boron nitride, metal impregnated ceramic, etc., which are sole Or in the form of a combination.

In one embodiment of the present invention, the upper plate may have an outer diameter (Dss) satisfying the following equation (3).

1.04Dw <Dss <1.5Dw ---- (3)

In addition, for example, the outer diameter Dss may satisfy 1.1Dw <Dss <1.3Dw. Here, the side mask member can be located on the upper edge surface of the top plate in the upper position and outside the wafer. Here, the upper edge surface need not be the uppermost surface of the upper plate but may be the lowermost surface. In another embodiment, the side mask member may be located on the upper edge surface of the dielectric ring structure outside of the wafer.

In all of the above embodiments, components used in one embodiment of the present invention may be used in other embodiments, except that the replacement of the components is not feasible or does not produce an effect contrary to the object of the present invention. Replacement can be used.

According to one aspect of the present invention, the present invention provides a method of forming a thin film having a film thickness nonuniformity of about 10% or less on a wafer using plasma CVD. The thin film forming method comprises the steps of: (i) placing a wafer on a top plate installed substantially parallel to the shower plate, and (ii) the top mask member is greater than zero (preferably between about 0.05 and 0.75 mm). Cover the top edge portion of the wafer at intervals, and a side mask member is disposed on the edge of the top plate to cover the side portions of the wafer at intervals greater than zero (preferably about 0.05 to 2 mm). Positioning the upper mask member and (i) applying radio-frequency (RF) power between the top plate and the shower plate to form a thin film on the wafer using plasma CVD. have.

For example, the above embodiments may include the following embodiments. However, it is not limited to this.

The method may further comprise providing the shower plate, wherein the shower plate may comprise a gas discharge member and a base member. The gas discharge member may have a diameter Ds satisfying Dw−d <Ds <Dw + 3d. Here, Dw means the diameter of the wafer, and d means the distance between the shower plate and the upper plate.

The method may further comprise providing the top plate. The top plate is conductive and may have an outer annular recess around the edge. The wafer may be supported on a dielectric ring structure located on the annular recess.

The method may further comprise providing the upper mask member. The upper mask member may have a thickness of about 2 mm or less at an inner edge and have an inclined portion inwardly. In addition, the upper mask member may be made of aluminum, aluminum oxide, aluminum nitride, silicon, silicon oxide, silicon carbide, silicon nitride, boron nitride, metal impregnated ceramic, etc., which may be used alone or in combination. Can be used as

The method may further comprise providing the top plate. The upper plate has an outer diameter Dss, and the outer diameter Dss satisfies 1.04Dw <Dss <1.5Dw with respect to the diameter Dw of the wafer.

In the method embodiments, the elements used in the embodiment of the device may be used alone or in combination.

The objects and effects of the present invention have been described as described above to summarize the advantages achieved by overcoming the present invention and related art. Of course, not all such objects or advantages may be achieved in accordance with any particular embodiment of the present invention. Thus, for example, those skilled in the art may perform or implement in a way that optimizes or implements the advantages or specific advantages described herein, even if they do not necessarily implement other objects or advantages as suggested or described herein. It will be appreciated.

In another aspect, the features and advantages of the present invention will become apparent from the following detailed description of the embodiments.

The above features of the present invention will be described in more detail with reference to the drawings of the embodiments. However, embodiments of the present invention are not intended to limit the scope of the present invention but are merely described for the purpose of clearly describing the present invention. The drawings are exaggerated for the purpose of explanation.

Although not limited thereto, a wafer that can be processed in embodiments of the present invention is a wafer having a thickness of about 0.725 ± 0.025mm and a diameter of about 200mm, having a thickness of about 0.775 ± 0.025mm and a diameter of about 300mm Wafers and the like. It can be applied according to wafer size without limitation by selecting a bevel mask having appropriate dimensions for the wafer to be processed. Also, if necessary, it can be appropriately selected depending on the top plate and shower plate wafer sizes. In the case of an oriental flat wafer, the mask and the shower plate may be configured to correspond to the outer shape of the oriental flat wafer. In addition, in the case of a notched wafer, the mask may be configured to cover the notched region using a local inner extension portion corresponding to the notched region. "Diameter" generally means the maximum diameter.

In embodiments of the invention, the bevel mask is not in contact with any part of the wafer. When the mask is in contact with the wafer, particles may be generated. When the wafer and the mask are spaced apart from each other, irregular plasma discharge may occur. When the gap between the wafer and the mask becomes large, film formation on the upper surface of the edge portion of the wafer can be prevented. In view of the above, in one embodiment, the distance β between the bottom face of the upper mask member and the top face of the wafer may be greater than zero (preferably between about 0.05 and 0.75 mm; see Example 3 and FIG. 5). have. Also, as an example, the spacing α between the inner side of the side mask member and the side of the wafer may be greater than zero (preferably between about 0.05 and 2 mm).

As shown in A1, B1, and C1 of FIG. 13, the side mask member 62 may be constituted by the bevel mask 60. In this embodiment, the side mask member 62 and the upper mask member 61 may be integrally formed or cast, thereby forming the bevel mask 60.

As another example, as shown in A2, B2, and C2 of FIG. 13, the side mask member 62 'may include a bevel mask 60' and a ring structure 90 '/ 80' or top plate 70 '. It can be configured by the edge protrusion 91 of.

As another example, as shown in A3, B3, and C3 of FIG. 13, the side mask member 62 "may have edge projections 91 of the ring structure 90" / 80 "or top plate 70". It can be configured by ').

In all cases, the spacing α can be appropriately determined as the distance between the surface of the side mask members 62, 62 'and 62 "and the side portions of the wafer.

The bevel masks 60, 60 ′ and 60 ″ may be positioned on the ring structures 90, 90 ′ and 90 ″, respectively, without trenches as shown in A1, A2 and A3 of FIG. 13.

In another embodiment, the bevel masks 60, 60 'and 60 "are formed with the ring structures 80, 80' and 80" with trench 82 as shown in B1, B2 and B3 of FIG. Can be positioned on each).

As another example, the bevel masks 60, 60 'and 60 "are positioned on the top plates 70, 70' and 70", respectively, as shown in C1, C2 and C3 of FIG. Can be.

In another embodiment, the bevel mask may not be located on the ring structure or the top plate and may be supported by another structure, such as lifting pins.

In C2 and C3 of Figure 13, the top plate 70 'or 70 "includes a protrusion 91 or 91' having a top surface higher than the wafer support portion 92. Thus, plasma excitation at the edge portion In order to control the excitation, the top plate may be preferably made of a dielectric such as aluminum oxide (AlN), whereas in A1 to A3 and B1 to B3 of FIG. 13, the top plate may be a conductive material. The ring structure may be a dielectric.

In addition, in C3 of FIG. 13, the heater 85 and / or electrodes may be embedded in the top plate 70 ″. In C2 of FIG. 13, the dielectric top plate may be mounted on a separate block and Heaters and / or electrodes may be installed in the block.

A1, B1, and C1 of FIG. 13 will be further described in FIGS. 11, 8, and 7, respectively.

The mask may be disposed on a separate member, such as mask lifting members vertically installed around the top plate or the top plate or mask lifting pins inserted through holes provided near the edge of the top plate outside the wafer location area. have. In addition, the mask may be suspended from the upper portion of the reactor and may be supported on a support extending from the sidewall of the reactor. The mask may be structurally connected to the support member, or may be simply located on a predetermined member without being connected to any member.

The mask may be made of aluminum, aluminum oxide, aluminum nitride, silicon, silicon oxide, silicon carbide, silicon nitride, boron nitride, metal impregnated ceramic, or the like, which may be used alone or in combination. . When a material having a volume resistance similar to that of the wafer (for example, silicon having a volume resistivity of about 10 ⁻⁵ to 10 ³ Pa · cm) is used as the bevel mask, the wafer without lowering the film thickness uniformity Undesired formation of the film at the edge of can be prevented (see Example 1 of FIG. 3).

However, silicon may be degraded by etching in the plasma cleaning process, which may cause damage to the mask. When a material such as ceramic (eg, Al ₂ O ₃ ) is used as the bevel mask, the problem of deterioration due to the etching can be solved. For example, the bevel mask may have a volume resistivity of about 10 ⁶ Pa · cm or more, and as another embodiment, may have a volume resistivity of about 10 ⁻⁵ to 10 ⁶ Pa · cm. However, the film thickness nonuniformity can be increased by about 15% by plasma CVD (see Example 1 of FIG. 3).

The top surface of the bevel mask faces the shower plate (or top electrode) and is exposed to the plasma. In one embodiment, when the mask is a dielectric, a silicon wafer having a thickness of about 0.8 mm at the site covered by the dielectric mask is placed on the top plate (or bottom electrode) and on the top of the wafer. Covered by the dielectric mask having a thickness on the order of 0.5 to 1 mm. In addition, the mask has a thickness required to provide sufficient strength from a processing viewpoint, for example about 2 to 5 mm at the outer edge of the wafer outline. As a result, the silicon wafer surface inside the inner edge of the mask and the ceramic portion outside the inner edge of the mask are electrically non-uniform with respect to the opposing electrode and the plasma. For this reason, nonuniform growth of film thickness occurs on the silicon wafer. For example, a film having a non-uniform thickness can be grown by local plasma concentration at about 0.5 to 1.0 mm from the inner edge of the mask.

According to an embodiment of the present invention, with respect to a portion outside the inner edge of the mask where plasma concentration occurs, plasma concentration around the inner edge of the mask is reduced by increasing the effective distance between the upper electrode and the lower electrode. In this way, film thickness uniformity can be realized. The effective distance means an electrical distance between the upper and lower electrodes in consideration of a capacitor and need not be actual or physical distance.

When a shower plate with protrusions (plasma enhanced spikes) is used, it corresponds to an inner region surrounded by the inner edge of the mask to adjust plasma intensity on a portion outside the inner edge of the mask. Placing the protrusions only on the inner portions may reduce plasma concentration near the inner edge of the mask.

Additionally, when a flat shower plate without protrusions is used, plasma concentration can be reduced near the inner edge of the mask by increasing the effective distance between the upper and lower electrodes in the region outside the inner edge of the mask.

Also, the effective distance between the upper and lower electrodes can be adjusted by placing a dielectric ring structure on the edge of the upper plate (lower electrode).

According to an embodiment of the present invention, the shower plate may include a gas discharge member and a base member. The gas discharge member has a diameter Ds satisfying Dw-d < Ds < Dw + 3d. Here, Dw means the diameter of the wafer, d means the distance between the shower plate and the upper plate. In another embodiment, the diameter Ds is Dw−0.5d <Ds <Dw + 2.5d, Dw <Ds <Dw + 2d, Dw + 0.5d <Ds <Dw + 1.5d, or the minimum and Other combinations of maximum values may be satisfied. In the above, the enhanced plasma region can be controlled to such an extent that the film uniformity can be improved (see Embodiment 5 of FIG. 10, Embodiment 4 of FIG. 6, and Embodiment 6 of FIG. 13). As used herein, “a bulk resistivity” means a resistance of a material constituting the mask, not a coating layer that may be formed on the mask.

According to an embodiment of the present invention, an upper portion of the bevel mask (the upper mask member) has a thickness of about 2 mm (for example, 0.5 to 1 mm) or less at an inner edge and is inwardly tapered portion. Has In one embodiment, the tapered angle may be about 10 to 45 degrees or 20 to 30 degrees with respect to the top surface of the wafer or the top plate. In one embodiment, the bevel mask may cover the upper surface of the wafer in the range of about 0.3 to 3mm from the outermost edge of the wafer. The covered range may be applied to the length of the inclined portion. Such configurations can affect plasma intensity near the wafer edge and enable high film thickness uniformity.

According to an embodiment of the present invention, a plurality of gas inlets and protrusions protruding from the surface are formed on the surface of the shower plate. 7 shows a partial cross-sectional view of one embodiment of the present invention. The drawings are exaggerated for the purpose of explanation. For example, the mask 60 actually contacts the upper edge surface of the top plate 70 in this embodiment.

In addition, a heater is not shown in this figure. The heater may be embedded in the upper plate, as shown in C3 of FIG. 13. Alternatively, the heater may be installed separately from the upper plate. For example, the top plate may be located on the heater.

The shower plate 21 may include a base member 40 and a gas discharge member 41. The protrusions (plasma reinforced spikes) 42 are uniformly disposed around the fine gas inlets 43 for introducing gas and may have a polygonal column or polygonal pyramid shape. For example, it may have a hexagonal pillar or a square pyramid shape.

By roughly matching the diameter Ds of the area where the protrusions are disposed to the inner diameter Dm of the bevel mask 60, abnormal film thickness growth near the inner edge of the mask can be prevented, thereby providing a uniform thickness. A film having can be obtained. As described above, the diameter Ds satisfies the inequality Dw-d <Ds <Dw + 3d, and also the equation (Dw-Dm) = 2γ (e.g., γ is 0.5 to 2.5 mm). do. Thus, the inequality Dm + 2γ-d <Ds <Dm + 2γ + 3d is also satisfied. Here, γ may be about 1% to about 10% of dm, so the inequality Dm-d <Ds <Dm + 3d may be substantially satisfied.

According to an embodiment of the present invention, the gas inlets 43 may have a size of about 0.2 to 2 mm, and the length of the protrusions 42 may be about 1 to 10 mm. The shower plate may be made of aluminum with an anodized surface. Further information regarding a shower plate that can be used in one embodiment of the present invention is disclosed in US patent application Ser. No. 11 / 061,986 filed Feb. 18, 2005 by ASM Japan KK, one of the applicants of the present invention. .

The spacing between the upper and lower electrodes (in this embodiment, the shower plate 21 and the upper plate 70) is denoted as d, and the diameter of the wafer 30 is denoted as Dw. In one embodiment, the diameter Ds of the region having the protrusions 42 of the shower plate 21 may satisfy the inequality Dw-d <Ds <Dw + 3d. When Ds is within the above range, the film uniformity can be improved. Also, in one embodiment, the diameter Dh of the region with multiple gas inlets 43 may satisfy the inequality Ds-2d <Dh. In other embodiments, Dw may be approximately equal to Dh. In the above, d may be about 3 to 50 mm (preferably 10 to 25 mm).

It is very important to provide a gap between the mask and the top surface of the wafer to prevent the formation of a film on the top and side edges of the wafer, the gap being within a certain range to avoid direct contact and abnormal discharge. It is required to be in. The distance between the bottom surface of the upper mask member 61 (see FIG. 8) of the bevel mask 60 and the wafer support surface of the upper plate 70 is a distance β from the thickness Tw of the wafer 30. It is substantially the same as adding. Here, β denotes a distance between the upper mask member 61 of the mask and the upper surface of the wafer 30, and is larger than 0 (preferably 0.05 to 0.75 mm). The side mask member 62 (refer to FIG. 8) of the mask 60 has an inner diameter Db, and the inner diameter Db is substantially equal to the diameter Dw of the wafer 30 plus 2α. Here, α denotes a distance between the side portion of the wafer and the side mask member 62 of the mask 60 and is larger than 0 (preferably 0.05 to 2 mm).

In addition, in the present embodiment, the inner edge 64 of the upper mask member 61 of the mask 60 may have a thickness of 2 mm or less (eg, 0.5 to 1 mm). The upper mask member 61 may also have a portion 63 inclined inward. The inclined portion 63 may have a length sufficient to cover the edge of the wafer 30. Due to the inclined portion 63, the effective electrode distance may gradually increase toward the edge of the wafer 30. Accordingly, plasma concentration may be reduced at the edge portion of the wafer 30.

In one embodiment of the present invention, when an oriental flat wafer is used instead of a circular silicon wafer, a bevel mask having an inner edge corresponding to the outer edge shape of the oriental flat wafer is used, so that the bevel mask is formed of the wafer. The entire outer edge of the wafer may be covered by about 0.5 to 2.5 mm from the edge. This change can also be applied to the area in which the protrusions are arranged in the shower plate. That is, a shower plate having a shape corresponding to the outer edge shape of the oriental flat wafer may be used. In one embodiment, when the distance from the center of the wafer to the outer edge portion is Rw, the area where the protrusions of the shower plate are disposed may be an inner area from the center to Rw + T. Here, T may preferably be defined within the range of about −d / 2 <T <3d / 2 (eg 0 <T <d).

In one embodiment of the invention, in the notched wafer, markings of about 1 to 1.5 mm are formed from the edge of the wafer toward the center. In this case, deposition of the film in the vicinity of the notched region can be prevented by forming an inner structure to cover the notched region longer by about 1.3 to 2.0 mm in part to completely cover the notched region.

8 is a partial cross-sectional view of an embodiment of the present invention exaggerated for the purpose of detailed description. In this embodiment, the top plate 71 on which the wafer 30 is located includes an inner portion 73 and an edge portion 80 (ring structure). The inner portion 73 is made of a conductive material, and the edge portion 80 is made of a dielectric material. The embodiment described in US Patent Publication No. 2003-0192478 (filed by ASM Japan K.K., one of the applicants of this application) is available. The edge region 80 has a ring-shaped structure and has an inner diameter of about 80 to 120% of the diameter of the wafer 30.

In addition, as an example, when considering near the inner edge of the mask 60 in which plasma concentration occurs, a ring-shaped recess or trench having an inner diameter of about 80 to 100% of the diameter of the wafer 30 is formed. The top plate 71 in which 82 is formed can be used. By placing the trench, a space of about 0.2 to 1.5 mm (preferably about 0.5 to 1.0 mm) is created below the wafer 30. When the ring structure 80 is disposed at the edge portion of the upper plate 70 ', a dielectric material such as ceramic constituting the ring structure 80 is inserted, and an annular edge recess having a depth of about 0.5 to 10 mm. 72 may be generated. Further, in this embodiment, the wafer 30 is in contact with the upper edge portion 81 of the ring structure 80 and the upper surface of the inner portion 73 of the trench 82 or the upper plate 71. Not in contact with Thus, plasma concentration can be reduced near the inner edge of the mask 60, and film thickness uniformity can be realized. Preferably, the mask 60 is located on the ring structure 80 and the trench 82 is located slightly inward at the inner edge 64 of the mask 60. Accordingly, plasma concentration can be reduced near the edge of the wafer 30.

According to one embodiment of the invention, even when no ring structure is used, a trench may be formed in the top plate itself to adjust the effective distance between the upper and lower electrodes.

According to one embodiment of the invention, the ring structure 80 may be made of a dielectric material such as ceramic. Materials or properties that can be used as the mask can also be used for the ring structure. The dielectric ring structure can be effectively located near the inner and outer edges of the mask where the plasma is concentrated. The inner portion 73 of the top plate 71 or 70 may be made of, for example, aluminum with anodized surface or surface treated aluminum or aluminum alloy.

As an alternative to the ring structure 80 provided with the trench 82, a ring structure 90 provided without a trench may be used, as shown in FIG. 11. The heater is not shown here. In FIG. 11, the ring structure 90 is fitted to the outer edge of the top plate 74 and is fitted to the height of the inner portion 75 of the top plate 74. The mask 60 is located on the upper edge surface of the ring structure 90. The ring structure 90 may be made of the same material as the ring structure 80, the configuration of the ring structure 90 may be different from the ring structure 80 except that the trench is not formed It may be the same. For example, the thickness of the ring structure 90 may be formed thinner (eg, about 1/3 to 1/2) than the ring structure 80 because the trench is not formed. For example, the thickness of the ring structure 90 may be in the range of about 1 to 5 cm (preferably about 1.5 to 3 cm). The inner diameter of the ring structure 90 may be larger than the wafer.

According to an embodiment of the present invention, the ring structure 90 may not be adjusted to the height of the inner portion 75 of the upper plate 74, rather than the inner portion 75 (see A3 of FIG. 13). It can have a high upper edge surface. In A3 of FIG. 13, the wafer 30 is surrounded by a ring structure 90 ″ and the top plate 74 may be made of a ceramic such as aluminum oxide (AlN).

According to an embodiment of the present invention, an inner diameter of the ring structure may be smaller than the wafer, and the wafer may contact the ring structure 90 without contacting the inner portion 75 of the upper plate 74. It may be. According to another embodiment, the upper edge portion of the ring structure 90 may be located lower than the inner portion 75. By using the ring structure 90 in combination with the mask 60 and the shower plate 21, the effective electrode distance can be adjusted near the edge of the wafer.

According to one embodiment of the invention, the lower electrode can be constituted by a heater 2 and an upper plate 3 which are integrally provided instead of separately provided parts, as shown in FIG. 2. For example, the integrated lower electrode may be made of aluminum or aluminum alloy, which is oxidized or surface treated, and its use temperature may be about 150 to 450 ° C. The integrated lower electrode may be made of surface-treated aluminum nitride having a use temperature of about 150 to 650 ° C. In addition, the heater may be built in the upper plate.

Further, according to one embodiment of the present invention, plasma concentration can be reduced by passing gas through holes or gaps formed in the lower electrode from the edge surface of the inner portion of the mask toward the wafer. This makes it possible to control abnormal growth of the film thickness on the silicon wafer. In addition, when the mask is not positioned on the upper edge surface of the top plate and is suspended, the gap between the mask and the top plate can be used as a gas passage for the above purpose. In one embodiment, when the mask is located on the upper edge surface of the upper plate and the upper edge surface is provided with through-holes near the outer edge of the wafer, the gas is It may pass through the gap between the through holes and the mask and the wafer.

With respect to the gas being passed, the gas may be a source gas used for film formation. In another embodiment, the gas being passed is hydrocarbon (CxHy; where x and y are integers of at least 1; preferably x is at least 5) and an inert gas (e.g., N ₂ , Ar, He, etc. Can be selected from. The flow rate of the gas may be about 10 to 3000sccm, preferably about 20 to 1000sccm.

2 is a schematic view showing an embodiment of the present invention, which is exaggerated for the purpose of explanation. The plasma CVD film forming apparatus 1 includes a reaction chamber 6, a gas introduction section 5, an upper electrode 9, and a lower electrode including a heater 2 and an upper plate 3. Gas is provided from the gas line (not shown) through the gas inlet 5. The circular upper electrode 9 is arranged below the gas introduction section 5. The upper electrode 9 has a hollow structure and has a plurality of fine holes (gas inlets) for injecting the gas toward the wafer. In addition, the upper electrode 9 has a structure in which a shower plate 21 having a plurality of gas inlets can be replaced in order to facilitate maintenance and reduce component costs.

In addition, an exhaust 10 is provided under the reaction chamber 6. The drain base 10 is connected with an external vacuum pump (not shown) to evacuate the interior of the reaction chamber 6. The upper plate 3 is disposed substantially parallel to the upper electrode. The upper plate 3 supports the wafer 4, heats the wafer 4 by the heater 4, and maintains the wafer at a set temperature (eg, -50 to 650 ° C.). The edge portion 24 (ring structure) of the upper plate 3 may be made of alumina. In addition, a mask 22 is provided near the wafer 4. When the top plate 3 is moved downward by a vertical drive mechanism (not shown), the mask 22 is positioned on the mask support stand 23. When the top plate 3 is moved upwards, the mask 22 is located on the edge portion 24 of the top plate 3. The gas introduction section 5 and the upper electrode 9 are electrically insulated from the reaction chamber 6 and are connected to an external first RF power source 7. The second RF power source 8 is also connected. Here, reference numeral 12 denotes ground. Thus, the upper electrode 9 and the lower electrode function as RF electrodes and create a plasma reaction region near the wafer 4. The shape and characteristics of the film formed on the wafer 4 can be changed by the flow rate, temperature, RF frequency, plasma spatial distribution, dislocation distribution, etc. of the source gas.

As an embodiment of the present invention, a plurality of protrusions may be disposed on the shower plate 21. The protrusions may be disposed around the fine holes for introducing gas, and may have polygonal pillars or polygonal pyramidal shapes such as hexagonal pillars and square pyramids. In addition, the shape of the protrusions is not limited to hexagonal columns and square pyramids, any shape may be used. For example, a cylinder shape or an ellipse shape may be used. In addition, fine protrusions are not applied, and a bank shape having a predetermined width may be used. When the bank shape is used, the protrusion may have a parallel line shape in which a plurality of straight lines are arranged in parallel, and a lattice shape or a round shape in which a plurality of straight lines cross each other may be used. Also in this case, the protrusions in the form of banks are arranged around the fine holes for introducing gas. In view of the fact that the protrusions are formed by machining, a protrusion having a hexagonal pillar or a square pyramid shape is preferable.

Example

Embodiments of the present invention will be described in more detail below. However, these examples are not intended to limit the scope of the present invention. Facility conditions and process conditions are as follows.

Facility condition (wafer size: Φ200 mm)

Mask Material: Alumina, Silicone

Top plate: aluminum with anodized surface

Top plate edge area (alumina): Flat type (inner diameter: Φ203mm larger than wafer, thickness: 2mm, Fig. 11), trench type (inner diameter: Φ180mm smaller than wafer, thickness: 4mm, trench length: 6mm, depth: 1mm, degree 8)

Gap between mask and top surface of wafer: 0.075mm, 0.325mm, 0.575mm, 0.775mm

1 mm gap between mask and wafer side

Shower Plate: Aluminum with Anodized Surface

Shower Plate Size: Φ250mm

Shower Plate Type: Hexagon Pillar Protrusion

Protrusion area: Φ200mm, Φ220mm, Φ250mm (gas inlet area: Φ200mm, Φ220mm, Φ205mm)

Shower plate temperature: 180 ℃

Top plate temperature: 430 ℃

Electrode distance: 16mm

Cover range: 1.5mm

Process conditions

1,3,5-trimethylbenzee (TMB): 130 sccm

He: 200sccm

RF power: 13.56 MHz; 550 W, 430 kHz; 150 W

Pressure: 800Pa

Target film thickness: 200nm

Example 1 (Mask Material: Alumina, Silicon)

Protrusion area: Φ250mm (Gas inlet area: Φ205mm)

Upper plate outer edge (alumina): flat type

Gap between mask and top surface of wafer: 0.075mm

Film thickness profiles are shown in FIG. 3. Compared to the silicon mask, the film thickness of the alumina mask is increased sharply near the outermost edge area by about 15% compared to the central area.

Example 2 (upper plate outer edge (alumina): flat type, trench type)

Mask Material: Alumina

Protrusion area: Φ250mm (Gas inlet area: Φ205mm)

Gap between mask and top surface of wafer: 0.075mm

Film thickness profiles are shown in FIG. 4. Compared to the flat type, in the trench type, the thickness of the film at the outer edge is about 25 to 15%. This means the result of an increase in the effective electrode distance caused by positioning the wafer on the dielectric material and providing a gap at the outer edge of the wafer.

Example 3 (gap between mask and wafer top surface: 0.075 mm, 0.325 mm, 0.575 mm, 0.775 mm)

Protrusion area: Φ250mm (Gas inlet area: Φ205mm)

Mask Material: Alumina

Upper plate outer edge (alumina): trench type

Film thickness profiles are shown in FIG. 5. When the gap between the mask and the wafer was changed from 0.075 mm to 0.575 mm, no film formation was observed on the side portions and the top edge portions of the wafer. However, abnormal discharge occurred intermittently at an interval of 0.075 mm, which is judged to be not satisfactory film formation.

Example 4 (protrusion region: Φ 200 mm, Φ 220 mm, Φ 250 mm)

Mask Material: Alumina

Upper plate outer edge (alumina): trench type

Gap between mask and top surface of wafer: 0.075mm

Film thickness profiles are shown in FIG. 6. In the case of Φ250mm (Ds = Dw + 3.125d), the film thickness difference between the center part and the edge part was about + 12%, and for Φ220mm (Ds = Dw + 1.25d), the part between the center part and the edge part The difference in film thickness was about -5%, and in the case of Φ 200 mm (Ds = Dw), the difference in film thickness between the center part and the edge part was about -7%. Thus, the film thickness distribution can be controlled by controlling the protrusion region of the shower plate, and the film thickness was satisfactorily around Φ 220 mm.

Example 5

Additionally, under the same conditions as in Example 4, the diameters Ds of the protrusion regions were set to Dw, Dw + d, Dw + 2d and Dw + 3d, and the film thickness distributions were measured. The results are shown in FIG. The ratio of edge thickness to center thickness is proportional to Ds. When Ds was Dw + 2d, it was determined that there was little difference in film thickness between the center portion and the edge portion. In order to prevent the film from becoming thicker at the edge portion, Ds is preferably set between Dw and Dw + 2d. However, even when Ds was set to Dw + 3d, the film thickness difference was as low as about 10%.

Example 6 (protrusion region: Φ 200 mm, Φ 220 mm, Φ 250 mm)

Mask Material: Alumina

Top plate outer edge (aluminum): flat type

Gap between mask and top surface of wafer: 0.075mm

Film thickness profiles are shown in FIG. 12. In the case of Φ250mm (Ds = Dw + 3.125d), the film thickness difference between the center part and the edge part was measured by + 15%, and in the case of Φ220mm (Ds = Dw + 1.25d), the film between the center part and the edge part The thickness difference was measured at + 5%, and for Φ 200 mm (Ds = Dw), the film thickness difference between the center and the edge was measured at -15%. Therefore, the film thickness distribution can be controlled by controlling the protrusion region of the shower plate, and the film thickness was measured to a degree satisfactory near Φ 220 mm.

Although the present invention has been described in terms of preferred embodiments, other embodiments apparent to those skilled in the art may also be within the scope of the present invention. Accordingly, the scope of the invention may be limited only by the claims that follow. The invention includes various embodiments and will not be limited by the above preferred embodiments.

The present invention includes the following examples.

1) A plasma CVD film forming apparatus for forming a thin film on a wafer, wherein the apparatus functions as a vacuum chamber, a shower plate which functions as an upper electrode and is installed in the vacuum chamber, and functions as a lower electrode and opposes the shower plate. An upper plate disposed to be substantially parallel to position the wafer thereon, a vertical drive mechanism for moving the upper plate on which the wafer is placed in the vertical direction, a wafer positioned on the upper plate and the upper plate upwards A mask for preventing the formation of a film on the top edge and side portions of the wafer by covering the top edge and side portions of the wafer when moved to and between the mask and the top surface of the wafer. Spacing of 0.05 to 0 It may be specified that the point about .7mm and the distance between the mask and the side surface of the wafer is about 0.05 to 2mm.

2) In the above item 1), the plasma CVD film forming apparatus is characterized in that the surface portion of the shower plate is formed with a plurality of gas inlets and a plurality of protrusions protruding from the surface, the upper electrode and the lower When the distance between the electrodes is called 'd' and the diameter of the wafer is called 'Dw', the diameter Ds of the region having plasma enhanced spikes of about 1 to 10 mm is inequality Dw-d <Ds <Dw + It can be specified that a shower plate is used which satisfies 3d and whose diameter Dh of the region with a plurality of gas inlets having a diameter of about 0.2 to 2 mm satisfies the inequality Ds-2d &lt; Dh.

3) In the above item 1), the plasma CVD film forming apparatus has a spacing near the electrode called 'd', a wafer diameter called 'Dw', and Ds in a range of Dw-d &lt; Ds &lt; Dw + 3d. Is at, the shower plate has a region of flat diameter 'Ds' with an outer edge having the shape of a configuration that increases the distance from the lower electrode to about 2 to 10 mm, the diameter of the region with gas inlets. Dh 'may be specified as a point within the range Ds-2d <Dh.

4) In the above items 2) and 3), the plasma CVD film forming apparatus can be specified in that the outer edge portion outside the plane having the protrusions or the increased plane of the diameter 'Ds' is covered by the dielectric material. have.

5) In the above items 1) to 4), the apparatus for forming a plasma CVD film, wherein the mask has a thickness of about 2 mm or less at the innermost edge, and at least one inclined portion has the innermost edge and the outermost edge of the mask. It can be specified in that it is formed between the outer edges.

6) In items 1) to 5), the plasma CVD film forming apparatus can be specified in that the mask covers the top surface of the wafer in a range of about 0.3 to 3 mm from the outermost edge of the wafer. have.

7) In the above items 1) to 6), the plasma CVD film forming apparatus, wherein the mask is made of aluminum, aluminum oxide, aluminum nitride, silicon, silicon oxide, silicon carbide, silicon nitride, boron nitride and metal implanted ceramics It may be specified in that it may consist of at least one selected from the group.

8) In the above items 1) to 7), the plasma CVD film forming apparatus may be characterized in that the lower electrode is substantially made of aluminum nitride (AlN) and the use temperature is about 150 to 650 ° C.

9) In the above items 1) to 7), the plasma CVD film forming apparatus may be specified in that the lower electrode is substantially made of aluminum and the use temperature is about 150 to 450 ° C.

10) In the above items 2) to 9), the plasma CVD film forming apparatus may be specified by an area having protrusions or an increased area. Here, when the distance from the center of the wafer to the outer edge is referred to as 'Rw', in the distance 'Rw + To' from the center of the increased area to its outer edge, 'To' is -d / 2 to 3d / It may be about 2, and at a distance 'Rw + Th' from the center of the region having a plurality of gas inlets to its outer edge, 'Th' is greater than -d.

11) In the above items 1) to 10), the plasma CVD film forming apparatus includes a top plate for supporting a wafer including an inner portion and an edge portion, wherein the inner portion is made of a conductive material and the outer portion is It may be specified in that it is made of a dielectric material.

12) In the above items 1) to 11), the plasma CVD film forming apparatus can be specified in that the trench is formed in a part of the lower electrode on which the wafer is placed.

13) In the above items 1) to 11), the plasma CVD film forming apparatus can be specified in that the trench is formed in a part of a ring-shaped structure located at the edge of the upper plate on which the wafer is placed.

14) In the above items 1) to 11), the plasma CVD film forming apparatus is characterized in that the edge portion is a ring-shaped structure, and the inner diameter of the ring-shaped structure is about 80 to 120% of the wafer diameter. Can be.

15) In the item 14), the plasma CVD film forming apparatus, wherein the inner diameter of the ring-shaped structure is about 80 to 100% of the wafer diameter, the trench is formed in a portion of the ring-shaped structure on which the wafer is placed It can be specified in that respect.

16) In the above items 1) to 15), the plasma CVD film forming apparatus can be specified in that a gas flows through the inside of the lower electrode from the inner edge surface of the mask toward the wafer surface.

17) In the above items 1) to 16), the plasma CVD film forming apparatus can be specified in that the volume resistivity of the mask is about 10 ⁶ Pa · cm or more.

18) In the above items 1) to 16), the plasma CVD film forming apparatus may be specified in that the volume resistivity of the mask is about 10 ⁻⁵ to 10 ⁶ Pa · cm.

The plasma CVD film forming apparatus according to the embodiments of the present invention as described above can reduce the plasma concentration at the edge portion of the wafer, thereby preventing abnormal film thickness growth near the edge of the wafer.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (42)

In the plasma chemical vapor deposition apparatus for forming a thin film on a wafer having a diameter of Dw and a thickness of Tw, A vacuum chamber; A shower plate functioning as one of two electrodes and installed in the vacuum chamber; An upper plate that functions as another electrode, is movable between an upper position and a lower position, and is disposed to be substantially parallel to the shower plate to position the wafer thereon; An upper mask member disposed at an interval of Tw + β from the wafer support surface of the upper plate to cover the edge portion of the upper surface of the wafer, wherein β is greater than 0, and the gap Tw + β is Means a gap between the wafer support surface of the upper plate and the bottom surface of the upper mask member); And When the upper mask member is located in the upper position, it is disposed below the upper mask member to cover the side portion of the wafer, and has a side mask member having an inner diameter of Dw + α (where α is greater than zero). Plasma chemical vapor deposition apparatus comprising a. The apparatus of claim 1, wherein α is 0.05 to 2 mm and β is 0.05 to 0.75 mm. The plasma chemical vapor deposition apparatus according to claim 1, wherein the shower plate comprises a gas discharge member and a base member, and the gas discharge member has a diameter Ds satisfying the following equation (1). Dw-d <Ds <Dw + 3d ---- (1) (Wherein d means the distance between the shower plate and the top plate) The plasma chemical vapor deposition apparatus according to claim 3, wherein the diameter Ds satisfies Equation 2 below. Dw <Ds <Dw + 2d ---- (2) 4. The gas discharge member of claim 3, wherein the gas discharge member comprises a plurality of gas inlets and plasma enhanced spikes protruding downward from a surface on which the plurality of gas inlets are formed, wherein Ds is the outermost spike among the plasma enhanced spikes. A plasma chemical vapor deposition apparatus, characterized in that the outer diameter of the region defined by them. 6. The plasma chemical vapor deposition apparatus according to claim 5, wherein the region defined by the outermost inlets among the plurality of gas inlets has a diameter Dh satisfying Equation (3) below. Ds-2d <Dh ---- (3) The apparatus of claim 5, wherein the inlets have a diameter of 0.2 mm to 2 mm, and the spikes have a length of 1 mm to 10 mm. 4. The apparatus of claim 3, wherein the upper mask member has a bulk resistivity of at least 10 ⁶ Pa · cm. The apparatus of claim 1, wherein the upper mask member has a volume resistance of 10 ⁻⁵ to 10 ³ Pa · cm. The apparatus of claim 1, wherein the upper mask member and the side mask member are integrally provided and constitute a bevel mask. The top plate of claim 1, wherein the top plate is conductive, an outer annular recess is formed around an edge of the top plate, and the wafer is supported on a dielectric ring structure positioned on the annular recess. Plasma chemical vapor deposition apparatus. 12. The apparatus of claim 11, wherein the side mask member is in contact with the upper edge surface of the dielectric ring structure. 12. The apparatus of claim 11, wherein the side mask member is configured in whole or in part by the dielectric ring structure. 12. The apparatus of claim 11, wherein the dielectric ring structure has an inner annular recess. 12. The apparatus of claim 11, wherein the plane formed by the top edge surface of the dielectric ring structure is positioned higher than the plane formed by the top surface of the top plate. 12. The apparatus of claim 11, wherein the dielectric ring structure has an inner diameter of 0.8Dw to 1.2Dw. The apparatus of claim 1, wherein the upper mask member has a thickness of 2 mm or less at an inner edge portion and a tapered portion inwardly. The apparatus of claim 1, wherein the upper mask member covers an upper surface of the wafer in a range of 0.3 to 3 mm from an outermost edge of the wafer. The method of claim 1, wherein the upper mask member is made of at least one selected from the group consisting of aluminum, aluminum oxide, aluminum nitride, silicon, silicon oxide, silicon carbide, silicon nitride, boron nitride, and metal impregnated ceramic. A plasma chemical vapor deposition apparatus. The plasma chemical vapor deposition apparatus according to claim 1, wherein the upper plate has an outer diameter (Dss) satisfying Equation (4) below. 1.04Dw <Dss <1.5Dw ---- (4) The apparatus of claim 1, wherein the side mask member contacts the top edge surface of the top plate at the top position. Positioning the wafer on a top plate installed substantially parallel to the shower plate; An upper mask member covers the upper edge portion of the wafer at a distance β greater than zero, and a side mask member is disposed at the edge of the upper plate to cover the side portions of the wafer at an interval α greater than zero. Positioning the upper mask member over the wafer to make it; And Applying a radio-frequency (RF) power between the top plate and the shower plate to form a thin film on the wafer using plasma chemical vapor deposition. How to form. 23. The film forming method according to claim 22, wherein the interval β is 0.05 to 0.75 mm, and the interval α is 0.05 to 2 mm. 23. The diameter Ds of claim 22, further comprising providing the shower plate, wherein the shower plate comprises a gas discharge member and a base member, the gas discharge member satisfying the following equation (5): A film forming method comprising: Dw-d <Ds <Dw + 3d ---- (5) (Wherein, Dw means the diameter of the wafer, d is the distance between the shower plate and the top plate) 25. The method of claim 24, wherein Ds satisfies Equation (6) below. Dw <Ds <Dw + 2d ---- (6) 25. The apparatus of claim 24, wherein the gas discharge member comprises a plurality of gas inlets and plasma enhanced spikes protruding downward from a surface on which the plurality of gas inlets are formed, wherein Ds is the outermost spike among the plasma enhanced spikes. It is an outer diameter of the area | region defined by these, The film formation method characterized by the above-mentioned. 27. The method of claim 26, wherein the region defined by the outermost inlets of the plurality of gas inlets has a diameter Dh that satisfies Equation (7) below. Ds-2d <Dh ---- (7) 27. The method of claim 26, wherein the inlets have a diameter of 0.2 mm to 2 mm and the spikes have a length of 1 mm to 10 mm. 25. The method of claim 24, wherein the upper mask member has a volume resistivity of at least 10 ⁶ Pa · cm. 23. The method of claim 22, further comprising providing the upper mask member, wherein the upper mask member has a volume resistance of 10 ^-5 to 10 ³ Pa · cm. 23. The method of claim 22, further comprising providing the top plate, wherein the top plate is conductive, an outer annular recess is formed around an edge of the top plate, and the wafer is formed on the annular recess. And is supported on a dielectric ring structure positioned at the substrate. 32. The method of claim 31 wherein the side mask member is in contact with the upper edge surface of the dielectric ring structure. 32. The method of claim 31 wherein the dielectric ring structure has an inner annular recess. 32. The method of claim 31 wherein the wafer is in contact with the top edge surface of the dielectric ring structure. 32. The method of claim 31 wherein the dielectric ring structure has an inner diameter of 0.8 to 1.2 times the wafer diameter (Dw). 23. The method of claim 22, further comprising providing the upper mask member, wherein the upper mask member has a thickness of 2 mm or less at an inner edge portion and has an inclined portion inwardly. 23. The method of claim 22, further comprising providing the upper mask member, wherein the upper mask member is provided integrally with the side mask member and constitutes a bevel mask. 23. The method of claim 22, wherein an upper surface of the wafer is covered by the upper mask member in a range of 0.3 to 3 mm from the outermost edge of the wafer. 23. The method of claim 22, further comprising providing the upper mask member, wherein the upper mask member is formed of aluminum, aluminum oxide, aluminum nitride, silicon, silicon oxide, silicon carbide, silicon nitride, boron nitride, and metal implanted ceramics. A film forming method comprising at least one selected from the group consisting of. 23. The method of claim 22, further comprising providing the top plate, wherein the top plate has an outer diameter (Dss) that satisfies Equation (8) with respect to the diameter (Dw) of the wafer. Film formation method. 1.04Dw <Dss <1.5Dw ---- (8) 23. The method of claim 22 wherein the side mask member is in contact with the top edge surface of the top plate. 23. The method of claim 22, wherein the film formed on the wafer has a film thickness nonuniformity of 10% or less.

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