KR20070008077A - Method and system for arranging access controller or direct memory having circular multiple processor structure - Google Patents

Abstract

A method and a system for arranging a DMAC(Direct Memory Access Controller) in a structure having ring type multiple processors are provided to increase an entire processing rate by reducing a data transfer time between the processors and quickly outputting data to the outside. A reception DMAC(311) is connected to the first processor in a data transfer direction based on a bridge(350) used as a connection path between a single ring and the outside. A transmission DMAC(314) is connected to the last processor in the data transfer direction based on the bridge. The DMACs include a DSP(Digital Signal Processor)(341-344) capable of processing the transmitted and received data.

Description

METHOD AND SYSTEM FOR ARRANGING ACCESS CONTROLLER OR DIRECT MEMORY HAVING CIRCULAR MULTIPLE PROCESSOR STRUCTURE}

1 is a layout diagram of a reception DMAC and a transmission DMAC embedded in an SB3000 chip, which is generally configured as a one-chip;

2 is a diagram illustrating positions of a receiving DMAC and a transmitting DMAC according to the first embodiment of the present invention;

3 is a diagram illustrating positions of a reception DMAC and a transmission DMAC embedded in an MPSoC according to a second embodiment of the present invention.

The present invention relates to a method and system for arranging a direct memory access controller, and more particularly, to a method and system for arranging a direct memory access controller in a structure having an annular multiprocessor in a structure having an annular multiprocessor.

In general, controller systems for accessing a memory have various forms, and processors are configured using a digital signal processor (hereinafter, referred to as a "DSP") to process high-speed data. As a representative method of the types of controller systems for accessing the memory as described above, there is a method having a circular multiprocessor. As described above, various chips have been developed and used in the direct memory access controller (DMAC), which is effective for processing transmission / reception and broadcast reception signals in a multi-processor system connected in a ring between processors. Next, a chip having a direct memory access controller in an annularly connected multiprocessor system will be described.

1 is a layout diagram of a reception DMAC and a transmission DMAC embedded in an SB3000 chip, which is generally configured as a one-chip. The SB3000 chip shown in FIG. 1 is Sandbridge Tech, a company that develops a multi-processor system on chip (MPSoC) used for software-defined radio (SDR). /www.sandbridgetech.com) shows the locations of the receiving and transmitting DMACs embedded in the SB3000 chip of the company. The four DSPs embedded in the chip are DSP # 1 141, DSP # 2 142, DSP # 3 143, and DSP # 4 144, respectively, reference numerals 190, 191, 192, and 193, which are data transmission paths. It is connected in a ring-type structure that is transmitted uni-directionally according to 194. Each of the DSPs 141 to 144 includes instruction caches (I $) 161, 162, 163, and 164, and data caches (D $: 172, 172, 173, and 174). And L2 memories 181, 182, 183, and 184, and external interfaces (Ext. I / F) 151, 152, 153, and 154 for data transmission and reception with an external device. The multiple DSP blocks 141, 142, 143, and 144 connected in an annular structure are connected to another processor, a central processing unit (CPU: ARM926EJ-S) 130, through a bridge 150. The CPU 130 used in the SB3000 is ARM926EJ-S manufactured by ARM (Advanced RISC Machines).

As shown in FIG. 1, the DSP # 1 141, the DSP # 2 142, the DSP # 3 143, and the DSP # 4 144 sequentially rotate clockwise with respect to the bridge 150. Are arranged according to the data transmission direction of the annular data path. In addition, the SB3000 receives A / D data, which is an output of an analog-to-digital converter (ADC), through a receive I / O (Rx I / O) 121. The Rx Direct Memory Access Controller (Rx DMAC) 111 transmits the A / D data to the DSP # 1 141. Meanwhile, the SB3000 chip outputs D / A-converted data, which is an output of a digital-to-analog converter (DAC), through a transmission I / O (Tx I / O) 122. The D / A-converted data causes the Tx Direct Memory Access Controller (Tx DMAC) 112 to be retrieved from DSP # 2 142.

In general, a communication terminal performs processing of a transmission signal as well as a reception signal processing. In general, the reception terminal processing is more complicated and has a larger amount of calculation than processing of a transmission signal. That is, over 50% of the total required calculation amount is received signal processing. For example, the amount of computation that each of the DSPs 141, 142, 143, and 144 can process is referred to as 600 Million Instructions Per Second (MIPS), and a total of four DSPs 141, 142, 143, and 144 are processed. Suppose we can handle this 2400 MIPS of computation. In this case, when the amount of computation for processing the received signal occupies 70% of the total, and the amount of computation for the transmission signal processing occupies 30% of the total, the computations for receiving and transmitting become 1680 MIPS and 720 MIPS, respectively. . Since this amount of computation exceeds 600 MIPS, which can be processed by one DSP, it must be distributed and processed among several DSPs. Therefore, processing of a received signal requiring 1680 MIPS processes 1200 MIPS in two DSP blocks and 480 MIPS in another DSP block. In the processing of the transmission signal, 120 MIPS is processed in the DSP which processes only the 480 MIPS, and 600 MIPS is processed in the other DSP. Thus, a DSP that processes 480 MIPS for transmit processing and 120 MIPS for receive processing handles a total of 720 MIPS.

When data moves from one DSP to a clockwise adjacent DSP along the annular data transmission path as shown in FIG. 1, it takes unit time expressed as the number of cycles. The number of cycles actually taken may vary depending on which memory area in the DSP moves from one memory area to another. For simplicity, one cycle is required to move data along the data paths 190, 191, 192, 193, 194.

Then, it can be said that it takes 1 cycle to transfer data from DSP # 1 141 to DSP # 2 142 and 2 cycles to transfer data from DSP # 1 141 to DSP # 3 143. . In addition, it takes four cycles to move data from DSP # 2 142 to DSP # 1 141. Because, the total time required for the bridge 150 to exist in the middle of the path takes 4 cycles. As described above, when the amount of computation for transmitting / receiving signal processing is distributed for each DSP, the DSs that perform the transmission signal processing and the DSPs that perform the reception signal processing need to be located as close as possible because there is a lot of data. In this way, the number of cycles required for data movement can be minimized, and data can be prevented from moving unnecessarily along the annular data path, thereby increasing throughput of the annular data path. Therefore, under this condition, as an example of allocating one DSP for the transmission / reception signal processing, DSP # 1 141 which receives A / D data performs 600 MIPS processing, and DSP # 3 143 is 600 MIPS. Process. In addition, DSP # 4 144 processes 480 MIPS for reception, DSP # 2 142 for exporting D / A data performs 600 MIPS processing, and DSP # 4 144 processes 120 MIPS for transmission data. Using this method, the transmission signal and the reception signal can be processed at once.

However, when configured as shown in FIG. 1, since DSP # 2 142 for processing a transmission signal exists between DSPs for processing a received signal, DSPs for processing a received signal may not be adjacent in a clockwise direction. Occurs. In other words, if the DSPs for processing the received signal are not adjacent to each other, the entire time is long. Therefore, the throughput of the multiprocessor is reduced.

Accordingly, an object of the present invention is to provide a method for arranging a direct memory access controller (Direct Memory Access Controller) (hereinafter referred to as "DMAC") in an annularly connected multiprocessor system at an effective position for communication transmission and reception and broadcast reception signal processing. In providing a system.

Another object of the present invention is a processor group for processing a received signal and a transmit signal processing in a multiprocessor system which simultaneously performs processing of a received signal and a transmitted signal by arranging DMACs at appropriate positions in a multiprocessor system annularly connected between processors. To provide a method and system that can be minimized waste of unnecessary time or cycle due to data movement between processors adjacent to each other.

Another object of the present invention is to place DMAC in the proper position in the annularly connected multiprocessor system between the processors to minimize the need for the output of the processor performing the last signal processing in the multiprocessor system to travel unnecessarily through the annular data path. In addition, the present invention provides a method and system capable of minimizing the number of cycles or time required for the output to be transmitted to the outside through a bridge or the like.

A method of the present invention for achieving the above objects is a method of arranging a direct memory access controller in a multi-processor system connected by a single ring, wherein the receiving direct memory access controller is based on a bridge that is a connection path between the ring and the outside. The direct memory access controller for transmission is connected to the first processor in the direction of movement, and the last processor is connected to the last processor in the direction of data movement based on a bridge, which is a connection path between the ring and the outside.

A system of the present invention for achieving the above objects is a multi-processor system in which direct access controllers are connected in a single ring, and a receiving direct memory access controller is a data movement direction based on a bridge that is a connection path between the single ring and the outside. In this case, the direct memory access controller for transmission is connected to the last processor in the direction of data movement based on a bridge, which is a connection path between the ring and the outside, and the direct access controllers can process transmit and receive data. It includes a digital signal processor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, specific details appear in the following description, which is provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific matters. Will be self-evident. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a diagram illustrating positions of a receiving DMAC and a transmitting DMAC according to the first embodiment of the present invention. Hereinafter, FIG. 2 will be compared with FIG. 1 described in the related art. Before the comparison of FIGS. 1 and 2, it should be noted that the reference numeral 200 is used in FIG. 2 to facilitate the differentiation of the drawings even though the same parts as those of FIG. 1 are used. That is, for example, the bridge 150 of FIG. 1 is used the same in FIG. 2, but is illustrated as the bridge 250 to distinguish the drawings.

In FIG. 2, DSP # 2 242 for receiving A / D data and processing 600 MIPS and A / D data for 600 MIPS are processed by changing the positions of the reception DMAC and the transmission DMAC of FIG. DSP # 3 243 and DSP # 4 244 which process A / D data of 480 MIPS perform processing of the received signal. On the other hand, the DSP # 1 251 processing 600 MIPS D / A data and the DSP # 4 244 processing 120 MIPS D / A data perform transmission signal processing. In this case, there is a problem that it takes two cycles to move data from DSP # 4 244 to DSP # 1 241 because there is a bridge 250 between DSPs for the transmission signal processing. And DSPs for processing received signals are adjacent.

Unlike a communication terminal, a broadcast terminal generally performs only received signal processing. If the amount of computation that the broadcast terminal needs to process is 2100 MIPS, it is enough to process 600 MIPS for each of the three DSP blocks and 300 MIPS for the other DSP block. In this case, however, in the annular structure of FIG. 2, the DSP # 2 242, the DSP # 4 243, the DSP # 4 244, and the DSP # 1 241, which receive the A / D data, process the received signal. do. If you want to move the data processed by DSP # 1 241 in which the last processing is performed to the external memory through the bridge 250 through the CPU 230 or the Advanced High-speed Bus (AHB) I / O 232, The data may reach the bridge 250 only through the data movement paths 291, 292, 293, and 294.

Therefore, in the above-described first embodiment, since the data flowing into the annular data paths 290, 291, 292, 293, and 294 is increased, the overall throughput may be reduced by preventing the movement of other data.

Next, a second embodiment of the present invention will be described.

In the second embodiment of the present invention, the annularly connected multiprocessors are all limited to the same type of processor, but those skilled in the art to which the present invention pertains can easily use the annularly connected method using the method of the present invention. The same applies to different processors. In addition, although the embodiment of the present invention describes only a multi-processor system connected by a single ring in which data can move only in a clockwise direction, a person skilled in the art using the method of the present invention belongs to It can also be applied to multiprocessor systems connected by dual rings that easily move data clockwise and counterclockwise. In addition, the embodiment of the present invention will be described only for unidirectional DMAC, but those skilled in the art to which the present invention pertains may be easily applied to the bidirectional DMAC using the method of the present invention.

3 is a diagram illustrating positions of a reception DMAC and a transmission DMAC embedded in an MPSoC according to a second embodiment of the present invention. In FIG. 3, reference numerals are used to designate reference numerals 300 to distinguish the drawings.

As illustrated in FIG. 3, the four DSPs 341 to 344 built in the MPSoC are respectively DSP # 1 341, DSP # 2 342, DSP # 3 343, and DSP # 4 344. Are connected in a uni-directional ring structure according to reference numerals 390, 391, 392, 393 and 394. Each DSP block includes instruction caches (I $) (361, 362, 363, 364), data caches (D $: data caches) 371, 372, 373, 374, and L2 memories, respectively. 381, 382, 383, and 384, and external interfaces (Ext. I / F: External Interfaces) 351, 352, 353, and 354 for data transmission and reception with the outside. The multiple DSPs 341 to 344 connected in an annular structure are connected to another processor CPU 330 through a bridge 350. The DSP # 1 341, the DSP # 2 342, the DSP # 3 343, and the DSP # 4 344 sequentially rotate clockwise with respect to the bridge 350 according to the data transmission direction of the annular data path. It is arranged.

In addition, the MPSoC receives A / D data, which is an output of an analog-to-digital converter (ADC), through a receive I / O (Rx I / O) 321. The A / D data is transmitted to the DSP # 1 341 by a Rx Direct Memory Access Controller (Rx DMAC) 311. Meanwhile, the MPSoC outputs D / A data, which is an output of a digital-to-analog converter (DAC), through a transmission I / O (Tx I / O) 324. Therefore, the D / A data causes a Tx Direct Memory Access Controller (Tx DMAC) to be taken from DSP # 4 (344).

In this configuration, in the second embodiment of the present invention, in a multiprocessor system annularly connected between processors, the receiving DMAC is connected to the first processor based on the data progress direction of the annular structure, and the transmitting direct memory access controller is connected to the last processor. By connecting, when the user programs the communication system using the multiprocessor system, the processor group performing the reception signal processing and the processor group performing the transmission signal processing can be arranged adjacent to each other. Therefore, in the prior art, it is possible to minimize unnecessary waste of time or cycles due to data movement between salping processors. In addition, by minimizing the unnecessary output of the processor performing the signal processing through the annular data path, it is possible to minimize the time or the number of cycles required for the output to be transmitted to the outside through the bridge.

As described above, in the case of the annular multiprocessor structure according to the present invention, data transmission time between processors is reduced, and output is increased to the outside, thereby increasing the overall throughput.

Claims (7)

In a method of disposing a direct memory access controller in a multi-processor system connected by a single ring, The receiving direct memory access controller connects with the first processor in the direction of data movement based on the bridge, which is the link between the ring and the outside. The direct memory access controller for transmission is connected to the last processor in the direction of data movement based on a bridge, which is a connection path between the ring and the outside. The method of claim 1, And transmitting and receiving direct memory access controllers are unidirectional direct memory access controllers. The method of claim 1, And transmitting and receiving direct memory access controllers are bidirectional direct memory access controllers. In a multiprocessor system in which direct access controllers are connected in a single ring, The receiving direct memory access controller connects to the first processor in the direction of data movement based on the bridge, which is the linkage between the single ring and the outside, and the direct memory access controller for transmission is based on the bridge, which is the linkage between the ring and the outside. To the last processor in the direction of data movement, And said direct access controllers comprise a digital signal processor capable of processing transmission and reception data. In a method of disposing a direct memory access controller in a multi-processor system connected by a dual ring, Receiving direct memory access controller is connected to the first processor on the basis of the bridge that is the connection path between the double ring and the outside, The direct memory access controller for transmission is connected to the last processor on the basis of the bridge which is a connection path between the double ring and the outside. The method of claim 5, And transmitting and receiving direct memory access controllers are unidirectional direct memory access controllers. The method of claim 5, And transmitting and receiving direct memory access controllers are bidirectional direct memory access controllers.

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