KR20060062522A - Method for forming a contact hole to measure a critical demension of the contact hole in semiconductor device and method for measuring the critical demension of the contact hole using the same - Google Patents

Abstract

The present invention relates to a method of forming a contact hole for stably measuring the contact hole (CD) and openness of a semiconductor device and a method of measuring a contact hole CD using the same. To this end, the present invention comprises the steps of providing a semiconductor substrate formed with a lower conductive layer; Forming an interlayer insulating film on the entire structure including the lower conductive layer; Depositing a hard mask made of the same material as the lower conductive layer on the interlayer insulating layer; Etching the hard mask; Forming a contact hole through which the lower conductive layer is exposed by performing an etching process using the etched hard mask; Applying a sacrificial protective film over the entire structure including the contact hole; Removing the hard mask so that the sacrificial protective film applied inside the contact hole remains; And removing the sacrificial protective film remaining in the contact hole to expose the lower conductive layer.

Semiconductor element, contact hole, CD, hard mask, anti-reflection film, photoresist

Description

TECHNICAL FOR FORMING A CONTACT HOLE TO MEASURE A CRITICAL DEMENSION OF THE CONTACT HOLE IN SEMICONDUCTOR DEVICE AND METHOD FOR MEASURING THE CRITICAL DEMENSION OF THE CONTACT HOLE USING THE SAME}             

1A to 1C are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the prior art.

Figure 2 is a cross-sectional view showing a lower plug lost during the hard mask removal process in the prior art.

3A to 3D are cross-sectional views illustrating a method for forming contact holes in a semiconductor device according to a preferred embodiment of the present invention.

4 is a flowchart illustrating a CD measurement method of a contact hole bottom using a method of forming a contact hole in a semiconductor device according to an exemplary embodiment of the present invention shown in FIGS. 3A to 3D.

5 is a cross-sectional view showing a metal contact forming method according to a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10, 110: semiconductor substrate 11, 111: first interlayer insulating film

12, 112: lower plug 13, 113: second interlayer insulating film

14, 114: bit lines 15, 115: hard mask

16, 116: spacer 17, 117: third interlayer insulating film

18, 118: hard mask 19: photoresist pattern

20, 119: contact hole 120: sacrificial shield

The present invention relates to a method for forming a contact hole of a semiconductor device for measuring CD and a method for measuring a contact hole using the same, and more particularly, to a CD (Critical Demension) and an open of a bottom of a contact hole for a metal contact The present invention relates to a method for forming a contact hole in a semiconductor device for measuring CDs and a method for measuring contact holes using the same.

Due to the reduction of design rules due to the high integration of semiconductor devices, more precise process control is required in the manufacturing process of semiconductor devices. In particular, in the case of DRAM, the thickness of 0.115 μm or less may be used to connect a metal line and a bit line, between a conductive layer and a bit line on a substrate, or between an active region of a substrate and a capacitor electrode. There is a growing interest in the process of forming metal contacts.

In the DRAM contact forming process, a hard mask scheme is generally applied to secure an etching process margin. The hard mask scheme deposits an interlayer insulating film over an entire structure including bit lines formed thereon, and then deposits a hard mask thereon. Thereafter, an etching process using a photoresist pattern is performed to etch the hard mask, and then an etching process using the etched hard mask is performed. Through this etching process, the interlayer insulating film is patterned to form a contact hole for exposing the lower conductive layer.

Meanwhile, in the DRAM device, it is very important to determine the critical dimension of the bottom of the contact hole (hereinafter referred to as 'CD') and whether it is open after forming the contact hole for the metal contact. The reason is that the CD and the open state of the bottom of the contact hole directly affect the malfunction of the semiconductor device. Accordingly, in the related art, at least one wafer in which the contact hole forming process is completed is sampled and the CD and the opening of the contact hole bottom are measured by a scanning electron microscope (SEM).

Hereinafter, a method of measuring a CD and an open state of a bottom of a contact hole according to the prior art and a problem thereof will be described with reference to the metal contact forming method illustrated in FIGS. 1A to 1C.                         

As shown in FIG. 1A, the first interlayer insulating layer 11 is formed on the semiconductor substrate 10 and then etched to form a poly plug 12 therein. Next, a second interlayer insulating film 13 is formed over the entire structure including the poly plug 12. Then, after forming the bit line 14 and the hard mask 15 on the second interlayer insulating film 13, the spacers 16 are formed on both side walls of these (14, 15). Subsequently, a third interlayer insulating layer 17 is formed on the entire structure to cover the semiconductor structure layer including the spacers 16. Then, a hard mask 18 is deposited on the third interlayer insulating film 17 with a polysilicon film.

Subsequently, as shown in FIG. 1B, after forming the photoresist pattern 19 on the hard mask 18, an etching process using the photoresist pattern 19 as a food mask is performed to etch the hard mask 18. do. As a result, the hard mask pattern 18a is formed.

Subsequently, a strip process is performed as shown in FIG. 1C to remove the photoresist pattern 19. Then, an etching process using the hard mask pattern 18a as an etching mask is performed to sequentially etch the third interlayer insulating layer 17 and the second interlayer insulating layer 13. As a result, a contact hole 20 through which the poly plug 12 as the lower conductive layer is exposed is formed.

In the state in which the contact hole 20 is formed through the metal contact formation method as described above, the CD and the opening of the bottom of the contact hole 20 are measured using SEM. However, in this process, stable measurement is difficult because the secondary electrons emitted from the upper hard mask pattern 18a are overwhelmingly larger than the secondary electrons emitted from the poly conductive layer 12 as the lower conductive layer. Accordingly, it is almost impossible to check on the in-line whether the CD and the bottom of the contact hole 20 are open.

For this reason, after removing the hard mask pattern 18a, it is possible to measure the CD and the opening of the bottom of the contact hole 20 by using the SEM, in this case, as shown in 'A' shown in Figure 2, the hard mask pattern During the removal process, the poly plug 12 formed of the same material as the hard mask pattern 18a is lost. As a result, this wafer is defectively processed.

In addition, the CD and the opening of the bottom of the contact hole of the sampled wafer can be measured using a subsequent electrical property test, without checking in-line, in which case it is usually about two to three months for the electrical property test. It is time consuming and therefore unsuitable in terms of yield.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, the method of forming a contact hole of a semiconductor device for measuring CD, which can stably measure the CD and the opening of the bottom of the metal contact contact hole of the semiconductor device The purpose is to provide.

Another object of the present invention is to provide a method for measuring contact hole CD using the method for forming a contact hole of the semiconductor device.

According to an aspect of the present invention, there is provided a semiconductor substrate including a lower conductive layer, forming an interlayer insulating layer on an entire structure including the lower conductive layer, and forming the interlayer insulating layer. Depositing a hard mask made of the same material as the lower conductive layer, etching the hard mask, and performing an etching process using the etched hard mask to expose a contact hole through which the lower conductive layer is exposed. Forming a sacrificial protective film on the entire structure including the contact hole, removing the hard mask so that the sacrificial protective film applied inside the contact hole remains; Exposing the lower conductive layer by removing the sacrificial protective film remaining on the CD. It provides a method to form the contact hole of the conductor elements.

In addition, the present invention according to another aspect to achieve the above object, the step of selecting at least one of the wafers of the main wafer formed to the interlayer insulating film, and the hard mask in the method for forming the contact hole for the selected wafer Forming a contact hole by sequentially exposing the lower conductive layer to forming a contact hole; and measuring a CD (Critical Demension) of the bottom of the contact hole; do.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

3A to 3D are cross-sectional views illustrating a method for forming a contact hole for a metal contact of a DRAM device, for example, to explain a method for forming a contact hole in a semiconductor device for measuring CDs according to a preferred embodiment of the present invention. Here, the contact hole forming method of the semiconductor device is applied to the sampled wafer.

As shown in FIG. 3A, a first interlayer insulating layer 111 is deposited on the semiconductor substrate 110. In this case, the first interlayer insulating layer 111 is formed of an oxide-based material. For example, HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, USG (Un-doped Silicate Glass) film, FSG (FSG) film It may be formed of any one of a fluorinated Silicate glass (COE) film, a carbon doped oxide (CDO) film and an organo-silicate glass (OSG) film.

Subsequently, an etching process, a deposition process, and a planarization process may be performed to form a plug 112 as a lower conductive layer in the first interlayer insulating layer 111 so as to be connected to the active region of the semiconductor substrate 110. At this time, the lower plug 112 is preferably formed of polysilicon.

Subsequently, a second interlayer insulating layer 113 is deposited on the entire structure including the lower plug 112. In this case, the second interlayer insulating layer 113 may be formed of the same material as the first interlayer insulating layer 111.

Subsequently, the second interlayer insulating layer 113 may be planarized by performing a chemical mechanical polishing (CMP) process.                     

Subsequently, a bit line 114 and a hard mask 115 are formed on the second interlayer insulating layer 113. In this case, the bit line 114 may be formed of a polysilicon layer and a conductive layer or a polysilicon layer and a metal silicide layer. Here, the conductive layer is tungsten, and the metal silicide layer is a tungsten silicide layer. Meanwhile, the hard mask 115 is formed of a nitride film-based material.

Subsequently, spacers 116 are formed on both sidewalls of the hard mask 115 and the bit line 114. In this case, the spacer 116 may be formed of a nitride film or an oxide film-based material.

Next, a third interlayer insulating layer 117 is deposited on the entire structure to cover the semiconductor structure layer including the spacer 116. In this case, the third interlayer insulating layer 117 may be formed of the same material as the first interlayer insulating layer 111 or may have a stacked structure in which at least two or more layers of these materials are stacked.

Subsequently, a hard mask 118 is deposited on the third interlayer insulating film 117. In this case, the hard mask 118 is formed of the same material as the lower plug 112. It is preferably formed of polysilicon.

Subsequently, after forming a photoresist pattern (not shown) on the hard mask 118, an etching process using the photoresist pattern is performed to etch the hard mask 118.

Subsequently, after the strip process is removed to remove the photoresist pattern, an etching process using the etched hard mask 118 as an etching mask is performed to etch the third interlayer insulating layer 117 and the second interlayer insulating layer 113. As a result, a contact hole 119 through which the lower plug 112 is exposed is formed.

Subsequently, as illustrated in FIG. 3B, a sacrificial protective layer 120 is coated on the entire structure including the contact hole 119. In this case, the sacrificial protective film 120 is formed using a bottom anti reflection coating (BARC) or photoresist that is easily removed through a cleaning process. In this case, the antireflection film may be a planar organic or inorganic antireflection film.

Subsequently, as illustrated in FIG. 3C, a sacrificial protective film 120 applied on the hard mask 118 (see FIG. 3B) is removed by performing a front surface etching process such as a blanket or etch back. At the same time, the hard mask 118 is recessed and removed. As a result, a sacrificial protective film 120 having a profile as shown in FIG. 3C is formed.

Subsequently, as illustrated in FIG. 3D, the sacrificial protective film 120 remaining in the contact hole 119 (see FIG. 3A) is removed by performing a strip process. As a result, the lower plug 112 is exposed.

Subsequently, a cleaning process may be performed to remove residues that may remain in the contact hole 119.

Hereinafter, a method for measuring CD and opening of the bottom of the contact hole using the contact hole forming method of the semiconductor device according to the preferred embodiment of the present invention will be described with reference to FIG. 4.                     

Referring to FIG. 4, first, any one of the wafers advanced to the result shown in FIG. 3A is selected (sampled) (step S10). Then, the process proceeds sequentially from step S11 to S14 in the same manner as shown in Figs. 3b to 3d.

Subsequently, CD and bottom of the contact hole 119 are measured by SEM method with respect to the resultant shown in FIG. 3D. Since the measurement is performed with all of the upper hard mask 118 (see FIG. 3A) removed, the CD and the bottom of the contact hole 119 can be stably measured. In this case, when the measured CD of the bottom of the contact hole 119 is included in the spec (spec-in) range, the process of forming a contact hole is performed on the main lot wafer (spec-in) ( Step S15 and step S16). On the other hand, if it is not included in the specification (spec-out), the wafer is sampled again, and then steps S11 to S14 are sequentially performed under different process conditions.

On the other hand, in the case of specification-in, the contact hole forming process is performed under the same conditions applied to the wafer sampled for the main lot wafer (step S16). Then, the CD of the contact hole top is measured to determine whether the contact hole bottom is open (step S17). Then, as shown in FIG. 5, a metal contact 121 is formed inside the contact hole (step S18).

In step S18, the metal contact 121 forming process first deposits a polysilicon film so that the contact hole is filled. Then, the hard mask (not shown) is a process for performing a front surface etching process such as CMP (Chemical Mechanical Polishing) or etch back so as to be recessed.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment using a DRAM device as an example, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, it is possible to monitor whether the metal contact hole is defective without losing the sampled wafer, thereby improving the yield of the semiconductor device.

Claims (6)

Providing a semiconductor substrate having a lower conductive layer formed thereon; Forming an interlayer insulating film on the entire structure including the lower conductive layer; Depositing a hard mask made of the same material as the lower conductive layer on the interlayer insulating layer; Etching the hard mask; Forming a contact hole through which the lower conductive layer is exposed by performing an etching process using the etched hard mask; Applying a sacrificial protective film over the entire structure including the contact hole; Removing the hard mask so that the sacrificial protective film applied inside the contact hole remains; And Exposing the lower conductive layer by removing the sacrificial protective layer remaining in the contact hole; Method for forming a contact hole of a semiconductor device for measuring CD comprising a. The method of claim 1, The sacrificial protective film is an anti-reflection film or photoresist. The method of claim 1, And the hard mask is formed of a conductive material or a polysilicon film. Selecting at least one of the main wafers formed up to the interlayer insulating film of claim 1; In the method for forming a contact hole of the semiconductor device for measuring CDs according to any one of claims 1 to 3, the step of forming the hard mask and exposing the lower conductive layer are sequentially performed on the selected wafer. Forming a hole; And Measuring a CD (Critical Demension) of the bottom of the contact hole; Contact hole CD measurement method comprising a. The method of claim 4, wherein Forming a contact hole on the main wafer under the same conditions as the selected wafer when the CD of the contact hole bottom is included in the spec as a result of the CD measurement; And Determining whether the bottom of the contact hole is opened by measuring a CD of the upper portion of the contact hole formed on the main wafer; Contact hole CD measurement method further comprising. The method of claim 4, wherein The contact hole CD measuring method of measuring the CD of the bottom of the contact hole.

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