KR20060015386A - Method for forming multi electric layer of semiconductor device - Google Patents

Method for forming multi electric layer of semiconductor device Download PDF

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KR20060015386A
KR20060015386A KR1020040064111A KR20040064111A KR20060015386A KR 20060015386 A KR20060015386 A KR 20060015386A KR 1020040064111 A KR1020040064111 A KR 1020040064111A KR 20040064111 A KR20040064111 A KR 20040064111A KR 20060015386 A KR20060015386 A KR 20060015386A
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forming
conductive wiring
semiconductor device
wiring
carbon nanotube
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KR1020040064111A
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Korean (ko)
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김명진
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주식회사 하이닉스반도체
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Priority to KR1020040064111A priority Critical patent/KR20060015386A/en
Publication of KR20060015386A publication Critical patent/KR20060015386A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1094—Conducting structures comprising nanotubes or nanowires

Abstract

본 발명은 반도체 소자의 다층 도전 배선 형성 방법에 관한 것으로, 금속 배선을 탄소나노튜브 배선으로 형성하여 종래 기술에 따른 금속 배선보다 저항이 낮고, 선폭이 작게 형성되며 주변 회로 영역의 면적이 작아져서 칩 사이즈가 작아지며, 크로스 토크를 방지하는 반도체 소자의 다층 도전 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layer conductive wiring of a semiconductor device, wherein the metal wiring is formed of carbon nanotube wiring so that the resistance is lower than the metal wiring according to the prior art, the line width is smaller, and the area of the peripheral circuit area is smaller. The present invention relates to a method for forming a multilayer conductive wiring of a semiconductor device, the size of which is reduced and which prevents cross talk.

Description

반도체 소자의 다층 도전 배선 형성 방법{METHOD FOR FORMING MULTI ELECTRIC LAYER OF SEMICONDUCTOR DEVICE}TECHNICAL FIELD OF FORMING MULTI ELECTRIC LAYER OF SEMICONDUCTOR DEVICE

도 1은 종래 기술에 따른 반도체 소자의 다층 도전 배선 형성 방법을 도시한 단면도. 1 is a cross-sectional view showing a method for forming a multilayer conductive wiring of a semiconductor device according to the prior art.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 다층 도전 배선 형성 방법을 도시한 단면도들. 2A to 2E are cross-sectional views illustrating a method for forming a multilayer conductive wiring line of a semiconductor device according to the present invention.

< 도면의 주요 부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>

10, 100 : 반도체 기판 20, 110 : 제 1 절연막 10, 100: semiconductor substrate 20, 110: first insulating film

30, 130 : 제 1 도전 배선 40, 140 : 제 2 절연막30, 130: first conductive wiring 40, 140: second insulating film

50, 150 : 제 2 도전 배선 120 : 제 1 콘택홀50, 150: second conductive wiring 120: first contact hole

본 발명은 반도체 소자의 다층 도전 배선 형성 방법에 관한 것으로, 다층 도전 배선을 탄소 나노 튜브로 형성하여 종래 기술의 다층 도전 배선으로 사용된 금속 배선보다 저항이 낮고, 선폭이 작게 형성되며 주변 회로 영역의 면적이 작아져서 칩 사이즈가 작아지며, 크로스 토크를 방지하는 반도체 소자의 다층 도전 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer conductive wiring of a semiconductor device, wherein the multilayer conductive wiring is formed of carbon nanotubes so that the resistance is lower than that of the metal wiring used as the multilayer conductive wiring of the prior art, and the line width is formed to be smaller. It is related with the method of forming a multilayer conductive wiring of the semiconductor element which area becomes small, chip size becomes small, and crosstalk is prevented.

도 1은 종래 기술에 따른 반도체 소자의 다층 도전 배선 형성 방법을 도시한 단면도로써 상기 다층 도전 배선은 금속 배선을 말한다. 1 is a cross-sectional view showing a method for forming a multilayer conductive wiring of a semiconductor device according to the prior art, wherein the multilayer conductive wiring refers to a metal wiring.

도 1을 참조하면, 하부 구조를 포함한 반도체 기판(10)의 전체 표면 상부에 제 1 절연막(20)을 형성한 후 제 1 절연막(20) 상에 제 1 콘택홀(미도시)을 형성한다.Referring to FIG. 1, after forming the first insulating film 20 over the entire surface of the semiconductor substrate 10 including the lower structure, a first contact hole (not shown) is formed on the first insulating film 20.

다음에, 제 1 절연막(20) 상부에 상기 제 1 콘택홀(미도시)을 통해 연결되는 제 1 도전 배선(30)을 형성하고, 제 1 도전 배선(30) 상부에 제 2 절연막(40)을 형성한다.Next, a first conductive wire 30 is formed on the first insulating film 20 through the first contact hole (not shown), and a second insulating film 40 is disposed on the first conductive wire 30. To form.

그 다음에, 제 2 절연막(40) 상부에 제 2 도전 배선(50)을 형성하는 단계를 포함하는 것을 특징으로 한다. Next, the second conductive wiring 50 is formed on the second insulating film 40.

상술한 종래 기술에 따른 반도체 소자의 다층 도전 배선 형성 방법에서, 텅스텐, 알루미늄 및 구리를 이용하여 제 1 및 제 2 도전 배선을 형성하는데 공정이 미세화됨에 따라 시그널 커플링에 의한 크로스 토크로 인하여 테스트하는 공정에서 칩 페일이 발생하는 문제점이 있으며, 상기 금속들의 저항이 증가하면서 고집적화의 한계가 발생하는 문제점이 있다. In the above-described method for forming a multilayer conductive wiring of a semiconductor device according to the prior art, the first and second conductive wirings are formed by using tungsten, aluminum and copper, which are tested due to cross talk by signal coupling as the process becomes finer. There is a problem that chip fail occurs in the process, there is a problem that the limit of high integration occurs as the resistance of the metals increase.

상기 문제점을 해결하기 위하여, 도전 배선을 탄소 나노 튜브로 형성하여 종래 기술에 따른 금속으로 형성된 도전 배선보다 저항이 낮고, 선폭이 작게 형성되며 주변 회로 영역의 면적이 작아져서 칩 사이즈가 작아지는 효과가 있다. In order to solve the above problems, the conductive wiring is formed of carbon nanotubes, so that the resistance is lower than the conductive wiring formed of metal according to the prior art, and the line width is smaller, and the area of the peripheral circuit area is smaller, thereby reducing the chip size. have.                         

또한, 캐퍼시턴스를 최적화시켜 도전 배선 커플링 현상에 의한 크로스 토크를 방지하는 반도체 소자의 다층 도전 배선 형성 방법을 제공하는 것을 그 목적으로 한다. It is also an object of the present invention to provide a method for forming a multilayer conductive wiring of a semiconductor device that optimizes capacitance and prevents crosstalk due to conductive wiring coupling phenomenon.

본 발명에 따른 반도체 소자의 다층 도전 배선 형성 방법은The method for forming a multilayer conductive wiring of a semiconductor device according to the present invention

반도체 기판의 전체 표면 상부에 제 1 절연막을 형성하는 단계;Forming a first insulating film over the entire surface of the semiconductor substrate;

상기 제 1 절연막을 식각하여 제 1 도전 배선 콘택홀을 형성하는 단계;Etching the first insulating layer to form a first conductive wiring contact hole;

상기 제 1 도전 배선 콘택홀을 통해 상기 반도체 기판에 접속되는 탄소 나노 튜브의 제 1 도전 배선을 형성하는 단계; 및Forming a first conductive wire of a carbon nanotube connected to the semiconductor substrate through the first conductive wire contact hole; And

후속 공정으로 상기 제 1 도전 배선에 접속되는 다층 도전 배선을 형성하는 단계Forming a multilayer conductive wiring connected to said first conductive wiring in a subsequent process

를 포함하는 반도체 소자의 다층 도전 배선 형성 방법이다.The multilayer conductive wiring formation method of the semiconductor element containing these.

본 발명은 원리는 종래 기술의 다층 도전 배선보다 저항이 낮고, 선폭이 작게 형성되며 주변 회로 영역의 면적이 작아져서 칩 사이즈가 작아지는 효과를 제공하기 위하여 우수한 기계적 특성, 전기적 선택성, 뛰어난 전계방출 특성, 고효율의 수소저장매체 특성 등을 지니는 신소재인 탄소 나노 튜브를 전기방전법, 레이저 증착법, 열분해 증착법, 열화학 기상 증착 성장법 및 플라즈마 화학 기상 증착법을 이용하여 다층 도전 배선을 형성하는 기술에 있다. Principle of the present invention is that the mechanical resistance, electrical selectivity, and excellent field emission characteristics are excellent in order to provide the effect that the resistance is lower, the line width is smaller, and the area of the peripheral circuit area is smaller than the conventional multilayer conductive wiring, so that the chip size is smaller. The present invention relates to a technique for forming a multilayer conductive wiring by using a carbon nanotube, which is a new material having a high efficiency of a hydrogen storage medium, by using an electric discharge method, a laser deposition method, a pyrolysis deposition method, a thermochemical vapor deposition growth method, and a plasma chemical vapor deposition method.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다. Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.                     

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 다층 도전 배선 형성 방법을 도시한 단면도들이다. 2A to 2E are cross-sectional views illustrating a method of forming a multilayer conductive wiring line of a semiconductor device according to the present invention.

도 2a를 참조하면, 반도체 기판(100)의 전체 표면 상부에 제 1 절연막(110)을 형성한다. Referring to FIG. 2A, the first insulating layer 110 is formed on the entire surface of the semiconductor substrate 100.

도 2b를 참조하면, 제 1 절연막(110)을 식각하여 제 1 도전 배선 콘택홀(120)을 형성한다. Referring to FIG. 2B, the first insulating layer 110 is etched to form the first conductive wiring contact hole 120.

도 2c를 참조하면, 상기 제 1 도전 배선 콘택홀(120)을 통해 반도체 기판에 접속되는 탄소 나노 튜브로 제 1 도전 배선(130)을 형성한다. 이때, 상기 탄소 나노 튜브의 도전 배선을 형성하는 공정은 전기방전법, 레이저 증착법, 열분해 증착법, 열화학 기상 증착 성장법 및 플라즈마 화학 기상 증착법 중 선택된 어느 하나의 방법을 사용하여 형성하는 것이 바람직하다. Referring to FIG. 2C, the first conductive wiring 130 is formed of carbon nanotubes connected to the semiconductor substrate through the first conductive wiring contact hole 120. At this time, the process of forming the conductive wiring of the carbon nanotubes is preferably formed using any one method selected from the electric discharge method, laser deposition method, pyrolysis deposition method, thermochemical vapor deposition growth method and plasma chemical vapor deposition method.

도 2d를 참조하면, 제 1 도전 배선(130) 상부에 제 2 절연막(140)을 형성한다.Referring to FIG. 2D, a second insulating layer 140 is formed on the first conductive wire 130.

도 2e를 참조하면, 제 1 도전 배선(130)에 접속되도록 탄소 나노 튜브로 제 2 도전 배선(150)을 형성한다. 이때, 상기 탄소 나노 튜브의 도전 배선을 형성하는 공정은 전기방전법, 레이저 증착법, 열분해 증착법, 열화학 기상 증착 성장법 및 플라즈마 화학 기상 증착법 중 선택된 어느 하나의 방법을 사용하여 형성하는 것이 바람직하다. Referring to FIG. 2E, the second conductive wiring 150 is formed of carbon nanotubes so as to be connected to the first conductive wiring 130. At this time, the process of forming the conductive wiring of the carbon nanotubes is preferably formed using any one method selected from the electric discharge method, laser deposition method, pyrolysis deposition method, thermochemical vapor deposition growth method and plasma chemical vapor deposition method.

본 발명에 따른 반도체 소자의 다층 도전 배선 형성 방법은 텅스텐, 알루미 늄 및 구리로 형성하는 다층 도전 배선을 탄소 나노 튜브로 형성하여 종래 기술에 따른 다층 도전 배선보다 저항이 낮고, 선폭이 작게 형성되며 주변 회로 영역의 면적이 작아져서 칩 사이즈가 작아지는 효과가 있다. In the method for forming a multilayer conductive wiring of a semiconductor device according to the present invention, the multilayer conductive wiring formed of tungsten, aluminum and copper is formed of carbon nanotubes, so that the resistance is lower than the multilayer conductive wiring according to the prior art, and the line width is formed smaller. There is an effect that the area of the circuit area is smaller and the chip size is smaller.

또한, 캐퍼시턴스를 최적화시켜 금속 배선 커플링 현상에 의한 크로스 토크를 방지하는 효과가 있다. In addition, there is an effect of optimizing the capacitance to prevent crosstalk due to the metal wiring coupling phenomenon.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (2)

반도체 기판의 전체 표면 상부에 제 1 절연막을 형성하는 단계;Forming a first insulating film over the entire surface of the semiconductor substrate; 상기 제 1 절연막을 식각하여 제 1 도전 배선 콘택홀을 형성하는 단계;Etching the first insulating layer to form a first conductive wiring contact hole; 상기 제 1 도전 배선 콘택홀을 통해 상기 반도체 기판에 접속되는 탄소 나노 튜브로 제 1 도전 배선을 형성하는 단계; 및Forming a first conductive wire from a carbon nanotube connected to the semiconductor substrate through the first conductive wire contact hole; And 후속 공정으로 상기 제 1 도전 배선에 접속되는 다층 도전 배선을 탄소 나노 튜브로 형성하는 단계Forming a multi-layer conductive wiring connected to the first conductive wiring by a carbon nanotube in a subsequent process 를 포함하는 반도체 소자의 다층 도전 배선 형성 방법. Multi-layer conductive wiring forming method of a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 탄소 나노 튜브의 도선 배선을 형성하는 단계는 전기방전법, 레이저 증착법, 열분해 증착법, 열화학 기상 증착 성장법 및 플라즈마 화학 기상 증착법 중 선택된 어느 하나의 방법을 사용하여 형성하는 것을 특징으로 하는 반도체 소자의 다층 도전 배선 형성 방법. The forming of the conductive wire of the carbon nanotube may be performed using any one method selected from among an electric discharge method, a laser deposition method, a pyrolysis deposition method, a thermochemical vapor deposition growth method, and a plasma chemical vapor deposition method. Method for forming multilayer conductive wiring.
KR1020040064111A 2004-08-14 2004-08-14 Method for forming multi electric layer of semiconductor device KR20060015386A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227919B2 (en) 2008-07-11 2012-07-24 Samsung Electronics Co., Ltd. Interconnection structure and electronic device employing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227919B2 (en) 2008-07-11 2012-07-24 Samsung Electronics Co., Ltd. Interconnection structure and electronic device employing the same

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