KR20060000889A - 높은 신뢰성을 갖는 반도체메모리소자 및 그를 위한구동방법 - Google Patents
높은 신뢰성을 갖는 반도체메모리소자 및 그를 위한구동방법 Download PDFInfo
- Publication number
- KR20060000889A KR20060000889A KR1020040049875A KR20040049875A KR20060000889A KR 20060000889 A KR20060000889 A KR 20060000889A KR 1020040049875 A KR1020040049875 A KR 1020040049875A KR 20040049875 A KR20040049875 A KR 20040049875A KR 20060000889 A KR20060000889 A KR 20060000889A
- Authority
- KR
- South Korea
- Prior art keywords
- mrs
- semiconductor memory
- function
- output
- decoding
- Prior art date
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
Claims (4)
- 복수의 필드로 구성된 MRS를 통해 기능을 설정하는 반도체메모리소자에 있어서,상기 필드들의 코드값을 인가받아 디코딩하기 위한 디코딩수단; 및상기 디코딩수단의 복수의 출력신호 중 다수개가 활성화된 경우에는 출력신호인 기능 설정신호를 이전 상태로 유지하고, 상기 디코딩수단의 복수의 출력신호 중 하나만이 활성화된 경우에는 이에 해당하는 기능 설정신호를 활성화시키기 위한 출력수단을 구비하는 반도체메모리소자.
- 제1항에 있어서,상기 출력수단은 상기 디코딩수단의 출력신호 중 해당 출력신호를 셋신호로 가지며, 이외 출력신호를 리셋신호로 갖는 복수의 RS 래치로 구현되는 것을 특징으로 하는 반도체메모리소자.
- 제2항에 있어서,상기 RS래치는 크로스 커플드된 낸드게이트로 구현되는 것을 특징으로 하는 반도체메모리소자.
- 반도체메모리소자의 모드의 기능을 정의하기 위해 MRS에 인가된 코드값을 디코딩하는 단계;상기 디코딩된 코드값이 MRS에 정의된 경우인지, 또는 정의되지 않은 경우인지를 판별하는 단계; 및상기 판별단계에서 MRS에 정의된 경우에는 해당 기능 설정신호를 활성화시키고, 정의되지 않은 경우에는 이전 기능 설정신호를 유지시켜 출력시키는 단계를 갖는 반도체메모리소자의 구동방법.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040049875A KR100625293B1 (ko) | 2004-06-30 | 2004-06-30 | 높은 신뢰성을 갖는 반도체메모리소자 및 그를 위한구동방법 |
TW093141588A TWI293463B (en) | 2004-06-30 | 2004-12-31 | Semiconductor memory device capable of stably setting mode register set and method therefor |
US11/030,485 US7065000B2 (en) | 2004-06-30 | 2005-01-05 | Semiconductor memory device capable of stably setting mode register set and method therefor |
CN200510069387.7A CN1716444B (zh) | 2004-06-30 | 2005-05-16 | 能稳定设置模式寄存器设置的半导体存储器件及方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040049875A KR100625293B1 (ko) | 2004-06-30 | 2004-06-30 | 높은 신뢰성을 갖는 반도체메모리소자 및 그를 위한구동방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20060000889A true KR20060000889A (ko) | 2006-01-06 |
KR100625293B1 KR100625293B1 (ko) | 2006-09-20 |
Family
ID=35513741
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020040049875A KR100625293B1 (ko) | 2004-06-30 | 2004-06-30 | 높은 신뢰성을 갖는 반도체메모리소자 및 그를 위한구동방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7065000B2 (ko) |
KR (1) | KR100625293B1 (ko) |
CN (1) | CN1716444B (ko) |
TW (1) | TWI293463B (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101124284B1 (ko) * | 2005-12-15 | 2012-03-15 | 주식회사 하이닉스반도체 | 모드 레지스터 셋 디코더 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100799132B1 (ko) | 2006-06-29 | 2008-01-29 | 주식회사 하이닉스반도체 | 초기값변경이 가능한 모드레지스터셋회로. |
KR100834395B1 (ko) * | 2006-08-31 | 2008-06-04 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR100892670B1 (ko) * | 2007-09-05 | 2009-04-15 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 프리차지 제어 회로 |
CN115602222A (zh) * | 2021-07-09 | 2023-01-13 | 长鑫存储技术有限公司(Cn) | 一种编译方法、编译电路、模式寄存器和存储器 |
CN115602223A (zh) * | 2021-07-09 | 2023-01-13 | 长鑫存储技术有限公司(Cn) | 一种编译方法、编译电路、模式寄存器和存储器 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5459693A (en) * | 1990-06-14 | 1995-10-17 | Creative Integrated Systems, Inc. | Very large scale integrated planar read only memory |
JP3080520B2 (ja) * | 1993-09-21 | 2000-08-28 | 富士通株式会社 | シンクロナスdram |
JP3351953B2 (ja) * | 1996-03-19 | 2002-12-03 | 富士通株式会社 | モードレジスタ制御回路およびこれを有する半導体装置 |
JP4141520B2 (ja) * | 1997-11-14 | 2008-08-27 | 株式会社ルネサステクノロジ | 同期型半導体記憶装置 |
JP3204384B2 (ja) * | 1997-12-10 | 2001-09-04 | エヌイーシーマイクロシステム株式会社 | 半導体記憶回路 |
DE19829288C2 (de) * | 1998-06-30 | 2001-03-01 | Siemens Ag | Dynamische Halbleiter-Speichervorrichtung und Verfahren zur Initialisierung einer dynamischen Halbleiter-Speichervorrichtung |
JP2000036192A (ja) | 1998-07-17 | 2000-02-02 | Fujitsu Ltd | 半導体集積回路 |
KR100319713B1 (ko) * | 1998-07-31 | 2002-04-22 | 윤종용 | 동기형반도체메모리장치의프로그램가능한모드레지스터 |
KR100652362B1 (ko) * | 2000-09-20 | 2006-11-30 | 삼성전자주식회사 | 정상동작에서는 고정된 카스 레이턴시를 갖고테스트시에는 다양한 카스 레이턴시로 테스트 가능한반도체 메모리 장치 |
US6529424B2 (en) * | 2001-05-17 | 2003-03-04 | Koninklijke Philips Electronics N.V. | Propagation delay independent SDRAM data capture device and method |
JP4000028B2 (ja) * | 2001-09-18 | 2007-10-31 | 株式会社東芝 | 同期型半導体記憶装置 |
KR100443505B1 (ko) * | 2001-10-23 | 2004-08-09 | 주식회사 하이닉스반도체 | 확장 모드 레지스터 세트의 레지스터 회로 |
KR100455393B1 (ko) | 2002-08-12 | 2004-11-06 | 삼성전자주식회사 | 리프레시 플래그를 발생시키는 반도체 메모리 장치 및반도체 메모리 시스템. |
-
2004
- 2004-06-30 KR KR1020040049875A patent/KR100625293B1/ko active IP Right Grant
- 2004-12-31 TW TW093141588A patent/TWI293463B/zh not_active IP Right Cessation
-
2005
- 2005-01-05 US US11/030,485 patent/US7065000B2/en active Active
- 2005-05-16 CN CN200510069387.7A patent/CN1716444B/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101124284B1 (ko) * | 2005-12-15 | 2012-03-15 | 주식회사 하이닉스반도체 | 모드 레지스터 셋 디코더 |
Also Published As
Publication number | Publication date |
---|---|
US7065000B2 (en) | 2006-06-20 |
US20060002225A1 (en) | 2006-01-05 |
CN1716444B (zh) | 2010-11-03 |
TW200601336A (en) | 2006-01-01 |
CN1716444A (zh) | 2006-01-04 |
TWI293463B (en) | 2008-02-11 |
KR100625293B1 (ko) | 2006-09-20 |
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