KR20050112845A - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

In order to lower the address voltage and facilitate address discharge in the plasma display panel, the voltage of the scan electrode is made equal to the selection voltage for a period shorter than the selection time of one scan electrode in the final period of the reset period. In this way, erroneous discharge which may be caused by a low selection voltage can be eliminated.

Description

Driving method of plasma display panel and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

The present invention relates to a plasma display panel (PDP) and a driving method thereof.

A plasma display panel is a flat display device that displays characters or images by using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size.

The plasma display panel generally includes a plurality of address electrodes extending in the column direction and a plurality of sustain electrodes and scan electrodes extending in the row direction, and the sustain electrodes are formed corresponding to the scan electrodes. At this time, the discharge space at the intersection of the address electrode and the sustain and scan electrodes forms a discharge cell.

In general, such a plasma display panel is driven by dividing one frame into a plurality of subfields, and gray scales are expressed by a combination of subfields. In general, each subfield includes a reset period, an address period, and a sustain period as shown in FIG. The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

Referring to FIG. 1, the voltage of the scan electrode Y is gradually decreased in the form of a ramp from the Vs voltage to 0V while the address electrode A is biased to 0V in the reset period. The sum of the voltage applied between the address electrode A and the scan electrode Y and the wall voltage due to the wall charges formed on the address electrode A and the scan electrode Y are maintained at the discharge start voltage. Next, a scan pulse having a voltage equal to the final voltage of the reset period (0 V in FIG. 1) is applied to the scan electrode Y selected in the address period, and an address pulse of a positive voltage Va is applied to the address electrode A. do.

In the wall charge state set in the reset period, when the 0 V voltage is applied to the scan electrode Y and the address electrode A, the discharge start voltage is maintained. Therefore, in the address period, the positive voltage Va is greater than the discharge start voltage. As high as the voltage is applied. However, since the scan pulses must be sequentially applied to the plurality of scan electrodes in the limited address period, the width of the scan pulses is set narrow. If the delay time for the discharge (hereinafter referred to as "address discharge") to occur in the address period is longer than the width of the scan pulse, the address discharge cannot occur. Therefore, in order to reduce the discharge delay time, a Va voltage is applied to the address electrode A to increase the voltages of the address electrode A and the scan electrode Y by a Va voltage higher than the discharge start voltage to reduce the discharge delay time.

In recent years, the partial pressure of xenon (Xe) injected into the discharge gas has been increased to increase the efficiency of the plasma display panel. When the partial pressure of xenon increases, the voltage required for discharge increases, so that the discharge delay time may not be shortened only by the Va voltage applied to the address electrode A. FIG. As a result, the address discharge delay time may increase, and thus, discharge may occur after or at the end of the scan pulse, resulting in weaker discharge than the desired discharge, thereby preventing wall charges from being formed normally. As a result, a low discharge that does not occur or a weak discharge occurs in the sustain period.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of driving a plasma display panel that can easily cause an address discharge.

In order to solve this problem, the present invention lowers the scan electrode voltage in the final stage of the reset period by a predetermined voltage for a short period.

According to an aspect of the present invention, there is provided a plasma including a plurality of first electrodes and a plurality of second electrodes formed in a direction crossing the first electrode, and a discharge cell defined by the first electrode and the second electrode. A method of driving a display panel is provided. The driving method of the present invention includes gradually lowering a voltage of the first electrode from a first voltage to a second voltage during a first period of a reset period, the second period of the second period of the reset period after the first period. Maintaining the voltage of the first electrode substantially to the second voltage for a period other than three periods, and applying a third voltage to the first electrode of a discharge cell to be selected among the discharge cells during an address period; Applying a fourth voltage to the second electrode. In this case, a fifth voltage lower than the second voltage is applied to the first electrode during the third period, and the third period is 2 kV or more.

According to one embodiment of the invention, the third period is 10 ms or less.

According to another embodiment of the present invention, the fifth voltage is a voltage at the same level as the third voltage.

According to another feature of the present invention, there is provided a plasma including a plurality of first electrodes and a plurality of second electrodes formed in a direction crossing the first electrode, and a discharge cell defined by the first electrode and the second electrode. A plasma display device including a display panel and a driving circuit configured to apply driving signals to the first and second electrodes are provided. The driving circuit may gradually reduce a voltage obtained by subtracting the voltage of the second electrode from the voltage of the first electrode from the first voltage to the second voltage during the first period, and then, except for the third period of the second period. The second voltage is substantially maintained during the third period, and the voltage obtained by subtracting the voltage of the second electrode from the voltage of the first electrode is set to a third voltage lower than the second voltage during the third period. At this time, the third period is 10 ms or less.

According to one embodiment of the invention, the third period is at least 2 ms.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In the present invention, the wall charge refers to a charge formed in the wall of the discharge cell (eg, the dielectric layer) close to each electrode and accumulated in the electrode. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. And the wall voltage refers to the potential difference existing in the wall of the discharge cell by the wall charge. In addition, the weak discharge refers to a discharge that occurs so that the voltage applied to the discharge cell by the wall voltage of the discharge cell and the external applied voltage can maintain the discharge start voltage.

2 is a schematic diagram of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address driver 300, and a sustain electrode driver (hereinafter referred to as an “X electrode driver”). 400 and a scan electrode driver (hereinafter referred to as a “Y electrode driver”) 500.

The plasma display panel 100 includes a plurality of address electrodes A1 to Am extending in the column direction, and a plurality of sustain electrodes (hereinafter, referred to as "X electrodes") which are arranged in pairs to each other in the row direction (hereinafter referred to as "X electrode"). Xn) and scan electrodes (hereinafter referred to as "Y electrodes") (Y1 to Yn). The X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and generally have one end connected in common to each other. At this time, the discharge space at the intersection of the address electrodes A1 to Am and the X and Y electrodes X1 to Xn and Y1 to Yn forms a discharge cell.

The controller 200 receives an image signal from the outside and outputs an address driving control signal, an X electrode driving control signal, and a Y electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield is composed of a reset period, an address period, and a sustain period.

The address driver 300 receives an address drive control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode A1-Am. The X electrode driver 400 receives the X electrode driving control signal from the controller 200 to apply a driving voltage to the X electrodes X1 to Xn, and the Y electrode driver 500 controls the Y electrode driving from the controller 200. The signal is received and a driving voltage is applied to the Y electrodes Y1-Yn.

Hereinafter, driving waveforms applied to the A electrode, the X electrode, and the Y electrode in each subfield will be described with reference to FIGS. 3 and 4. In the following description, a discharge cell formed by one A electrode, an X electrode, and a Y electrode will be described.

3 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention.

As shown in Fig. 3, each subfield in the drive waveform according to the first embodiment of the present invention includes a reset period Pr, an address period Pa, and a sustain period Ps. The reset period Pr includes a rising period Pr1 and a falling period Pr2. In FIG. 4, the final voltage applied to the Y electrode in the falling period Pr2 and the voltage applied to the Y electrode selected in the address period Pa are illustrated as negative voltages.

The rising period Pr1 of the reset period Pr is a period in which wall charges are formed on the Y electrode, the X electrode and the A electrode, and the falling period Pr2 partially erases the wall charges formed in the rising period Pr1 to discharge the address. To facilitate the period. The address period Pa is a period for selecting a discharge cell to cause sustain discharge in the sustain period from among the plurality of discharge cells. The sustain period Ps is a period for sustain discharge of the discharge cells selected in the address period Pa by applying sustain pulses sequentially to the Y electrode and the X electrode.

First, in the rising period Pr1 of the reset period Pr, a waveform gradually rising from the voltage Vs to the voltage Vset is applied to the Y electrode while maintaining the voltages of the A and X electrodes as the reference voltages. While this waveform is rising, weak discharge occurs in all discharge cells between the Y and X electrodes and between the Y and A electrodes. As a result, negative wall charges are accumulated at the Y electrode, and positive wall charges are accumulated at the A electrode and the X electrode at the same time.

In the falling period Pr2 of the reset period Pr, the waveform gradually falls from the Vs voltage to the Vnf voltage at the Y electrode while the reference voltage and the Ve voltage are applied to the A and X electrodes, respectively, during the first period Pr21. Is applied. While this waveform is falling, again weak discharge occurs in all the discharge cells, so that the negative wall charges of the Y electrode are erased and the positive wall charges of the X electrode and the A electrode are erased. At this time, the difference Ve-Vnf between the voltage Ve applied to the X electrode and the voltage Venf applied to the Y electrode is set to about the discharge start voltage between the Y electrode and the X electrode. Then, the wall voltage between the Y electrode and the X electrode at the final voltage Vnf of the falling waveform is close to 0 V, so that discharge cells in which the address discharge has not occurred in the address period can be prevented from being discharged in the sustain period.

The wall voltage between the A electrode and the Y electrode can be lowered by setting the final voltage of the falling waveform to the negative voltage of -Vnf. Next, the voltage of the Y electrode is kept short at the -Vnf voltage for the second period Pr22. In this second period Pr22, the wall voltage between the Y electrode and the A electrode is almost equal to the voltage obtained by adding the Vnf voltage to the discharge start voltage between the Y electrode and the A electrode.

Next, in the address period Pa, the scan voltage of the Vscl voltage is applied to the Y electrode to be selected while the Y electrode is held at the Vsch voltage. The address voltage Va is applied to the A electrode of the discharge cell to be turned on among the discharge cells formed by the Y electrode to which the Vscl voltage is applied. Then, the address discharge is caused by the difference between the voltage Va applied to the A electrode and the voltage Vnf applied to the Y electrode and the wall voltages formed on the A and Y electrodes.

If the -Vnf voltage and the -Vscl voltage are the same, in the discharge cell to be selected in the voltage Vnf and the address period Pa between the A electrode and the Y electrode in the second period Pr22 of the falling period Pr2. The voltage Va-Vscl between the A electrode and the Y electrode of D is different by the Va voltage. Since the wall charge state of the discharge cell before the address discharge occurs is the same as the final wall charge state in the second period Pr22 of the falling period Pr2, the discharge voltage in the address period is equal to the magnitude of the address voltage Va. Is determined by. However, since the address voltage Va cannot use a high level voltage due to the characteristics of the circuit for supplying the address voltage, when the -Vnf voltage and the -Vscl voltage are the same, the discharge voltage is low and the address discharge is easily caused by the discharge delay. Do not.

Therefore, in the first embodiment of the present invention, the voltage Vscl is lower than the voltage Vnf, so that the voltage Va + Vscl between the A electrode and the Y electrode at the address discharge is reduced in the second period Pr22 of the falling period Pr2. The voltage Vnf between the and Y electrodes is increased by (Va-Vscl + Vnf). As a result, the discharge voltage during the address discharge becomes high, so that the address discharge can easily occur, and the address voltage Va can be reduced.

Next, in the sustain period Ps, sustain discharge pulses are sequentially applied to the Y electrode and the X electrode. The sustain discharge pulse is a pulse that causes the voltage difference between the Y electrode and the X electrode to be alternately Vs voltage and -Vs voltage. The Vs voltage is a voltage capable of causing sustain discharge between the Y electrode and the X electrode together with the wall voltage formed in the discharge cell in the address period Pa. In FIG. 4, the sustain discharge pulse is illustrated as a pulse having an alternate voltage of Vs and a ground voltage.

As described above, in the first exemplary embodiment of the present invention, the voltage Vscl applied to the Y electrode selected in the address period Pa is lower than the final voltage Vnf applied to the Y electrode in the falling period Pr2, thereby causing the address voltage. Va can be lowered and address discharge can be facilitated.

However, when the ambient temperature becomes high or the temperature of the plasma display panel increases, or when there are many priming particles in the discharge cell, the discharge may easily occur even at a low voltage. That is, under these conditions, the externally applied voltage (Vnf−) is lower than the final state of the reset period Pr by the voltage Vscl applied to the Y electrode even in the discharge cell in which the Va voltage is not applied to the A electrode in the address period Pa. Discharge may occur since it is as large as the voltage. Due to such a discharge, a wall voltage is formed in the discharge cells which are not selected, and erroneous discharge may occur in the organic period Ps.

Hereinafter, an embodiment capable of removing such an error discharge will be described in detail with reference to FIG. 4.

4 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention. As shown in Fig. 4, the drive waveform according to the second embodiment of the present invention is the same as the first embodiment except for the final state of the reset period.

In detail, in the second embodiment of the present invention, in the second period Pr22 of the falling period Pr2, the voltage of the Y electrode is reduced by the voltage ΔV for a predetermined period Δt. In this way, discharge may occur between the Y electrode and the A electrode during the Δt period under the conditions in which the above-described false discharge may occur. In other words, an error discharge that may occur due to the Vscl voltage applied to the Y electrode in the address period Pa is formed in advance during the second period Pr22 of the falling period Pr, so that the error discharge does not occur in the address period Pa. do.

Next, referring to Tables 1 and 2, an appropriate range of the Δt period in the second embodiment of the present invention will be described. In Table 1 and Table 2, the 'x' indicates a case in which the above-mentioned misdischarge or low discharge does not occur, and the '○' indicates a case in which the misdischarge or low discharge occurs.

First, if the Δt period is too short, erroneous discharge cannot be formed in advance in the second period Pr22 of the falling period Pr, so the period of Δt needs to be longer than a certain period. That is, as shown in Table 1, if the period of? T is set to 2 ms or more, mis-discharge or low discharge in the address period and the sustain period can be eliminated.

Δt [㎲] 0 One 2 3 4 5 6 7 Discharge / Low Discharge ○ ○ × × × × × ×

In addition, it is necessary to prevent a large amount of wall charges from forming in the Δt period so that the erroneous discharge in the Δt period does not form the same condition as the erroneous discharge in the address period Pa. That is, it is necessary to make the period of Δt shorter than a certain period. In other words, as shown in Table 2, when the period of? T is set to 10 ms or less, mis-discharge or low discharge in the address period and the sustain period can be eliminated.

Δt [㎲] 4 5 6 7 8 9 10 11 12 Discharge / Low Discharge × × × × × × × ○ ○

As can be seen from Table 1 and Table 2, when the period of? T is set to 2 ms or more and 10 ms or less, mis-discharge or low discharge in the address period and the sustain period can be eliminated.

As described above, according to the second embodiment of the present invention, this misinterpretation is performed in the final stage of the falling period Pr2 in order to eliminate the misdischarge which may be formed in the address period Pa by the low voltage Vscl of the Y electrode. Conditions similar to those under which transitions can be formed are formed. Then, discharge may occur in the final stage of the falling period Pr2 to eliminate erroneous discharges that may be formed in the address period Pa.

In the first and second embodiments of the present invention, waveforms in which the falling waveform is applied after the rising waveform is applied in all reset periods have been described. In contrast, the first embodiment of the present invention has been described in US Pat. No. 6,294,875 to Kurata et al. It is also applicable to driving waveforms in which the rising waveform and the falling waveform are applied only in the main reset period, and only the falling waveform is applied in the negative reset period.

In addition, in the first and second embodiments of the present invention, the voltage of the Y electrode is gradually decreased in the form of a lamp in the falling period Pr2. However, the voltage of the Y electrode is gradually decreased in the form of a log, a RC curve, or the like. You can also In addition, in the first and second embodiments of the present invention, the voltage of the Y electrode is gradually changed while the voltages of the A and X electrodes are biased. However, if the relative voltage difference between the electrodes described in the present invention is satisfied, the Y electrode, The voltages applied to the X electrode and the A electrode may be changed in other forms.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the address discharge can be easily generated, and the address voltage can be lowered. In addition, erroneous discharges that may occur in the address period can be eliminated in advance in the reset period.

1 is a driving waveform diagram of a plasma display panel according to the prior art.

2 is a schematic diagram of a plasma display device according to an exemplary embodiment of the present invention.

3 and 4 are driving waveform diagrams of the plasma display panel according to the first and second embodiments of the present invention, respectively.

Claims (8)

A method of driving a plasma display panel including a plurality of first electrodes and a plurality of second electrodes formed in a direction crossing the first electrodes, the discharge cells being defined by the first electrodes and the second electrodes. , Gradually lowering the voltage of the first electrode from the first voltage to the second voltage during the first period of the reset period, Maintaining the voltage of the first electrode substantially at the second voltage for a period other than a third period of the second period of the reset period after the first period, and Applying a third voltage to the first electrode and a fourth voltage to the second electrode of the discharge cell to be selected among the discharge cells during an address period; And a fifth voltage lower than the second voltage is applied to the first electrode during the third period, and the third period is 2 kV or more. The method of claim 1, And the third period is 10 ms or less. The method according to claim 1 or 2, And the fifth voltage is a voltage having the same level as the third voltage. The method according to claim 1 or 2, A method of driving a plasma display panel, wherein the second electrode is maintained at a constant voltage during the first period and the second period. A plasma display panel including a plurality of first electrodes and a plurality of second electrodes formed in a direction crossing the first electrodes, wherein a discharge cell is defined by the first electrode and the second electrode, and A driving circuit applying a driving signal to the first electrode and the second electrode, The driving circuit may gradually reduce a voltage obtained by subtracting the voltage of the second electrode from the voltage of the first electrode from the first voltage to the second voltage during the first period, and then, except for the third period of the second period. Substantially maintain the second voltage during the third period, and set a voltage obtained by subtracting the voltage of the second electrode from the voltage of the first electrode during the third period to a third voltage lower than the second voltage, And the third period is 10 ms or less. The method of claim 5, And the third period is 2 ms or more. The method according to claim 5 or 6, The driving circuit selectively applies a scan voltage to the plurality of first electrodes in an address period, and an address voltage to the second electrode of a discharge cell to be turned on among discharge cells formed by the first electrode to which the scan voltage is applied. Is authorized, The third voltage is a voltage having the same level as the scan voltage minus a voltage applied to a second electrode of a discharge cell other than the discharge cell to be turned on among discharge cells formed by the first electrode to which the scan voltage is applied. Plasma display device. The method according to claim 5 or 6, The plasma display panel further comprises a plurality of third electrodes paired with the plurality of first electrodes, respectively.