KR20050112458A - Method of fabricating semiconductor device - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device. In the method of manufacturing the semiconductor device, first and second interlayer insulating films having different etching rates are deposited on a semiconductor substrate having a lower active layer including a channel region. The first and second interlayer insulating layers are etched to form contact holes. A plug is formed in the contact hole. A layer of amorphous material is deposited on the entire surface of the resultant product in which the plug is formed. The second interlayer insulating layer at the lower interface of the amorphous material layer is removed. The amorphous material layer is crystallized to form an upper active layer. The portion from which the second interlayer insulating film is removed is filled with an insulating film. The insulating film is planarized.

Description

Method of manufacturing semiconductor device {Method of fabricating semiconductor device}

The present invention relates to a method for manufacturing a semiconductor device.

As the integration of semiconductor devices increases, various methods for maximizing device performance while reducing the size of individual devices have been proposed. Accordingly, the size of discrete devices such as MOS transistors has been proposed. Is shrinking. As a result, the channel length of the MOS transistor is reduced to cause a short channel effect.

Since the threshold voltage of the device is eventually reduced by the short channel effect, a method of doping a high concentration of impurities in a channel region is generally applied to prevent the threshold voltage from being lowered. However, when doping a high concentration of impurities in the channel region, the current resistance of the device is not only degraded due to the increase in channel resistance, but also leakage between the channel region and the source / drain due to the increase in the electric field between the channel region and the source / drain. The problem of increasing the current occurs.

As a method for solving the above problems caused by the improvement in the degree of integration of devices, a method of manufacturing a semiconductor device having a multi-channel structure has been applied.

The method of manufacturing a semiconductor device having a multi-channel structure is described in US Patent No. 6,429,484 entitled "Multiple active layer structure and a method of making such a structure." As described by Yu et al.

The method disclosed in US Pat. No. 6,429,484 proposes a structure in which a device is configured in a multilayer active layer on a silicon on insulator (SOI) substrate. More specifically, a single crystal lower active layer is formed on an SOI wafer. After forming an insulating layer filling the lower active layer, a contact hole is formed to expose the lower active layer. In addition, a plug is formed in the contact hole through selective epitaxy growth (SEG) on the single crystal of the lower active layer. Then, using the plug as a seed layer (Seed layer) to deposit an amorphous layer (Amorphous layer) on top and to form a top active layer by monocrystalline by a solid phase epitaxy (SPE) method. Alternatively, the upper active layer may be formed using a lateral overgrowth epitaxy (LOE) method.

However, when the contact hole is filled by applying the SEG method, crystal defects are easily generated, which causes crystal defects due to contact surface irregularities when forming the upper active layer using a subsequent SPE process. In order to prevent crystal defects due to such fine bending, a high temperature heat treatment process of about 800 ° C. may be applied. When the high temperature heat treatment process is performed, impurities of the source / drain junction diffuse into the channel region to cause the short channel effect once again. can do.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device manufacturing method capable of preventing crystal defects.

Another technical problem of the present invention for solving the above problems is to provide a method for manufacturing a semiconductor device that can prevent a short channel effect.

The present invention for achieving the above technical problem provides a method of manufacturing a semiconductor device. In the method of manufacturing the semiconductor device, first and second interlayer insulating films having different etching rates are deposited on a semiconductor substrate having a lower active layer including a channel region. The first and second interlayer insulating layers are etched to form contact holes. A plug is formed in the contact hole. A layer of amorphous material is deposited on the entire surface of the resultant product in which the plug is formed. The second interlayer insulating layer at the lower interface of the amorphous material layer is removed. The amorphous material layer is crystallized to form an upper active layer. A portion from which the second interlayer insulating film is removed is filled with an insulating film to planarize the insulating film. In addition, after the insulating layer is planarized, an isolation layer and a transistor may be formed in the upper active layer to have multiple channels.

The second interlayer insulating layer may be formed of a material having an etching rate higher than that of the first interlayer insulating layer. The second interlayer insulating layer may be removed by etching the second amorphous material and the second interlayer insulating layer to expose a portion of the first interlayer insulating layer, and then performing a wet etching process using the first interlayer insulating layer as an etch stop layer. The second interlayer insulating layer may be removed by etching a portion of the amorphous material layer to expose an upper portion of the second interlayer insulating layer, and then wet etching.

The plug may form a contact hole by etching the first and second interlayer insulating layers, form a spacer on a sidewall of the contact hole, fill the contact hole with an amorphous material, and planarize the exposed spacer, The spacer may be removed by wet etching so that the contact surface of the amorphous material is removed, and the amorphous material from which the contact surface is removed may be crystallized.

In addition, the spacer may be formed of a material having a higher etching rate than that of the first and second interlayer insulating layers so that the first and second interlayer insulating layers may serve as an etch stop layer when the spacers are removed.

In addition, the amorphous material crystallization process may be carried out at 500 ~ 750 ℃ as a solid phase epitaxy process, thereby preventing the diffusion of impurities in the lower junction region generated during the high temperature thermal process of more than 800 ℃. have.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, lengths, thicknesses, and the like of layers and regions may be exaggerated for convenience. Like numbers refer to like elements throughout.

1A to 1H are sequential process cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

First, referring to FIG. 1A, an isolation layer 102 is formed on a semiconductor substrate 100 to define a lower active region. The device isolation layer 102 is a conventional shallow trench isolation (STI) method, and after forming a trench having a predetermined depth in a semiconductor substrate, the trench is buried in an oxide film such as HDP or the like with good buried characteristics. It can form by planarization after that.

Channel ion implantation is performed by using an N-type or P-type dopant in the semiconductor substrate 100 having the lower active region defined by the device isolation layer 102. For example, the channel ion implantation may inject a P-type channel ion in the case of an N-MOS transistor. Alternatively, in the case of a P-MOS transistor, an N-type channel ion may be implanted. In this case, the channel ion implantation process may be performed before the device isolation layer 102 is formed.

The gate insulating layer 104, the first gate conductive layer 106, the second gate conductive layer 108, and the capping layer 110 are sequentially formed on the semiconductor substrate 100 subjected to the channel ion implantation. The gate insulating layer 104 may be formed using thermal oxidation or chemical vapor deposition. The first gate conductive layer 106 may be formed of polysilicon, and the second gate conductive layer 108 may be formed of a metal silicide layer such as tungsten silicide. The capping film 110 may be formed of a nitride film.

Subsequently, a photoresist pattern (not shown) is formed in the same size as the gate pattern to be formed on the capping layer 110, and the capping layer 110 and the first layer are formed using the photoresist pattern as an etching mask. The gate pattern 112 is formed by anisotropically etching the two-gate conductive layer 108, the first gate conductive layer 106, and the gate oxide layer 104.

Referring to FIG. 1B, a low concentration impurity region 118a is formed by performing low concentration ion implantation on the substrate 100 using the gate pattern 112 and the device isolation layer as an ion implantation mask. Then, a buffer oxide film 114 is formed on both sidewalls of the gate pattern 112 and an insulating material to be used as a spacer is deposited. The gate spacer 116 is formed on the sidewalls of the gate pattern 112 by performing a dry etching process on the insulating material.

The high concentration impurity region 118b is formed by implanting high concentration ions into the substrate 100 using the gate pattern 112, the gate spacer 116, and the device isolation layer 102 using an ion implantation mask. The low concentration impurity region 118a and the high concentration impurity region 118b become source / drain 118 regions of the transistor. As a result, a transistor having a channel region including the gate pattern 112 and the source / drain 118 is formed.

Referring to FIG. 1C, an etch stop layer 120 is formed on an entire surface of the semiconductor substrate 100 on which the transistor is formed. An interlayer insulating layer 122 is formed on the entire surface of the resultant product on which the etch stop layer 120 is formed. In this case, the interlayer insulating layer 122 may be formed as a double structure of the first interlayer insulating layer 122a and the second interlayer insulating layer 122b having different etching rates with respect to wet etching. For example, the first interlayer insulating film 122a may be formed of an oxide film and the second interlayer insulating film 122b may be formed of a nitride film, but the first interlayer insulating film 122a may be formed by etching the second interlayer insulating film 122b in a subsequent process. The etch stop layer may be formed of a material having a lower etch rate than that of the second interlayer insulating layer. Next, the contact hole 124 is formed to expose the source / drain regions 118 formed in the semiconductor substrate 100. The contact hole 124 may be formed using a self-aligned contact technique.

Referring to FIG. 1D, sidewall spacers 126 are formed on the sidewalls of the contact hole 124. The sidewall spacer 126 may be formed of an insulating material having a higher etching rate than the interlayer insulating layer 122. In this case, the insulating material used may be any one of an aluminum oxide film (Al ₂ O ₃ ) or a silicon oxide film (SiO ₂ ) formed by atomic layer deposition (ALD).

Referring to FIG. 1E, the first amorphous silicon is deposited to completely fill the contact hole 124. The amorphous plug 128 is formed by planarization by a chemical mechanical polishing process using the second interlayer insulating film 122b as a polishing stop film. In this case, the amorphous plug 128 may be one selected from a group of Si, SiC, and SiGe.

Referring to FIG. 1F, the contact surface of the sidewalls of the amorphous plug 128 may be removed by performing a wet etching process to remove the sidewall spacers 126. The contact surface of the amorphous plug sidewall is not affected by fine bending and the like, so that crystal defects do not occur in a subsequent crystallization process. In this case, since the sidewall spacer 126 has a higher etching rate than the interlayer insulating layer 124, the interlayer insulating layer 124 may serve as an etch stop layer when the sidewall spacer is removed.

By performing a solid phase epitaxy (SPE) process on the resultant from which the contact surface of the amorphous plug 128 is removed, the amorphous plug 128 is crystallized to form the single crystal plug 130. In this case, the solid phase epitaxy process may be performed at a temperature of 500 to 750 ° C. lower than 800 ° C. to prevent diffusion of the dopant injected into the source / drain 118. This can solve the problem of reducing the channel length.

Referring to FIG. 1G, a second amorphous silicon 132 is deposited on the entire surface of the resultant single crystal plug 130.

Referring to FIG. 1H, a contact hole 134 is formed between gate electrodes by a selective etching process for the second amorphous silicon layer 132 and the second interlayer insulating layer 122b. In this case, the contact hole 134 may be formed by etching only the second amorphous silicon layer 132.

Referring to FIG. 1I, the contact surface of the second amorphous silicon layer 132 is removed by wet etching the second interlayer insulating layer 122b through the formed contact hole 134. In this case, the second interlayer insulating layer 122b is formed of a material having a higher etching rate than that of the first interlayer insulating layer 124a. In the wet etching process, the first interlayer insulating layer 124a serves as an etch stop layer. In the solid state epitaxial process on the second amorphous silicon layer 132, the second amorphous silicon layer 132 is crystallized to form an upper active layer 136. The solid phase epitaxy process may be performed at 500 to 750 ° C. to prevent diffusion of impurities in the lower source / drain 118 region to prevent short channel effects.

Referring to FIG. 1J, a portion from which the second interlayer insulating film 122b is removed is filled with an insulating film 138 such as an oxide film. Then, the insulating film 138 is planarized by a chemical mechanical polishing process. An isolation layer 140 is formed on the upper active layer 136 to separate the active region and the field region. The surface of the upper active layer 136 is exposed by performing a wet etching process on the resultant device on which the device isolation layer 140 is formed.

Referring to FIG. 1K, a gate pattern 142 is formed on the upper active layer 136. The low concentration impurity region 144 is formed using the gate pattern 142 and the device isolation layer 140 using an ion implantation mask. A buffer oxide layer 146 and a spacer 148 are formed on sidewalls of the gate pattern 142. The source / drain regions including the low concentration and high concentration impurity regions in the upper active layer 136 are formed by forming the high concentration impurity region 150 using the gate pattern 142, the device isolation layer 140, and the spacer 148 as an ion implantation mask. 152). Accordingly, a transistor having a channel region including the gate pattern 142 and the source / drain 152 is formed to form a semiconductor device having a multi-channel structure.

As described above, according to the method of manufacturing a semiconductor device according to the present invention, the crystallization process is performed after removing the contact surface of the amorphous material deposited for use as the contact plug and the upper active layer, without crystal defects due to fine bending at the contact surface. Can be formed.

According to the embodiment of the present invention as described above, by removing the contact surface of the amorphous material and performing a crystallization process by the solid state epitaxy process it is possible to improve the reliability of the device so as not to be affected by fine defects of the contact surface.

In addition, by performing the crystallization process at 800 ° C. or lower, the diffusion of impurities in the source / drain junction region can be prevented and the short channel effect can be prevented.

1A to 1K are sequential process cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Explanation of reference numerals for the main parts of the drawing

100 substrate 112 gate electrodes

122a: first interlayer insulating film 122b: second interlayer insulating film

124: contact hole 126: side wall spacer

128: first amorphous layer 130: single crystal plug

132: second amorphous layer 136: upper active layer

Claims (11)

Depositing first and second interlayer insulating films having different etching rates on a semiconductor substrate having a lower active layer including a channel region, Etching the first and second interlayer insulating films to form a contact hole, A plug is formed in the contact hole, Depositing an amorphous material layer on the entire surface of the resultant product in which the plug is formed, Removing the second interlayer insulating film at an interface below the amorphous material layer, Crystallizing the amorphous material layer to form an upper active layer, A portion from which the second interlayer insulating film is removed is filled with an insulating film, And planarizing said insulating film. The method of claim 1, The amorphous material layer is a semiconductor device manufacturing method, characterized in that any one of Si, SiC, SiGe. The method of claim 1, The amorphous material layer crystallization is a semiconductor device manufacturing method, characterized in that to proceed in the solid state epitaxy process. The method of claim 1, The amorphous material layer crystallization is carried out at 500 ~ 750 ℃ manufacturing method of a semiconductor device. The method of claim 1, The second interlayer insulating film is a method of manufacturing a semiconductor device, characterized in that the etching rate is higher than the first interlayer insulating film. The method of claim 1, The second interlayer insulating film removing process And partially etching the amorphous material layer, and then removing the exposed second interlayer insulating layer by wet etching. The method of claim 1, The second interlayer insulating film removing process And etching the portion of the amorphous material layer and the second interlayer insulating film, and then removing the second interlayer insulating film by wet etching. The method of claim 1, And forming an isolation layer and a transistor in the upper active layer after the insulating film is planarized. The method of claim 1, The plug formation Etching the first and second interlayer insulating films to form a contact hole, A spacer is formed on the sidewalls of the contact hole, Filling the contact hole with an amorphous material, Planarize to expose the spacers, Removing the spacers by wet etching to remove the contact surface of the amorphous material, And crystallizing the amorphous material from which the contact surface has been removed. The method of claim 9, The spacer is a method of manufacturing a semiconductor device, characterized in that the material has a higher etching rate than the first and second interlayer insulating film. The method of claim 9, The spacer is manufactured by a silicon oxide film or an aluminum oxide film.