KR20050098054A - The circuit of preventing simultaneous switching output - Google Patents

Abstract

A simultaneous transition output prevention circuit is disclosed. The simultaneous transition output prevention circuit according to the present invention receives a plurality of switching signals and a system clock applied to the output terminal of the semiconductor integrated circuit, a flip-flop unit for outputting the switching signal in synchronization with the system clock, a plurality of inputs from the flip-flop unit A level for generating and outputting a plurality of delay path selection signals for detecting a transition point of the switching signal in real time and for delaying a switching signal at which a transition occurs simultaneously with a predetermined reference signal from the transition point of the predetermined reference signal for a predetermined time. The detection unit delays the plurality of switching signals received from the flip-flop unit by a predetermined time in response to the control of the plurality of delay path selection signals to generate a plurality of delay switching signals having transition points different from the predetermined reference switching signals. A signal delay section for outputting, and a signal delay section and a flip-flop section And a multiplexer that receives a plurality of delay switching signals and a plurality of switching signals, respectively, and selects any one of a delay switching signal and a switching signal to output a plurality of simultaneous switching prevention signals to prevent simultaneous transitions. Characterized in that.

Description

The circuit of preventing simultaneous switching output

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simultaneous switching output (SSO) prevention circuit, and in particular, a simultaneous switching output prevention circuit for preventing simultaneous transition output occurring at the output stage of a semiconductor integrated circuit by delaying a switching signal that is simultaneously transitioned by a predetermined time. It is about.

FIG. 1 is a block diagram showing the structure of a conventional semiconductor integrated circuit output stage, and FIG. 2 is a waveform diagram of the main part shown in FIG. Referring to FIG. 1, output signal sources S1 to Sn applied to a conventional semiconductor integrated circuit output terminal are applied to a flip-flop unit 1 together with a system clock CLK. Referring to FIG. 2, the respective output signal sources S1 to Sn are synchronized with the time point A of the system clock CLK, and then output from the flip-flop unit 1 and input to the drive pins P1 to Pn. do. At this time, there is an output signal that transitions from "1" to "0" or from "0" to "1" at the same time with respect to the predetermined output signal.

Such simultaneous transition output signals cause a large amount of current to flow into the ground or power as a plurality of pins present in the semiconductor integrated circuit chip are simultaneously switched. This phenomenon generates Simultaneous Switch Noise (SSN), which is a very important factor in the design and processing speed of integrated circuits, and is known as ground bounce and clock waveforms. Clock waveform degradation and the like.

Such simultaneous transition noise causes a problem of signal distortion or malfunction. In addition, as the size and complexity of semiconductor integrated circuits increase, the number of simultaneous transition outputs (SSOs) increases, and thus the chip production price increases because the chips of the semiconductor integrated circuits must include a plurality of power pins. There is a problem of increasing power.

Accordingly, an object of the present invention is to prevent the occurrence of the simultaneous transition output at the output stage of the semiconductor integrated circuit to improve the performance of the semiconductor integrated circuit, reduce the power consumption, the simultaneous transition output that can lower the production cost of the semiconductor integrated circuit chip To provide a prevention circuit.

Simultaneous transition output prevention circuit according to the present invention for achieving the above object receives a plurality of switching signals and a system clock applied to the output terminal of the semiconductor integrated circuit, the flip-flop unit for flipping and outputting the switching signal to the system clock, flip A plurality of delay path selection signals for detecting a transition point of a plurality of switching signals received from the flop in real time and delaying a switching signal at which a transition occurs simultaneously with a predetermined reference signal from a transition point of the predetermined reference signal for a predetermined time. A level detector for generating and outputting a plurality of delay paths, the plurality of switching signals received from the flip-flop unit by a predetermined time, respectively, by a predetermined time in response to the control of the plurality of delay path selection signals. A signal delay unit for generating and outputting a delay switching signal; After receiving a plurality of delay switching signals and a plurality of switching signals from the delay unit and the flip-flop unit, respectively, one of the delay switching signal and the switching signal is selected to prevent simultaneous transitions, and thus, the plurality of simultaneous switching prevention signals. It is preferable to include a multiplexer for outputting.

Here, it is preferable that the level detector generates a multiplexer control signal for controlling the multiplexer to select and output a plurality of signals that do not simultaneously transition, and input the multiplexer control signal to the multiplexer.

The signal delay unit preferably includes a plurality of buffers.

Here, the number of simultaneous transition prevention signals output from the multiplexer is preferably 1/2 of the total number of signals input to the multiplexer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing the configuration of a simultaneous transition output (SSO) prevention circuit according to the present invention, Figure 4 is a waveform diagram of the main part shown in FIG.

Referring to FIG. 3, a simultaneous switching output prevention circuit according to the present invention includes a flip-flop unit 10, a level detector 20, a signal delay unit 30, a multiplexer (hereinafter, “MUX”). 40).

The flip-flop unit 10 includes a plurality of flip-flops F1 to Fn connected in parallel, and each flip-flop F1 to Fn includes a switching signal S1 to Sn applied to an output terminal of a semiconductor integrated circuit. After synchronization to a predetermined rising edge of the clock CLK, the signal is output to the level detector 20, the signal delay unit 30, and the multiplexer 40, respectively. In this case, the plurality of switching signals S1 to Sn are switched from "1" to "0" or "0" to "1" at the same time point or different time points, respectively.

The level detector 20 is a real-time when the potential of the plurality of switching signals (S1 ~ Sn) input from the flip-flop unit 10 is switched from "1" to "0" or "0" to "1". A plurality of switching signals received from the flip-flop unit 10 are sensed and input to the delay signal unit 30.

At this time, when at least one switching signal is simultaneously transitioned based on the predetermined switching signal, the level detector 20 transitions a signal (hereinafter, referred to as a "simultaneous switching signal") that is simultaneously switched with the predetermined reference signal. A delay path selection signal for delaying the viewpoint by a predetermined time is generated and output to the switching signal delay unit 30.

In addition, the level detector 20 generates a MUX control signal for allowing the MUX 40 to recognize which signal a simultaneous switching has occurred based on a predetermined signal at a predetermined time point and outputs it to the MUX 40. do.

The signal delay unit 30 has a plurality of paths having different delay times. The signal delay unit 30 connects the switching signals input from the flip-flop unit 10 to paths having different delay times in response to the control of the plurality of delay path selection signals input from the level detector 20. By delaying each other by a predetermined time, a plurality of delayed switching signals having different switching points are generated and output to the MUX 40.

The MUX 40 selects one of a switching signal and a delay switching signal respectively input from the flip-flop unit 10 and the signal delay unit 30 in response to the MUX control signal input from the level detector 20. Output As a result, the number of signals output from the MUX 40 is 1/2 of the number of signals input to the MUX 40. Here, the plurality of switching signals input from the flip-flop unit 10 and the plurality of delay switching signals input from the signal delay unit 30 have a one-to-one correspondence.

Meanwhile, the signals selected and output by the MUX 40 are as follows. That is, the MUX 40 outputs the delayed switching signal received from the signal delay unit 10 when the received switching signal simultaneously transitions with the predetermined switching signal as a reference. On the other hand, the MUX 40 outputs the switching signal input from the flip-flop unit 10 as it is when the input switching signal does not transition simultaneously with the predetermined switching signal as a reference.

Therefore, as shown in FIG. 4, the signals output from the MUX 40 and input to the drive pins P1 to Pn are the simultaneous transition prevention signals that do not perform simultaneous transitions, respectively. The generation of simultaneous transition output at the output stage of the integrated circuit is prevented. On the other hand, the plurality of switching signals and the delay switching signal output from the MUX 40 is input to the external device through the plurality of drive pins (P1 ~ P2).

As described above, according to the simultaneous transition output prevention circuit according to the present invention, the simultaneous transition output can be reduced or prevented to reduce the power consumption of the semiconductor integrated circuit. Simultaneous transition can reduce or prevent the generation of noise. Accordingly, there is an effect that can prevent the problem of signal distortion or malfunction.

In addition, according to the simultaneous transition output prevention circuit according to the present invention, the number of power supply pins of the semiconductor integrated circuit chip is reduced because the number of simultaneous transition output is prevented or reduced, thereby reducing the production cost of the semiconductor integrated circuit chip.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the present invention is not limited to the specific embodiments of the present invention without departing from the spirit of the present invention as claimed in the claims. Anyone skilled in the art can make various modifications, as well as such modifications that fall within the scope of the claims.

1 is a block diagram showing the configuration of a conventional semiconductor integrated circuit output stage;

2 is a waveform diagram of the main part shown in FIG.

3 is a block diagram showing the configuration of a simultaneous transition output (SSO) prevention circuit according to the present invention; and

4 is a waveform diagram of the main part shown in FIG.

Brief description of the main parts of the drawing

10: flip-flop portion 20: level detector

30: signal delay unit 40: multiplexer

P1 ~ Pn: Drive Pins F1 ~ Fn: Flip-Flops

S1-Sn: Switching signal CLK: System clock

Claims (4)

A flip-flop unit which receives a plurality of switching signals and a system clock applied to an output terminal of a semiconductor integrated circuit, and outputs the switching signals in synchronization with the system clock; A plurality of delays for detecting a time of transition of the plurality of switching signals received from the flip-flop unit in real time and delaying a switching signal at which a transition occurs simultaneously with a predetermined reference signal from a transition time of the predetermined reference signal by a predetermined time. A level detector for generating and outputting a path selection signal; In response to control of the plurality of delay path selection signals, the plurality of switching signals received from the flip-flop unit are delayed for a predetermined time, thereby generating a plurality of delay switching signals having transition points different from the predetermined reference switching signal. An output signal delay unit; And After receiving a plurality of delay switching signals and a plurality of switching signals from the signal delay unit and the flip-flop unit, respectively, any one of the delay switching signal and the switching signal is selected to prevent simultaneous transition. And a multiplexer for outputting a simultaneous switching prevention signal of the simultaneous transition output prevention circuit. The method of claim 1, wherein the level detector, And generating a multiplexer control signal for controlling the multiplexer to select and output a plurality of signals which are not simultaneously transitioned, and inputting the multiplexer control signal to the multiplexer. The method of claim 1, wherein the signal delay unit, A simultaneous transition output prevention circuit comprising a plurality of buffers. The method of claim 1, The number of simultaneous transition prevention signals output from the multiplexer is And a half of the total number of signals input to the multiplexer.