KR20050078259A - Multiple-layer phase change resistor cell and non-volatile memory device using the same - Google Patents

Abstract

The present invention relates to a multi-layer phase change resistance cell and a nonvolatile memory device using the same, and discloses a technique for reducing the number of cell arrays by forming a multi-layer cell array including a resistive memory device and a series PN diode chain. . In the present invention, a cross-point cell is disposed between a word line and a bit line by disposing a unit phase change resistance cell including a nonvolatile resistance memory device whose resistance state changes according to a current value and a series diode switch that does not require a separate gate control signal. The array is implemented, and the cross-point cell array is configured in multiple layers to reduce the overall chip size.

Description

Multi-layer phase change resistor cell and non-volatile memory device using the same}

The present invention relates to a multi-layer phase change resistance cell and a nonvolatile memory device using the same, and to reduce the overall size of the memory by configuring a multi-layer cell array including a resistor diode and a series diode cell that does not require a separate gate control signal It's a technology that makes it possible.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM) and preserve data even when the power is turned off. Has the property of being.

1A to 1D are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the state of electrical conduction according to the change in resistance. Here, AglnSbTe is mainly used as the material of the phase change layer 2.

That is, as shown in FIG. 1C, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 is in a crystalline phase to become a material having a low resistance state.

On the other hand, as shown in FIG. 1D, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, if the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

Meanwhile, a conventional memory device includes one switching element and one memory element for storing data. Here, the switching element of the conventional memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

However, when the cell array is implemented using the NMOS transistor as a switching device, there is a problem in that the overall chip size is increased. Accordingly, as described above, a cross point cell is implemented by using a phase change resistance element having a nonvolatile characteristic and a series diode switch that does not require a separate gate control signal, and the cross point cell is formed in a multilayer to form an overall chip size. There is a need for the present invention that can reduce the number.

The present invention has been made to solve the above problems and has the following object.

First, the purpose is to reduce the size of the array by configuring a series diode switch in a multi-layer using an interlayer insulating film.

Second, the purpose of the present invention is to reduce the overall size of the nonvolatile memory by implementing a cross point cell using a series diode switch that does not require a phase change resistor and a separate gate control signal.

Third, an object of the present invention is to efficiently drive read / write operations in a cell array using the above-described phase change resistance device and a series diode switch, thereby improving operating characteristics of a memory cell.

A multi-layer phase change resistance cell of the present invention for achieving the above object, a series diode having an insulating layer formed on the substrate and at least two or more diode elements consisting of a silicon layer on top of the insulating layer connected in series switch; A phase change resistance device including a top electrode, a phase change layer, and a bottom electrode, and configured to sense a crystallization state that changes according to a magnitude of a current applied from a word line and to store data corresponding to a change in resistance; A bit line connected to a node at both ends of the series diode switch through a bit line contact node; A contact node connecting a common node to which at least two diode elements are connected and the bottom electrode; And a unit phase change resistance cell having a word line formed on the top electrode, wherein a plurality of unit phase change resistance cells are provided in a row and column direction, and the plurality of unit phase change resistance cells are stacked in a multilayer structure. It is characterized by being separated from each other by an insulating layer.

A nonvolatile memory device using a multilayer phase change resistance cell of the present invention includes a plurality of multilayer phase change layers including a plurality of multilayer phase change resistance cells arranged in a row and column direction and stacked in a multilayer structure and separated from each other by an insulating layer. Resistive cell arrays; A plurality of word line drivers selectively driving word lines of the plurality of multi-layer phase change resistance cell arrays; And a plurality of sense amplifiers configured to sense and amplify data applied from the plurality of multilayer phase change resistance cell arrays, wherein each of the plurality of multilayer phase change resistance cells has a crystallization state that changes according to a magnitude of current applied from a word line. A phase change resistance element that senses and stores data corresponding to a change in resistance; And a series diode switch having at least two diode elements connected in series to each other and having a common connection node connected to one end of the phase change resistance element, wherein the series diode switches are selectively switched according to the magnitude of the voltage applied to the word line and the bit line. It is characterized by.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a unit cell configuration diagram of a multilayer phase change resistance cell according to the present invention.

The unit phase change resistor (PCR) cell includes one phase change resistor element PCR and one series diode switch 10. Here, the series diode switch 10 includes a PNPN diode switch 11 and a PN diode switch 12. The PNPN diode switch 11 and the PN diode switch 12 are connected in parallel between the bottom electrode of the phase change resistance element PCR and the bit line BL.

The PNPN diode switch 11 is connected in the reverse direction between one electrode of the phase change resistance element PCR and the bit line BL, and the PN diode switch 12 is connected in the forward direction between one electrode of the phase change resistance element PCR and the bit line BL. do. The other electrode of the phase change resistance element PCR is connected to the word line WL.

3 is a unit cell cross-sectional configuration diagram of the multilayer phase change resistance cell of FIG. 2.

The series diode switch 10 includes an insulating layer 31 formed on the silicon substrate 30 and a silicon layer 32 on the insulating layer 31 to form a silicon on insulator (SOI) structure. Here, an insulating layer 31 made of SiO 2 is stacked on the silicon substrate 30, and a silicon layer 32 is formed on the insulating layer 31. The silicon layer 32 is formed by stacking a PNPN diode switch 11 and a PN diode switch 12 made of growth silicon or polysilicon and connected in series.

The PNPN diode switch 11 alternately connects the P-type region and the N-type region in series, and the PN diode switch 12 connects the P-type region and the N-type region in series so that the P-type region is the PNPN diode switch 11. It is formed adjacent to the N-type region of.

The bit line BL is formed on the N-type region of the PN diode switch 12 and the P-type region of the PNPN diode switch 11 through the bitline contact node BLCN. In addition, the P-type region of the PN diode switch 12 and the N-type region of the PNPN diode switch 11 are connected to the bottom electrode 22 of the phase change resistance element PCR through the common contact node CN.

Here, the phase change resistance element PCR includes a top electrode 20, a phase change layer (PCM) 21, and a bottom electrode 22. The top electrode 20 of the phase change resistance element PCR is connected to the word line WL.

4 is a plan view of the series diode switch 10 of FIG. 3.

In the series diode switch 10, the PNPN diode switch 11 and the PN diode switch 12 made of the silicon layer 32 are continuously connected in series chain form. That is, one unit phase change resistance cell includes a PN diode switch 12 and a PNPN diode switch 11 connected in series. The PN diode switch 12 and the PNPN diode switch 11 are connected in series with each other in the unit phase change resistance cell adjacent to the same direction as one unit phase change resistance cell.

In addition, the series diode switch 10 is arranged in a plurality of layers with the insulating layer 31 interposed therebetween, and each of the upper series diode switch 10 and the lower series diode switch 10 is separated through the insulating layer 31. It is.

Accordingly, one PN diode switch 12 and one PNPN diode switch 11 are sequentially selected among the diode elements connected in series to form one phase change resistance cell region.

5 is a plan view of the multilayer phase change resistance cell of FIG. 2.

The silicon layer 32 made of growth silicon or polysilicon forms a PNPN diode switch 11 and a PN diode switch 12 connected in series. Each silicon layer 32 is insulated from the upper and lower portions through the insulating isolation layer 31. In the series diode switch 10, the P-type region of the PN diode switch 12 and the N-type region of the PNPN diode switch 11 are formed adjacent to each other so as to be commonly connected to the contact node CN of the phase change resistance element PCR.

In addition, the N-type region of the PN diode switch 12 and the P-type region of the PNPN diode switch 11 are connected to the bitline BL through the bitline contact node BLCN. The bitline contact node BLCN is commonly connected with the bitline contact node BLCN of the neighboring phase change resistance cell. That is, the same bit line contact node BLCN is commonly connected to the P-type region of the PNPN diode switch 11 and the N-type region of the PN diode switch 12 of the neighboring cell.

The word line WL is formed on the phase change resistance element PCR.

6 and 7 are cross-sectional views of the multilayer phase change resistance cell according to the present invention.

In the multilayer phase change resistance cell, a unit phase change resistance cell as shown in FIG. 3 is formed as a first layer cell array, and a second layer cell array is stacked on top of the first layer cell array. Here, an insulating isolation layer 31 is deposited on the phase change resistance element PCR formed on the first layer cell array to insulate the first layer cell array and the second layer cell array.

In addition, a series diode switch 10 made of polysilicon or growth silicon is deposited on the insulating isolation layer 31 of the second layer cell array. Accordingly, the series diode switch 10 formed in the first layer cell array and the series diode switch 10 formed in the second layer cell array are separated from each other by the insulating isolation layer 31.

The embodiment of FIG. 7 shows that the unit phase change resistance cell as shown in FIG. 3 may be composed of n multilayer cell arrays.

FIG. 8 illustrates a cross-sectional structure of a word line array of a multilayer phase change resistance cell when the series diode switch 10 having the structure as shown in FIG. 4 is cut in the direction A-A 'based on the insulating layer 31.

A plurality of word line arrays are arranged in the row direction and have a structure in which a plurality of word lines WL are sequentially stacked on top of the first layer word line WL. The word lines WL of each layer are separated from each other by the insulating layer 31.

FIG. 9 illustrates a cross-sectional structure of a bit line array of a multilayer phase change resistance cell when the series diode switch 10 having the structure shown in FIG. 4 is cut in the direction A-A 'based on the insulating layer 31.

A plurality of bit line arrays are arranged in the row direction and have a structure in which a plurality of bit line BLs of a plurality of layers are sequentially stacked on the first layer bit line BL. The bit lines BL of each layer are separated from each other by the insulating layer 31.

FIG. 10 is a diagram for describing an operation of the series diode switch 10 of FIG. 2.

When the applied voltage of the bit line BL increases in the positive direction based on the phase change resistance element PCR, the series diode switch 10 is kept off at the operating voltage Vo due to the operating characteristics of the PNPN diode switch 11. No current flows

Subsequently, when the applied voltage of the bit line BL is further increased to reach the threshold voltage Vc, the PNPN diode switch 11 is turned on and the series diode switch 10 is turned on according to the forward operation characteristic of the diode, thereby rapidly increasing the current. . At this time, the value of the current I consumed when the applied voltage of the bit line BL is greater than or equal to the threshold voltage Vc is due to the value of a resistor (not shown) connected to the bit line BL and serving as a load.

After the PNPN diode switch 11 is turned on, even a small voltage Vs is applied to the bit line BL, so that a large amount of current can flow. At this time, the PN diode switch 10 is maintained in the off state by the reverse operating characteristics.

On the other hand, when the applied voltage of the bit line BL increases in the negative direction based on the phase change resistance element PCR, that is, when a constant voltage is applied to the word line WL, the forward operation characteristic of the PN diode switch 10 is reduced. As a result, the series diode switch 10 is turned on so that current flows at any operating voltage. At this time, the PNPN diode switch 11 maintains the off state due to the reverse operation characteristic.

11 is a configuration diagram of a nonvolatile memory device using a multilayer phase change resistance cell according to the present invention.

The present invention provides a plurality of multilayer PCR cell arrays 40, a plurality of word line drivers 50, a plurality of sense amplifiers 60, a data bus 70, a main amplifier 80, a data buffer 90 and input / output. It has an output port 100.

Each multilayer PCR cell array 40 includes a plurality of unit phase change resistance cells having a structure as shown in FIG. 2 in a row and column direction. The plurality of word lines WLs arranged in the row direction are connected to the word line driver 50. The plurality of bit lines BL arranged in the column direction are connected to the sense amplifier 60.

Here, one multilayer PCR cell array 40 is connected in correspondence with one word line driver 50 and one sense amplifier 60.

The plurality of sense amplifiers 60 share one data bus 70. The data bus 70 is connected to the main amplifier 80, and the main amplifier 80 amplifies data applied from each sense amplifier 60 through the data bus 70.

The data buffer 90 buffers and outputs amplified data applied from the main amplifier 80. The input / output port 100 outputs output data applied from the data buffer 90 to the outside, or applies input data applied from the outside to the data buffer 90.

12 is a layout diagram of the multilayer PCR cell array 40 of FIG.

In the multilayer PCR cell array 40, a plurality of word lines WL are arranged in a row direction, and a plurality of bit lines BL are arranged in a column direction, respectively. In addition, since the unit cell C is positioned only in an area where the word line WL and the bit line BL cross each other, a cross point cell that does not require an additional area may be implemented.

Here, the cross point cell does not include an NMOS transistor device using a separate word line WL gate control signal. In addition, the structure of the phase change resistance device PCR using the series diode switch 10 having two connection electrode nodes can be positioned directly at the intersection of the bit line BL and the word line WL.

FIG. 13 is a detailed circuit diagram of the multilayer PCR cell array 40 of FIG.

In the multilayer PCR cell array 40, a plurality of word lines WL <0> to WL <n> are arranged in a row direction, and a plurality of bit lines BL <0> to BL <m> are arranged in a column direction, respectively. The unit cell C is located only in an area where the word line WL and the bit line BL cross each other. Here, one unit cell C includes a phase change resistance element PCR and a series diode switch 10.

A plurality of sense amplifiers 60 are connected to each bit line BL in a one-to-one correspondence. Each sense amplifier 60 amplifies the result of comparing the voltage applied from the bit line BL with a predetermined reference voltage REF at the time of activation of the sense amplifier enable signal SEN.

In addition, the bit line pull-down element N1 is connected to the bit line BL <0>, and the bit line pull-down element N2 is connected to the bit line BL <m>. Accordingly, when the bit line pull-down signal BLPD is activated, the ground voltage is applied to the bit line BL to pull down the bit line BL to the ground level.

This multi-layer PCR cell array 40 allows each phase change resistance element PCR to store one data.

14 is a timing diagram of an operation in a read mode of a nonvolatile memory device using a multilayer phase change resistance cell according to the present invention.

First, in the t0 period, the bit line pull-down signal BLPD is activated to turn on the NMOS transistors N1 and N2, thereby precharging the bit line BL to the ground level.

Subsequently, when the word line WL transitions high when the t1 section enters and a constant voltage is applied to the word line WL, the PN diode 12 of the series diode switch 10 is turned on. Accordingly, data of the multilayer PCR cell is transferred to the bitline BL. At this time, the bit line pull-down signal BLPD transitions to low.

Next, when the sense amplifier enable signal SEN transitions high in the period t2, the sense amplifier 60 operates to amplify the data carried on the bit line BL. When the column select signal CS transitions high, the column select switching unit (not shown) is turned on to output data D and / D on the bit line BL to the data bus 70 to read data stored in the PCR cell C. It becomes possible.

Subsequently, if the word line WL transitions low during the entry of the t3 section, the connection with the bit line BL is blocked to complete the read operation. At this time, both the PN diode switch 12 and the PNPN diode switch 11 of the series diode switch 10 maintain the turn-off state.

15 is a timing diagram of an operation in a write mode of a nonvolatile memory device using a multilayer phase change resistance cell according to the present invention.

In the write mode of the present invention, the sense amplifier enable signal SEN is kept low.

First, in the t0 period, the bit line pull-down signal BLPD is activated to turn on the NMOS transistors N1 and N2, thereby precharging the bit line BL to the ground level.

Thereafter, the bit line pull-down signal BLPD transitions low when the t1 period is entered. When the column select signal CS transitions high, the column select switching unit (not shown) is turned on so that new data D // D to be written through the data bus 70 is input to the bit line BL. Here, it is assumed that data applied to the bit line BL in the write mode is "high" or "low".

In this state, the voltage of the word line WL transitions to a negative voltage that is less than or equal to the threshold voltage Vc. That is, the difference between the low voltage level of the bit line BL and the negative voltage level of the word line WL does not reach the state of the threshold voltage Vc for turning on the PNPN diode switch 11 of the series diode switch 10.

However, according to the difference between the high amplification voltage of the bit line BL and the negative voltage of the word line WL, a voltage higher than or equal to the threshold voltage Vc for turning on the PNPN diode switch 11 is applied. As a result, the PNPN diode switch 11 is turned on so that data can be written to the phase change resistance element PCR.

At this time, after the PNPN diode switch 11 is turned on, as shown in the operating characteristic of FIG. 10, even if a small voltage Vs is applied to the phase change resistance element PCR, a large amount of current I can flow. Therefore, the current can flow sufficiently even if the voltage of the word line WL rises from the negative voltage to the low state again after the period t1.

Thereafter, the voltage drop level is different depending on the pattern of data applied to the bit line BL during the period t2 to tn.

That is, when the voltage level is applied to the bit line BL, the voltage level of the bit line BL is gradually decreased during the period t2 to tn. On the other hand, when the voltage level having the value of the data row is applied to the bit line BL, the voltage level of the bit line BL is continuously controlled during the t2 to tn period.

That is, as shown in FIG. 16, in order to keep the melting temperature of the phase change resistance element PCR that maintains the crystallization state at a low temperature at a low temperature when the data loaded on the bit line BL is "high". The level of the voltage applied to the voltage is dropped step by step. Accordingly, in the t1 section, the temperature characteristic of the data "high" gradually decreases after showing the peak value and shows low resistance characteristics.

Here, when the level of the voltage applied to the bit line BL is kept constant without dropping in voltage, the temperature of the phase change resistance element PCR is raised to change the phase change resistance element PCR in the crystallization state into an amorphous state. Accordingly, in the present invention, in order to maintain the crystallization temperature, the voltage level applied to the bit line BL is gradually dropped.

On the other hand, when the data loaded on the bit line BL is " low ", the level of the voltage applied to the bit line BL is kept constant in order to increase the melting temperature of the phase change resistance element PCR that maintains the amorphous state. That is, the higher the melting temperature, the higher the resistance characteristics and the characteristics of the phase change resistance element PCR in the amorphous state is improved. As a result, when a constant voltage is applied to the bit line BL, the temperature is increased to continuously maintain the amorphous state.

In the present invention, since data is stored in a phase change resistance device PCR having a nonvolatile characteristic, an operation process for restoring is unnecessary.

As described above, the present invention provides the following effects.

First, by constructing a series diode switch in multiple layers using an interlayer insulating film, the number of memory elements per unit area is increased by a multiple of the number of cell array layers so that the size of the array can be reduced without additional layout expansion.

Second, the multi-point cell can be implemented in multiple layers using a series diode switch that does not require a phase change resistor and a separate gate control signal, thereby reducing the overall size of the nonvolatile memory.

Third, the read / write operation can be efficiently driven in the cell array using the above-described phase change resistance element and the series diode switch to improve the operating characteristics of the memory cell.

1A to 1D are diagrams for explaining a conventional phase change resistance element.

2 is a unit cell configuration diagram of a multilayer phase change resistance cell according to the present invention;

3 is a unit cell cross-sectional view of the multilayer phase change resistance cell of FIG. 2.

4 is a plan view of the series diode switch of FIG.

5 is a plan view of the multilayer phase change resistance cell of FIG.

6 and 7 are cross-sectional views of a multilayer phase change resistance cell according to the present invention.

8 is a cross-sectional view of the wordline array of the multilayer phase change resistance cell of FIG.

9 is a cross-sectional view of the bit line array of the multilayer phase change resistance cell of FIG.

10 is a view for explaining the operation of the series diode switch of FIG.

11 is a configuration diagram of a nonvolatile memory device using a multilayer phase change resistance cell according to the present invention.

12 is a layout diagram of the multilayer phase change resistance cell array of FIG.

13 is a detailed circuit diagram of the multilayer phase change resistance cell array of FIG.

14 is a timing diagram of an operation in a read mode of a nonvolatile memory device using a multilayer phase change resistance cell according to the present invention;

15 is an operation timing diagram in a write mode of a nonvolatile memory device using a multilayer phase change resistance cell according to the present invention;

16 is a view for explaining a temperature characteristic of a multilayer phase change resistance cell in the write mode of the nonvolatile memory device using the multilayer phase change resistance cell according to the present invention;

Claims (14)

A series diode switch having an insulating layer formed on the substrate and at least two diode elements formed of a silicon layer on the insulating layer and connected in series; A phase change resistance device including a top electrode, a phase change layer, and a bottom electrode, and configured to sense a crystallization state that changes according to a magnitude of a current applied from a word line and to store data corresponding to a change in resistance; A bit line connected to both ends of the series diode switch through a bit line contact node; A contact node connecting the common node to which the at least two diode elements are connected and the bottom electrode; And A unit phase change resistance cell having a word line formed on the top electrode, The plurality of unit phase change resistance cells are provided in a row and column direction, and the plurality of unit phase change resistance cells are stacked in a multi-layer structure and separated from each other by the insulating layer. The multi-phase phase change resistance cell of claim 1, wherein the silicon layer is formed of at least one of growth silicon and polysilicon. The multi-layer phase change resistance cell of claim 1 or 2, wherein the silicon layer is formed by alternately connecting a plurality of PNPN diode switches and a plurality of PN diode switches in series to form a continuous diode chain. 4. The multilayer phase change resistance cell of claim 3, wherein the bit line contact node is formed in a P-type region of the plurality of PNPN diode switches and an N-type region of the plurality of PN diode switches, respectively. The multilayer phase change resistance cell of claim 3, wherein the contact node is formed at the common node to which an N-type region of the plurality of PNPN diode switches and a P-type region of the plurality of PN diode switches are connected. A plurality of multilayer phase change resistance cell arrays arranged in a row and column direction and including a plurality of multilayer phase change resistance cells stacked in a multilayer structure and separated from each other by an insulating layer; A plurality of word line drivers selectively driving word lines of the plurality of multi-layer phase change resistance cell arrays; And And a plurality of sense amplifiers for sensing and amplifying data applied from the plurality of multilayer phase change resistance cell arrays. Each of the plurality of multi-layer phase change resistance cells A phase change resistance device configured to store a data corresponding to a change in resistance by detecting a crystallization state that changes according to a magnitude of a current applied from a word line; And A series diode switch having at least two diode elements connected to one end of the phase change resistance element in series and connected in series, and selectively switched according to the magnitude of the voltage applied to the word line and the bit line Non-volatile memory device using a multi-layer phase change resistance cell comprising a. The method of claim 6, A data bus shared by the plurality of sense amplifiers; A main amplifier for amplifying data applied from the data bus; A data buffer for buffering amplified data applied from the main amplifier; And Non-volatile memory device using a multi-layer phase change resistance cell characterized in that it further comprises an input / output port for outputting the output data applied from the data buffer to the outside, or the input data applied from the outside to the data buffer . 8. The method of claim 6 or 7, wherein the series diode switch is switched to read data stored in the phase change resistance element when the voltage applied to the word line is the first voltage, and the voltage applied to the bit line And a switching operation to write data to the phase change resistance device when the second voltage is greater than the first voltage. The method of claim 6 or 7, wherein each of the plurality of multi-layer phase change resistance cell array, A plurality of multi-layer phase change resistance cells positioned in an intersection region between the plurality of word lines and the plurality of bit lines arranged in the row and column directions, respectively; And And a plurality of bit line pull-down devices connected to the plurality of bit lines in a one-to-one correspondence, respectively. 8. The method of claim 6 or 7, wherein the plurality of sense amplifiers are connected one-to-one to a plurality of bit lines, respectively, and compare and amplify a reference voltage and a voltage of the bit line when the sense amplifier enable signal is activated. A nonvolatile memory device using a multilayer phase change resistance cell. The method of claim 6 or 7, wherein the series diode switch A PN diode switch connected in a forward direction between the bottom electrode of the phase change resistance device and the bit line; And And a PNPN diode switch connected in a reverse direction between the bottom electrode of the phase change resistor and the bit line. The nonvolatile memory device of claim 11, wherein the P-type region of the PN diode switch is connected to the bottom electrode, and the N-type region is connected to the bit line. The nonvolatile memory device of claim 11, wherein an upper N-type region of the PNPN diode switch is connected to the bottom electrode, and a lower P-type region is connected to the bit line. The method of claim 11, wherein the series diode switch When the voltage level of the word line is high and the voltage level of the bit line is low, the PN diode switch is turned on and outputs first data to the phase change resistor. When the voltage level of the word line is negative and the voltage level of the bit line is high, the PNPN diode switch is turned on to operate to output second data to the phase change resistance device. Nonvolatile memory device using.