KR20050054520A - Driving apparatus of liquid crystal display and driving method thereof - Google Patents

Abstract

Disclosed are a driving device of a liquid crystal display device and a driving method thereof capable of realizing a plurality of resolutions without using a conventional scaler.

The liquid crystal display of the present invention generates a resolution control signal from the image data input by the timing controller, generates a scan pulse reflecting the resolution according to the resolution control signal by the gate driver, and generates a scan pulse in accordance with the resolution control signal by the data driver. The data is changed to reflect the resolution, and the changed data is displayed on the liquid crystal panel.

Description

Driving apparatus for liquid crystal display device and driving method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving device of a liquid crystal display device and a driving method thereof capable of realizing a plurality of resolutions without using a conventional scaler.

In general, CRT monitors have been mainly used as devices for displaying information of TVs and computers. CRT has been the mainstay of display devices for its high picture quality and high screen brightness. However, in recent years, as the screen of the monitor becomes larger, various functions are added. As a result, the conventional CRT monitor becomes too large to occupy a lot of space and weighs a lot so that it is not bonded as an optimal monitor.

Reflecting this, recently, liquid crystal displays (LCDs), plasma display panels (PDPs), organic luminescence (EL), light emitting diodes (LEDs), and field emission displays (FEDs) Flat panel display devices have been introduced. Among such flat panel display devices, LCDs, which are widely used as notebook PCs or computer monitors, and have low power consumption, are in the spotlight.

1 is a block diagram schematically showing a computer system to which a liquid crystal monitor having a conventional liquid crystal display device is connected.

As shown in FIG. 1, the liquid crystal monitor 20 used in a conventional computer system includes a scaler 22, a timing controller 23, a liquid crystal module 24, a microcontroller 21, and an inverter ( 28 and a backlight unit 29.

The microcontroller 21 is a scaler 22, a timing controller 23 and an inverter 28 according to a control command from a universal serial bus (USB) port 14 included in the PC main body 10. By changing the operation mode of the image quality and the position of the image is adjusted.

The scaler 22 changes the image data from the graphics card included in the PC main body 10 to a resolution suitable for the liquid crystal module 24 under the control of the microcontroller 21.

The timing controller 23 generates a gate control signal and a data control signal using the synchronization signal separated from the image data, and transmits the generated gate control signal and the data control signal to the liquid crystal module 24. The timing controller 23 may be provided in the liquid crystal module 24.

The liquid crystal module 24 supplies the image data to the liquid crystal panel 27, the gate driver 25 for sequentially driving the gate lines of the liquid crystal panel 27, and the data lines of the liquid crystal panel 27. It consists of a data driver 26 for this purpose.

The gate driver 25 sequentially scans the gate lines of the liquid crystal panel 27 according to the gate control signal provided from the timing controller 23 to sequentially drive the gate lines.

The data driver 26 sequentially latches the image data according to a data control signal provided from the timing controller 23, and then outputs the image data collectively when the corresponding gate line is driven.

The liquid crystal panel 27 is a liquid crystal is injected between the two glass substrates, the gate lines and the data lines are formed on the lower glass substrate to be orthogonal to each other. A thin film transistor (TFT) for selectively supplying image data input from the data lines to the liquid crystal cell is formed at the intersection of the gate lines and the data lines. In this case, a gate terminal of the thin film transistor is connected to the gate line, and a source terminal of the thin film transistor is connected to the data line. The drain terminal of the thin film transistor is connected to the pixel electrode.

Therefore, when the scan signal is provided to the gate electrode of the thin film transistor through one gate line by the gate driver, the thin film transistor is turned on, and the image data output from the data driver is The amount of light transmitted to the pixel electrode through the source terminal and the drain terminal of the thin film transistor to drive the liquid crystal is controlled to display a predetermined image. This operation is performed for all the gate lines for one frame period, and the image is continuously displayed every frame, so that a moving image can be implemented.

On the other hand, the inverter 28 changes the voltage level of the voltage signal to be supplied to the backlight unit 29 under the control of the microcontroller 21. In addition, the backlight unit 29 irradiates light to the rear surface of the liquid crystal panel in response to the voltage signal changed by the inverter 28. In this way, by varying the voltage signal in the inverter 28, the brightness of the image can be adjusted.

As described above, in the conventional computer system, when the input image is different from the resolution set in the liquid crystal monitor, a scaler is used to change the resolution of the input image to match the set resolution.

Therefore, various resolutions are supported through such a scaler. The scaler is typically provided inside a system or timing controller.

In general, the liquid crystal module is manufactured separately and mounted on the liquid crystal monitor.

However, such a scaler is not provided in the liquid crystal module but is provided in the system, and when the liquid crystal module having a resolution not supported by the scaler is mounted on the liquid crystal monitor, the scaler becomes useless.

Accordingly, the present invention has been made to solve the above problems, and provides a driving apparatus and a driving method of a liquid crystal display device capable of supporting a plurality of resolutions only by the liquid crystal module by adding simple logic to the driving circuit of the liquid crystal module. Has its purpose.

According to a preferred embodiment of the present invention for achieving the above object, the driving device of the liquid crystal display device is a resolution control signal, a gate start pulse, a gate shift pulse and a gate by using input data and a synchronization signal separated from the data. Timing control means for generating a gate control signal including an output enable and a data control signal including a source start pulse, a source shift pulse, and a source output enable; A gate driver controlling the resolution according to the resolution control signal and outputting a scan pulse according to the controlled resolution by using a gate control signal including a gate start pulse, a gate shift clock, and a gate output enable; A data driver controlling the resolution according to the resolution control signal and varying and outputting data according to the controlled resolution using a data control signal including a source start pulse, a source shift clock, and a source output enable; A liquid crystal panel displaying the variable data; And a backlight for irradiating light on the rear surface of the liquid crystal panel in response to the voltage signal changed according to the synchronization signal.

According to another preferred embodiment of the present invention, a method of driving a liquid crystal display device includes a resolution control signal, a gate start pulse, a gate shift pulse, and a gate output enable using input data and a synchronization signal separated from the data. Generating a data control signal comprising a gate control signal and a source start pulse, a source shift pulse and a source output enable; Controlling a resolution according to the resolution control signal, and outputting a scan pulse according to the controlled resolution using a gate control signal including a gate start pulse, a gate shift clock, and a gate output enable; Controlling the resolution according to the resolution control signal, and varying and outputting data according to the controlled resolution using a data control signal including a source start pulse, a source shift clock, and a source output enable; Displaying the variable data; And irradiating light to the rear surface of the liquid crystal panel in response to the voltage signal changed according to the synchronization signal.

Hereinafter, a driving device of the liquid crystal display device of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating a computer system to which a liquid crystal monitor having a liquid crystal display device is connected according to an exemplary embodiment of the present invention. 3 is a circuit diagram illustrating the gate driver of FIG. 2. 4 and 5 show input and output waveform diagrams of the gate driver of FIG. 2, respectively. 6 is a circuit diagram illustrating the data driver of FIG. 2. 7 and 8 show input and output waveform diagrams of the data driver of FIG. 2.

As shown in FIG. 2, the present invention eliminates the scaler used to adjust the resolution, and instead drives the gate driver and the data driver according to the resolution control signal generated by the timing controller, thereby resolving the resolution of the native resolution and the native resolution. Implement half the resolution.

Referring to FIG. 2, the liquid crystal monitor 40 used in the computer system is composed of a timing controller 44, a liquid crystal module 45, a microcontroller 42, an inverter 47, and a backlight unit 48.

The microcontroller 42 changes the operation modes of the timing controller 44 and the inverter 47 according to control commands from the universal serial bus included in the PC main body 30 so that the image quality and the position of the image are adjusted. .

The timing controller 44 receives image data provided from the graphics card of the PC main body 30 from the graphics card 12 of the PC main body 30 according to a clock signal provided from the microcontroller 42. The resolution control signal, the gate control signals GSP, GSC, and GOE and the data control signals SSP, CLK, and SOE are generated using the separated synchronization signal and transmitted to the liquid crystal module 45. The timing controller 44 may be provided in the liquid crystal module 45.

The resolution control signal is determined by the timing controller 44 to determine whether the image data is data for basic resolution or resolution data corresponding to half of the data for basic resolution, and according to the result, '0' or '1' is determined. Will be created. Therefore, when the image data is data for basic resolution, a resolution control signal of '0' is generated, and when the image data is data for resolution corresponding to half of the data for basic resolution, a resolution control signal of '1' is generated. Will be.

For example, when the horizontal / vertical resolution designed for the liquid crystal module is 1024/768, the basic resolution is 1024/768, and the half resolution is 1024/384. If the input data can display 384 pixels for one vertical line, it corresponds to half of 768 pixels per one vertical line designed in the liquid crystal module. Therefore, if such data is displayed on the liquid crystal module as it is, only half of one screen is displayed. Therefore, when the half-resolution data is input in this way, by generating a control signal having a resolution control signal of '1' to display the data corresponding to one pixel two by one, the image is displayed on all screens of the liquid crystal module. Data can be displayed.

As a result, the resolution control signal is provided to the gate driver and the data driver so that the input image data is varied to be displayed on the liquid crystal module 45 so as to be bonded to the resolution of the liquid crystal module.

As described above, the gate control signal includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE). The GSP is a time when data of one frame is provided, that is, a vertical synchronization signal ( It is a gate start pulse that informs the time point of turning on the first gate line of the screen for one period in which Vsync) is provided, and the GSC is a gate of a thin film transistor (TFT) provided in the liquid crystal module 45. The gate shift clock determines the time when the terminal is turned on or off, and GOE means a gate output enable that controls the output of the gate driver. In addition, the data control signal includes a source start pulse (SSP), a CLK (or SSC), and a source output enable (SOE). The SSP is a start point of data among one horizontal sync signal (Hsync), that is, data on a first data line. Is a source start pulse that indicates when is provided, CLK is a source shift clock that indicates the time to drive the data driver, and SOE means a source output enable that determines the output of the source driver. .

The liquid crystal module 45 supplies the image data to the liquid crystal panel 46, the gate driver 50 for sequentially driving the gate lines of the liquid crystal panel 46, and the data lines of the liquid crystal panel 46. It consists of a data driver 60 for this purpose.

The gate driver 50 varies with a predetermined resolution according to a resolution control signal provided from the timing controller 44, and sequentially provides scan pulses to gate lines of the liquid crystal panel 46 according to the gate control signal. Drive the gate lines sequentially. In other words, the gate driver 50 varies the image data to a resolution to be displayed on the liquid crystal panel 46 according to the resolution control signal. For example, when the resolution control signal is' 0 ', scan pulses are sequentially provided to each of the gate lines of the liquid crystal panel 46 according to the gate control signal, whereas the resolution control signal is' In the case of 1 ', scan pulses are sequentially provided to two gate lines of the liquid crystal panel according to the gate control signal. In other words, when the resolution control signal is '1', scan pulses are simultaneously provided to the first and second gate lines, and next scan pulses are simultaneously provided to the third and fourth gate lines. This operation is performed repeatedly for all the provided gate lines.

As shown in FIG. 3, the circuit configuration diagram of the gate driver 50 includes a gate shift register 51, a first resolution variable unit 53, an AND product 55, a level shifter 57, and a first buffer. It consists of a part 59.

The gate shift register 51 includes a plurality of flip flops 51a to 51e corresponding to each of the gate lines of the liquid crystal panel 46. At this time, the output terminal of each of the flip-flops 51a to 51e is connected to the input terminal of the next flip-flop and the logical product operation unit 55, the GSP is input to the first flip-flop 51a, and the respective flip-flops 51a are input. To 51e), the GSC is input. In this case, an output terminal of each of the AND gates 53a to 53c included in the first resolution variable part 53 is connected to an input terminal of each of the even-numbered flip-flops 51b and 51d.

The first resolution variable part 53 includes a plurality of AND gates 53a to 53c whose output values are provided to input terminals of even-numbered flip-flops 51b and 51d. In other words, an output terminal of each of the AND gates 53a to 53c is connected to an input terminal of even-numbered flip-flops 51b and 51d. At this time, a resolution control signal is input to each AND gate 53a to 53c, and a signal output from each AND gate 53a to 53c is provided to an input of even-numbered flip-flops 51b and 51d.

The GSP is input to the first AND gate 53a as well as the resolution control signal, and is ANDed to provide an output value to the second flip-flop 51b. The output values output from the GSP and the even-numbered flip-flop 51b are inputted to the second and subsequent AND gates 53b and 53c, and the result of the multiplication and operation is provided to the next even-numbered flip-flop 51d.

When a resolution control signal having a value of '0' is inputted, all output values of the AND gates 53a to 53c are all '0'. Accordingly, when a GSP is input to the first flip-flop 51a, a value of '1' is obtained. According to GSC, output values are sequentially sent to the AND product 55 from the first flip-flop 51a. On the other hand, when a resolution control signal of '1' is input, the output value '1' of the first AND gate 53a is provided to the second flip-flop 51b according to the GSP of '1' and at the same time, the first The flip-flop 51a is also provided with a GSP of '1'. At this time, when the GSC of '1' is input to each of the flip-flops 51a to 51e, the output value of '1' is simultaneously displayed at the first flip-flop 51a and the second flip-flop 51b. Will be exported). Subsequently, the output value output from the second flip-flop 51b is provided to the third flip-flop 51c and simultaneously provided to the second AND gate 53b. The second AND gate 53b performs an AND operation on the resolution control signal of '1', which is waiting in advance, and the output value of '1' provided from the second flip-flop 51b, and flips the output value '1' to the fourth flip. The flop 51d is provided. Accordingly, the third flip-flop 51c and the fourth flip-flop 51d have 1 at the same time, and when the next '1' GSC is input, the third flip-flop 51c and the fourth flip-flop At 51d, an output value of '1' is simultaneously sent to the AND product 55. This process is performed for all the gate lines of the liquid crystal panel 46. Therefore, when the resolution control signal is '1', two scan signals are output sequentially.

The AND product 55 performs an AND operation on the output signal provided by the gate shift register 51 and the GOE, and provides the output value to the level shifter 57. To this end, the OR operation unit 55 includes a plurality of OR gates 55a to 55d corresponding to the flip-flops 51a to 51e. Here, the GOE is a signal for controlling the output of the gate driver 50, that is, a signal for controlling the output of the gate shift register 51, and is input to each of the plurality of logical sum gates 55a to 55d. Therefore, when the GOE is '0', the output signal of the corresponding flip-flop is logically multiplied with the GOE and output to the level shifter 57 because the inversion is '1' by the NOT gate. ', The output signal of the corresponding flip-flop is not output because it is inverted to' 0 'by the NOT gate.

The level shifter 57 includes a plurality of sub-level shifters 57a to 57d to shift the voltage of the output signal output from the AND product 55 to a level suitable for driving the liquid crystal panel 46. .

The first buffer unit 59 includes a plurality of buffers 59a to 59d to signal-buffer the signal output from the level shifter 57 to the gate lines of the liquid crystal panel 46.

Meanwhile, the data driver 60 varies to a predetermined resolution according to the resolution control signal provided from the timing controller 44 and then provides data to the data lines of the liquid crystal panel 46 according to the data control signal. . In other words, the data driver 60 varies the image data to a resolution to be displayed on the liquid crystal panel 46 according to the resolution control signal. For example, when the resolution control signal is '0', the liquid crystal is sequentially latched once for each data corresponding to one pixel input according to the data control signal, and when the data is input to all the latches, the liquid crystals are collectively collected. Provided are the data lines of panel 46. On the other hand, when the resolution control signal is '1', the latch is sequentially latched twice for each data corresponding to one pixel input according to the data control signal, and then collectively when the data is input to all the latches. Provided as data lines. In other words, when the resolution control signal is '1', data corresponding to one pixel is displayed as two pixels. In this way, the image data may be displayed at the resolution of the liquid crystal module 45 even if the resolution data corresponds to half of the basic resolution.

As shown in FIG. 6, the circuit configuration diagram of the data driver 60 includes the second resolution variable part 61, the data shift register 63, the first latch part 65, the second latch part 67, It consists of a DAC unit 69 and a second buffer unit 71.

The second resolution variable part 61 includes a plurality of AND gates 61a and 61b whose output values are provided to input terminals of even-numbered flip-flops 63b and 63d of the data shift register 63. In other words, an output terminal of each of the AND gates 61a and 61b is connected to an input terminal of even-numbered flip-flops 63b and 63d. At this time, a resolution control signal is input to each AND gate 61a, 61b, and a signal output from each AND gate 61a, 61b is provided to an input of even-numbered flip-flops 63b, 63d.

The SSP, as well as the resolution control signal, is input to the first AND gate 61a to be ANDed to provide an output value to the second flip-flop 63b. An output value output from the SSP and the even-numbered flip-flop 63d is input to the second and subsequent AND gates 61b, and is provided as an even-numbered flip-flop followed by an AND operation.

When a resolution control signal of '0' is inputted, the output values of the AND gates 61a and 61b are all '0'. Accordingly, when the SSP is input to the first flip-flop 63a, According to CLK, output values are sequentially sent to the first latch unit 65 from the first flip-flop 63a. On the other hand, when a resolution control signal of '1' is input, the output value '1' of the first AND gate 61a is provided to the second flip-flop 63b according to the SSP of '1' and at the same time, the first The flip-flop 63a is also provided with an SSP of '1'. At this time, when CLK of '1' is inputted to each of the flip-flops 63a to 63d, the first latch unit 65 simultaneously outputs the value of '1' at the first flip-flop 63a and the second flip-flop 63b. Will be exported). Subsequently, the output value output from the second flip-flop 63b is provided to the third flip-flop 63c and simultaneously provided to the second AND gate 61b. The second AND gate 61b performs an AND operation on the resolution control signal of '1', which is waiting in advance, and the output value of '1' provided from the second flip-flop 63b, and flips the output value '1' to the fourth flip. It is provided by the flop 63d. Accordingly, the third flip-flop 63c and the fourth flip-flop 63d have 1 at the same time, and when the next '1' CLK is input, the third flip-flop 63c and the fourth flip-flop At the same time at 63d, an output value of '1' is sent out to the first latch portion 65. In addition, the operation of the remaining AND gates is repeatedly performed as described above, so that two output values are sequentially provided to the first latch unit 65.

Accordingly, when the resolution control signal is '1', the output signals are simultaneously output from two flip-flops at a time, and thus data corresponding to one pixel to be input is latched in two latches at the same time. The same data is displayed on two pixels on the screen.

The data shift register 63 includes a plurality of flip flops 63a to 63d corresponding to each of the data lines of the liquid crystal panel 46. At this time, the output terminal of each of the flip-flops 63a to 63d is connected to the input terminal of the next flip-flop and the first latch unit 65, the SSP is input to the first flip-flop 63a, and the remaining flip-flops 63b. The output value is input from the flip-flop of the immediately preceding stage to the input terminal of the second through 63d), and the CLK is input to each of the flip-flops 63a through 63d.

The first latch unit 65 includes a plurality of latches 65a to 65d corresponding to the flip-flops 63a to 63d, and according to an output signal provided from each of the flip-flops 63a to 63d. The data is sequentially latched and provided to the second latch portion 67.

For example, when the resolution control signal is '0', output signals are sequentially input to the first latch unit 65 from the respective flip-flops 63a to 63d provided in the data shift register 63. In addition, the first latch unit 65 sequentially latches data corresponding to one pixel to each latch according to the sequentially input signal.

If the resolution control signal is '1', the output signal is simultaneously output from the first and second flip-flops 63a and 63b provided in the data shift register 63 by the first CLK, and by the second CLK. The output signal is output from the third and fourth flip-flops 63c and 63d at the same time. As such, when an output signal is simultaneously output from the first and second flip-flops 63a and 63b by the resolution control signal of '1', data corresponding to one pixel is simultaneously displayed according to the output signal. The first and second latches 65a and 65b are latched. Next, when an output signal is simultaneously output from the third and fourth flip-flops 63c and 63d, the data corresponding to the next one pixel is simultaneously the third and fourth latches 65c and 65d according to the two output signals. ) Is latched. As such, the same pixel data latched in the two latches by the first latch unit 65 are sequentially provided to the second latch unit 67.

The second latch portion 67 includes a plurality of latches 67a to 67d corresponding to the latches 65a to 65d of the first latch portion 65, and in the first latch portion 65. The two latches simultaneously receive data sequentially and output the data to the DAC unit 69 by the SOE.

The DAC unit 69 includes a plurality of digital to analog converters (DACs) 69a to 69d corresponding to the latches 67a to 67d of the second latch unit 67, and the second latch unit Each of the digital data collectively provided at 67 is converted into analog data.

The second buffer unit 71 includes a plurality of buffers 71a to 71d corresponding to the plurality of DACs 69a to 69d to amplify each of the data converted into analog in the DAC unit 69. After that, the data lines are provided to respective data lines of the liquid crystal panel 46.

The liquid crystal panel 46 is a liquid crystal is injected between the two glass substrates, the gate lines and the data lines are formed on the lower glass substrate to be perpendicular to each other. A thin film transistor (TFT) for selectively supplying image data input from the data lines to the liquid crystal cell is formed at the intersection of the gate lines and the data lines. In this case, a gate terminal of the thin film transistor is connected to the gate line, and a source terminal of the thin film transistor is connected to the data line. The drain terminal of the thin film transistor is connected to the pixel electrode.

Therefore, when the resolution control signal is '0', the liquid crystal panel 46 provides a scan signal to the gate electrode of the thin film transistor through one gate line by the gate driver 50, and the thin film transistor is At this time, the data output from the data driver 60 is supplied to the pixel electrode via the source terminal and the drain terminal of the thin film transistor to drive the liquid crystal so that the amount of light transmitted is adjusted to display a predetermined image. do. This operation is performed for all the gate lines for one frame period, and the image is continuously displayed every frame, so that a moving image can be implemented. On the other hand, when the resolution control signal is '1', the liquid crystal panel 46 simultaneously provides a scan signal to two gate lines at a time by the gate driver 50, and correspondingly, the data driver At 60, data corresponding to one pixel is changed to be displayed as two pixels, and the changed data are displayed on the liquid crystal panel 46.

On the other hand, the inverter 47 changes the voltage level of the voltage signal to be supplied to the backlight unit 48 under the control of the microcontroller 42. In addition, the backlight unit 48 emits light to the rear surface of the liquid crystal panel in response to the voltage signal changed by the inverter 47. In this way, the voltage signal in the inverter 47 is varied, so that the brightness of the image can be adjusted.

Hereinafter, the operation of the gate driver will be described with reference to FIGS. 3 to 5.

On the basis of the image data input by the timing controller 44, it is determined whether the data is the resolution for the basic resolution or the resolution data corresponding to half of the data for the basic resolution. A resolution control signal is generated. In this case, when the resolution control signal is generated as '0', it means that the image data is data for the basic resolution. When the resolution control signal is generated as '1', the image data is called resolution data corresponding to half of the data for the basic resolution. Means that. In addition, a gate control signal and a data control signal for driving the gate driver 50 and the data driver 60 are generated using a synchronization signal separated from the image data input by the timing control signal. The gate control signal may include GSP, GSC, SOE, and the like, and the data control signal may include SSP, CLK (or SSC), SOE, and the like.

The gate driver 50 receives the resolution control signal and the gate control signal from the timing controller 44, changes the resolution according to the resolution control signal, and sequentially applies predetermined scan pulses according to the gate control signal. To the gate line.

The gate driver 50 may provide different scan pulses according to the resolution control signal '0' or '1'.

As shown in FIG. 4, when a resolution control signal having a value of '0' is input to the first resolution variable part 53, any output value is output from all the AND gates included in the first resolution variable part 53. Will not be.

At this time, when the GSP of '1' is input to the first flip-flop 51a of the gate shift register 51, the output signal of '1' from the first flip-flop 51a is logically multiplied by the GSC of '1'. It is output to the first AND gate 55a of the calculator 55 and is provided to the second flip-flop 51b. The output signal of '1' provided to the first AND gate 55a is output when the GOE is '0' and is provided to the corresponding gate line through the corresponding sub-level shifter 57a and the buffer 59a. .

On the other hand, the output signal of '1' input to the second flip-flop 51b is output to the output signal of '1' by the GSC of the next '1' to the second logical gate ( 55b) and the third flip-flop 51c. The output signal of '1' provided to the second AND gate 55b is provided to the next corresponding gate line through the corresponding sub-level shifter 57b and the buffer 59b under the control of the GOE.

Through this process, signals sequentially output from the flip-flops 51a to 51d are sequentially provided to the gate lines under the control of the GOE.

On the other hand, when the resolution control signal '1' is input to the first resolution variable unit 53, as shown in FIG. 5, the first AND gate 53a of the first resolution variable unit 53 has a resolution. In addition to the control signal, whether or not the output is determined by another input value, GSP.

As described above, the GSP is input to the first flip-flop 51a of the gate shift register 51 and the first AND gate 53a of the first resolution variable part 53.

In this case, a GSP of '1' is inputted to the first flip-flop 51a and the first AND gate 53a of the first resolution variable part 53. Then, the first AND gate 53a outputs an output signal of '1' and is provided to the second flip-flop 51b. Accordingly, a signal of '1' is input to both the first and second flip-flops 51a and 51b.

Next, when a GSC of '1' is input to each of the flip-flops 51a to 51d, the first and second flip-flops 51a and 51b simultaneously output an output signal of '1' to the AND product 55. To the corresponding first and second AND gates 55a, 55b. In addition, an output signal of '1' provided to the first and second AND gates 55a and 55b is controlled by GOE to correspond to the corresponding first and second sub-level shifters 57a and 57b and the first and second. The first and second gate lines are simultaneously provided through the first buffers 59a and 59b.

Meanwhile, an output signal of '1' output from the second flip-flop 51b is provided to the third flip-flop 51c and the second AND gate 53b of the first resolution variable part 53. At this time, since the resolution control signal of '1' is input to the second AND gate 53b, the resolution control signal of '1' and the output signal of '1' output from the third flip-flop 51c. Based on the AND operation, the output signal of '1' is provided to the third and fourth AND gates 55c and 55d of the AND operation unit 55. In addition, an output signal of '1' provided to the third and fourth AND gates 55c and 55d is controlled by a GOE to correspond to the corresponding third and fourth sub-level shifters 57c and 57d and third and fourth. The third and fourth gate lines are simultaneously provided through the first buffers 59c and 59d.

Through this process, two signals sequentially output from two flip-flops 51a and 51b, 51c, and 51d by one GSC are sequentially provided to two gate lines under the control of GOE. .

An operation of the data driver will be described with reference to FIGS. 6 to 8.

The data driver 60 receives the resolution control signal and the data control signal from the timing controller 44, changes the resolution according to the resolution control signal, and then supplies predetermined data according to the data control signal to the data of the liquid crystal module 45. To the line.

The gate driver 50 may provide data differently according to the resolution control signal '0' or '1'.

As shown in FIG. 7, when a resolution control signal of '1' is inputted to the resolution variable unit 61, any output value is output from all the AND gates 61a and 61b provided in the resolution variable unit 61. Will not be.

At this time, when the SSP of '1' is input to the first flip-flop 63a of the data shift register 63, the output signal of '1' is output from the first flip-flop 63a by the CLK of '1'. The first latch 65a and the second flip-flop 63b of the latch portion 65 are provided at the same time. Data corresponding to one pixel is latched by the output signal of '1' provided to the first latch 65a and provided to the first latch 67a of the second latch unit 67.

Meanwhile, the output signal of '1' input to the second flip-flop 63b is output as an output signal of '1' by the CLK of the next '1', so that the second latch 65b of the first latch unit 65b is output. ) And a third flip-flop 63c. In addition, the output signal of '1' provided to the second latch 65b is latched with data corresponding to the next one pixel and is provided to the second latch 67b of the second latch unit 67.

When all data corresponding to each pixel are inputted to the second latch unit 67 by the signals sequentially output from the flip-flops 63a to 63d through the above process, the DAC unit is controlled by SOE. 69 and a second buffer unit 71 are collectively provided to the respective data lines.

On the other hand, when the resolution control signal '1' is input to the resolution variable section 61, as shown in FIG. 8, the first AND gate 61a of the resolution variable section 61 is in addition to the resolution control signal. Whether or not it is output depends on other input value SSP.

As described above, the SSP is input to the first flip-flop 63a of the data shift register 63 and the first AND gate 61a of the resolution variable unit 61.

In this case, an SSP of '1' is inputted to the first flip-flop 63a and the first AND gate 61a of the resolution variable unit 61. Then, the first AND gate 61a outputs an output signal of '1' and is provided to the second flip-flop 63b. Accordingly, a signal '1' is input to both the first and second flip-flops 63a and 63b.

Next, when CLK of '1' is inputted to each of the flip-flops 63a to 63d, the first and second flip-flops 63a and 63b simultaneously output an output signal of '1' to the first latch unit ( To the corresponding first and second latches 65a, 65b. The first and second latches 65a and 65b simultaneously latch data corresponding to one pixel according to signals simultaneously output from the first and second flip-flops 63a and 63b. In other words, data corresponding to one pixel is simultaneously input to the first and second latches 65a and 65b.

The output signal of '1' output from the second flip-flop 63b is provided to the third flip-flop 63c and the second AND gate 61b of the resolution variable unit 61. At this time, since the resolution control signal of '1' is input to the second AND gate 61b, the resolution control signal of '1' and the output signal of '1' output from the third flip-flop 63c. Based on the AND operation, the output signal '1' is provided to the third and fourth latches 65c and 65d of the first latch unit 65. The third and fourth latches 65c and 65d simultaneously latch data corresponding to the next one pixel according to signals simultaneously output from the third and fourth flip-flops 63c and 63d. That is, data corresponding to the next one pixel is simultaneously input to the third and fourth latches 65c and 65d.

Through this process, when data corresponding to each pixel are all input to the second latch unit 67 by signals simultaneously output from two flip-flops 63a and 63b, 63c, and 63d, the SOE Under the control, the data is collectively provided to the data lines through the DAC unit 69 and the second buffer unit 71.

Through this process, it is possible to display two pieces of data corresponding to one pixel according to two signals sequentially output simultaneously from two flip flops by one CLK.

Although displaying data by one SSP has been described so far, data may be continuously displayed by an additionally applied SSP. That is, when one SSP is input, data is displayed on each pixel positioned on one gate line, and when an SSP that is '1' is input, the same processing as described above is performed and positioned on the next gate line. Data may be displayed in each pixel. Through this process, data corresponding to each pixel positioned on all gate lines of the liquid crystal module 45 is displayed.

Accordingly, the present invention may determine the resolution to be changed based on the input image data, and provide scan pulses and data according to the resolutions determined by the gate driver and the data driver according to the resolution control signal, and display them on the liquid crystal panel. .

As described above, according to the driving apparatus and driving method thereof of the liquid crystal display device of the present invention, a plurality of gates having variable resolution can be added to the gate driver and the data driver instead of using the existing scaler. Resolution can be implemented.

Therefore, by adding an AND gate that can easily change the resolution to the gate driver and the data driver, a plurality of resolutions can be realized while simplifying the system.

1 is a block diagram schematically showing a computer system to which a liquid crystal monitor having a conventional liquid crystal display device is connected.

2 is a block diagram schematically illustrating a computer system to which a liquid crystal monitor having a liquid crystal display device is connected according to an exemplary embodiment of the present invention.

3 is a circuit diagram illustrating a gate driver of FIG. 2.

4 and 5 are input and output waveform diagrams of the gate driver of FIG.

FIG. 6 is a circuit diagram illustrating the data driver of FIG. 2. FIG.

7 and 8 are input and output waveform diagrams of the data driver of FIG.

<Name of the code for the main part of the drawing>

30: PC main body 40: LCD monitor

44: timing controller 45: liquid crystal module

46: liquid crystal panel 50: gate driver

51: gate shift register 53, 61: resolution variable portion

55: logical sum operation unit 57: level shifter

59, 71: buffer 63: data shift register

65, 67: latch portion 69: DAC portion

Claims (20)

A gate control signal including a resolution control signal, a gate start pulse, a gate shift pulse, and a gate output enable and a source start pulse, a source shift pulse, and a source output enable using the input data and the synchronization signal separated from the data Timing control means for generating a data control signal comprising; A gate driver controlling the resolution according to the resolution control signal and outputting a scan pulse according to the controlled resolution by using a gate control signal including a gate start pulse, a gate shift clock, and a gate output enable; A data driver controlling the resolution according to the resolution control signal and varying and outputting data according to the controlled resolution using a data control signal including a source start pulse, a source shift clock, and a source output enable; And Liquid crystal panel for displaying the variable data Driving device of the liquid crystal display device comprising a. 2. The driving apparatus of claim 1, wherein the timing control means determines whether the data is data for basic resolution and generates a corresponding resolution control signal according to the determination result. The method of claim 1, The gate driver, A first resolution variable unit controlling a resolution according to the resolution control signal; A gate shift register configured to sequentially generate and output a scan pulse in response to the gate shift pulse according to the controlled resolution when the gate start pulse is input; An AND product controlling the output of the scan pulse output from the gate shift register according to the gate output enable; A level shifter for level shifting the voltage of the scan pulse output from the AND product; And A first buffer unit configured to amplify and output a level shifted scan pulse in the level shifter Driving device of the liquid crystal display device comprising a. 4. The apparatus of claim 3, wherein the resolution variable part comprises a plurality of AND gates for controlling the resolution by inputting the resolution control signal and the gate start pulse, and the signal output from each of the AND gates is a plurality of ORs. And an even-numbered flip-flop among the flip-flops of the liquid crystal display device. 4. The gate shift register of claim 3, wherein the gate shift register sequentially outputs an output signal from each flip-flop whenever the gate shift clock signal is applied when the resolution is controlled to a native resolution by the first resolution variable. Driving device for a liquid crystal display device characterized in that. 4. The gate shift register of claim 3, wherein when the resolution is controlled to half resolution by the first resolution variable unit, the gate shift register sequentially outputs output signals in units of two flip-flops every time the gate shift clock signal is applied. Driving device for a liquid crystal display device characterized in that the output. The method of claim 1, The data driver, A second resolution variable unit controlling the resolution according to the resolution control signal; A data shift register configured to sequentially output a signal in response to the source shift pulse according to the controlled resolution when the source start pulse is input; A latch unit sequentially latching data according to a signal output from the data shift register and then collectively outputting the data according to the source output enable; A digital-analog converter for converting data output from the latch unit into analog data; And A second buffer unit for amplifying and outputting analog data converted from the digital-analog converter Driving device of the liquid crystal display device comprising a. The method of claim 7, wherein the second resolution variable part comprises a plurality of AND gates for controlling the resolution by inputting the resolution control signal and the source start pulse, and the signal output from each of the AND gates is And an even-numbered flip-flop among the plurality of flip-flops. 8. The data shift register of claim 7, wherein the data shift register sequentially outputs an output signal from each flip-flop each time the data shift clock signal is applied, when the resolution is controlled to the native resolution by the second resolution variable. Driving device for a liquid crystal display device characterized in that. 8. The data shift register of claim 7, wherein when the resolution is controlled to half resolution by the second resolution variable unit, the data shift register sequentially outputs output signals in units of two flip-flops every time the data shift clock signal is applied. Driving device for a liquid crystal display device characterized in that the output. The driving apparatus of claim 10, wherein the latch unit latches data corresponding to one pixel into two latches simultaneously according to output signals output in units of two flip-flops. A gate control signal including a resolution control signal, a gate start pulse, a gate shift pulse, and a gate output enable and a source start pulse, a source shift pulse, and a source output enable using the input data and the synchronization signal separated from the data Generating a data control signal comprising; Controlling a resolution according to the resolution control signal, and outputting a scan pulse according to the controlled resolution using a gate control signal including a gate start pulse, a gate shift clock, and a gate output enable; Controlling the resolution according to the resolution control signal, and varying and outputting data according to the controlled resolution using a data control signal including a source start pulse, a source shift clock, and a source output enable; And Displaying the variable data Method of driving a liquid crystal display device comprising a. The method of claim 12, wherein the resolution control signal is generated according to whether or not the data is data for basic resolution. The method of claim 12, The step of outputting a scan pulse, Controlling the resolution according to the resolution control signal; Sequentially generating and outputting scan pulses in response to the gate shift pulses according to the controlled resolution when the gate start pulses are input; Controlling the output of the scan pulse output from the gate shift register in accordance with the gate output enable; Level shifting the voltage of the output scan pulse; And Amplifying and outputting the level shifted scan pulse Method of driving a liquid crystal display device comprising a. 15. The method of claim 14, wherein the output signal from each flip-flop is sequentially output whenever the gate shift clock signal is applied when the resolution is controlled at a basic resolution. 15. The method of claim 14, wherein when the resolution is controlled at half resolution, an output signal is sequentially output in units of two flip-flops every time the gate shift clock signal is applied. . The method of claim 12, The variable data outputting step includes: Controlling the resolution according to the resolution control signal; Sequentially outputting a signal in response to the source shift pulse according to the controlled resolution when the source start pulse is input; Sequentially latching data according to the output signal and then collectively outputting the data according to the source output enable; Converting the output data into analog data; And Amplifying and outputting the converted analog data Method of driving a liquid crystal display device comprising a. 18. The method of claim 17, wherein, when the resolution is controlled to the native resolution, the output signals from each flip-flop are sequentially output each time the data shift clock signal is applied. 18. The method of claim 17, wherein when the resolution is controlled at half resolution, an output signal is sequentially output in units of two flip-flops every time the data shift clock signal is applied. . 20. The method of claim 19, wherein data corresponding to one pixel is simultaneously displayed as two pixels according to the output signals output in units of two flip-flops.