KR20050040667A - Structure of mlc flash memory with segmented floating gate - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the construction of a semiconductor flash memory, and more particularly, to a state of a memory capable of storing a floating gate of a flash memory in one cell. It relates to a structure of a transistor characterized by increasing. In order to increase the state that can be stored in one cell, the structure of the present invention separates the two floating gates formed in one conventional quadrangle. By applying MLC (multi level cell) technology and mirror bit technology to each floating gate at the same time, the number of states that can be stored in one cell is increased by 8 times from 2 to 16. The technique of the present invention makes it possible to store 8 times the amount of information as compared to the prior art in a flash memory cell of the same area without changing the process technology.

Description

Structure of MLC flash memory with segmented floating gate}

Non-volatile semiconductor memory has started to look like today, starting with magnetic core memory and reaching EEPROM (electrically erasable and programmable read only memory). Flash memory is the most representative of the EEPROMs currently used, and is rapidly increasing in demand due to the recent expansion of digital cameras and mobile phones. And the competition for storing large amounts of data in the same area of semiconductors is heating up at the same time as the demand for flash memory increases. Until recently, it has been common to store one bit (two state) of information in one memory cell, but MLC (multi level cell) technology has emerged as an effort to store a large amount of information in a given area. MLC technology is a technology that stores as much information as possible in a given area without changing the structure or process of the cell transistor. The most representative MLC technology is to control the amount of charge stored in the floating gate to make several intermediate levels, which were mainly developed and used by Intel Corporation in the United States. Intel uses this technology to store two bits of information in one cell, which is twice the storage capacity of conventional structures. The other MLC method, also called mirror bit method, was also developed by AMD in the United States and is currently used in AMD products. Mirror bit method can also store 2 bits of data. In this design, the amount of information that can be stored in one cell is increased to 4 bits by applying MLC techniques developed to date to the improved transistor cell structure. This is eight times the storage capacity of conventional flash memory and four times the capacity increase compared to current MLC technology.

In the present invention, the structure of the transistor was changed to apply two types of MLC methods developed to date to one cell. That is, the floating gate electrode of the transistor was separated into two pieces, and the distribution of charge in the floating gate electrode was divided into two parts. To this end, in the process of forming a floating gate during the process, the floating gates were separated into two at the source and drain sides and etched and formed.

1 is a cell transistor configuration of a conventional general flash memory. In the figure, 3 and 4 represent the source and drain of the transistor, respectively, and 1 and 2 represent the control and floating gates. The programming of the cell occurs by applying a voltage to the source and drain of the transistor and applying a high voltage to the gate, electrons flowing through the channel of the transistor are trapped in the floating gate from the drain side through the gate insulating film. The electrons trapped by this mechanism increase the threshold voltage of the transistor, which has the effect of reducing the drain current in transistor operation. Intel-based MLC technology increases the memory capacity of the cell by adjusting the length or time of the gate pulse in programming by this mechanism to create several levels of quantification on the floating gate. 2 shows a mirror bit type MLC technique using a similar transistor structure and different programming methods. This technique requires programming both at the source and the drain, so unlike conventional transistors, the structure of the transistor needs to be symmetrical. In this structure, electrons are accumulated in the floating gate on the drain side when the transistor is operated with the fourth electrode as a drain, and when the third electrode is drained and the fourth is operated as a source, the charge is applied to the floating gate above the third electrode. Are gathered. By properly adjusting the characteristics of the floating gate and programming pulses, the electrons can be confined to the right or left side of the floating gate in each case. The electrons trapped in the floating gate on the drain side have a greater influence on the drain current than the electrons on the source side during operation of the transistor. Therefore, four states of voltage-current characteristics can be obtained depending on the presence or absence of electrons in each location. Can be. 3 is a voltage-current characteristic of a 2-bit device obtained by the two MLC methods as described above. In the figure, curve 1 is the current characteristic when there are no electrons in the floating gate, and curve 4 is when the floating gate is completely saturated with electrons and in the mirror bit method, electrons are trapped in both floating gates. 4 is a structure of a transistor according to the present invention. In this design, the floating gate is divided into two pieces on the source and drain side, and each piece is operated by mirror bit method and Intel type MLC is applied at the same time. In this structure, when electrons are injected into the floating gate 5, the amount of electrons entering the electrode 5 is controlled to four states while the electrode 3 is used as a drain. On the contrary, when electrons are injected at the second time, the fourth is used as the drain and the gate pulse is controlled to make four states in the two floating gates. As a result, two floating gates belonging to one transistor each produce four states, so that the voltage-current characteristics of the transistor collectively have 16 states. This operation is made possible by the separation of the floating gate. If you do not separate the floating gate, the electrons from both sides will be mixed with each other and the resolution of the electrons in the floating gate will not be increased. 5 is a planar structure of a transistor of the present invention. 6 is a voltage-resistance characteristic of 16 stages of the transistor of the present invention. Here, the charge states in the drain and source side floating gates in the 16 voltage-current states are as follows.

When the transistor having the floating gate separated from the present invention is used, electrons captured from the source and drain sides of FIG. 4 are not mixed with each other and are limited to their respective gate regions. In addition, when MLC technology is used to inject electrons into the source and the drain, two-bit states are formed in each region, thereby enabling four-bit data-side 16 states as a whole. This is an 8x increase in data integration capacity over the prior art and a 4x improvement in density over current MLC technology. Therefore, 8 times of information can be stored without expanding the physical area of the semiconductor. In addition, applying only the mirror bit technology to the structure results in the physical isolation of the right and left charges completely, eliminating the overlapping opportunity in the current distribution by both charges.

1 is a transistor structure used in the conventional and MLC method.

2 is a programming method used in the mirror bit method.

3 is a voltage-current characteristic of a transistor showing a two-bit memory state in the MLC and mirror bit schemes.

4 is a transistor configuration in which the floating gate is separated according to the present invention.

5 is a plan view of a transistor according to the present invention.

6 is a voltage-current characteristic of a transistor according to the present invention.

* mirror bit technology: MLC technology developed by AMD in the US to perform floating gate programming separately on the source and drain sides of transistors (www.amd.com)

<Explanation of symbols in Fig. 1, 2, 4, 5>

1: Control gate of transistor

2, 5: floating gate of transistor

3: source of transistor

4: drain of transistor

Claims (4)

A transistor structure comprising separating a floating gate of a semiconductor flash memory into two or more pieces. 2. The transistor structure of claim 1, wherein the transistor is divided into two at the source and drain sides. A flash memory applying mirror bit technology to the transistor structure of claim 2. Flash memory technology to increase the data integration by applying the conventional mirror bit and MLC technology to the transistor of claim 2.