KR20050003803A - 반도체 패키지의 서브스트레이트 - Google Patents
반도체 패키지의 서브스트레이트 Download PDFInfo
- Publication number
- KR20050003803A KR20050003803A KR1020030045304A KR20030045304A KR20050003803A KR 20050003803 A KR20050003803 A KR 20050003803A KR 1020030045304 A KR1020030045304 A KR 1020030045304A KR 20030045304 A KR20030045304 A KR 20030045304A KR 20050003803 A KR20050003803 A KR 20050003803A
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- solder mask
- reference mark
- semiconductor package
- wire bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H10W72/071—
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
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- H10W46/00—
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- H10W70/65—
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/049—Wire bonding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H10W46/301—
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- H10W46/601—
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- H10W72/075—
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- H10W72/50—
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- H10W72/536—
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- H10W72/5363—
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- H10W72/884—
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- H10W72/952—
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- H10W90/754—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/975—Substrate or mask aligning feature
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (4)
- 반도체 칩이 안착되고, 상기 반도체 칩의 외곽으로 본드핑거가 형성된 반도체 패키지의 서브스트레이트에 있어서,상기 서브스트레이트의 소정부에는 기준마크가 형성되고,상기 기준마크는 기준메탈과, 상기 기준메탈위로 도포되는 솔더마스크의 일부가 오픈된 개방부를 포함하는 것을 특징으로 하는 반도체 패키지의 서브스트레이트
- 제 1 항에 있어서,상기 기준메탈은 솔더마스크의 개방부에 의해 일부노출된 것을 특징으로 하는 반도체 패키지의 서브스트레이트
- 제 1 항에 있어서,상기 기준마크는 ''자 형태의 기준메탈과 ''자 형태의 솔더마스크 개방부를 포함하여 구성됨을 특징으로 하는 반도체 패키지의 서브스트레이트
- 제 1 항에 있어서,상기 기준마크는 적어도 1곳 내지 4곳 형성되며, 본드핑거라인의 모서리부에형성되는 것을 특징으로 하는 반도체 패키지의 서브스트레이트
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030045304A KR100546698B1 (ko) | 2003-07-04 | 2003-07-04 | 반도체 패키지의 서브스트레이트 |
| US10/884,082 US7030508B2 (en) | 2003-07-04 | 2004-07-01 | Substrate for semiconductor package and wire bonding method using thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030045304A KR100546698B1 (ko) | 2003-07-04 | 2003-07-04 | 반도체 패키지의 서브스트레이트 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20050003803A true KR20050003803A (ko) | 2005-01-12 |
| KR100546698B1 KR100546698B1 (ko) | 2006-01-26 |
Family
ID=33550283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030045304A Expired - Lifetime KR100546698B1 (ko) | 2003-07-04 | 2003-07-04 | 반도체 패키지의 서브스트레이트 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7030508B2 (ko) |
| KR (1) | KR100546698B1 (ko) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101333412B1 (ko) * | 2006-02-14 | 2013-11-28 | 닛토덴코 가부시키가이샤 | 배선 회로 기판 및 그 제조 방법 |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI243442B (en) * | 2004-12-14 | 2005-11-11 | Siliconware Precision Industries Co Ltd | Bond positioning method for wire-bonding process and substrate for the bond positioning method |
| JP4607612B2 (ja) * | 2005-02-09 | 2011-01-05 | 日東電工株式会社 | 配線回路基板およびその製造方法 |
| US20070290321A1 (en) * | 2006-06-14 | 2007-12-20 | Honeywell International Inc. | Die stack capacitors, assemblies and methods |
| US20080121413A1 (en) * | 2006-11-27 | 2008-05-29 | Cardona Sergio E | Method for manufacturing printed circuit boards |
| JP5990438B2 (ja) | 2012-09-13 | 2016-09-14 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| KR102084288B1 (ko) | 2012-11-05 | 2020-03-03 | 유니버시티 오브 플로리다 리서치 파운데이션, 아이엔씨. | 디스플레이의 휘도 보상 |
| NL2011575C2 (en) * | 2013-10-08 | 2015-04-09 | Besi Netherlands B V | Method for positioning a carrier with electronic components and electronic component produced with such method. |
| JP2016189499A (ja) * | 2016-08-12 | 2016-11-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| KR102271093B1 (ko) | 2021-01-25 | 2021-07-02 | 에스앤피티(주) | 반도체 패키징용 서브스트레이트 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3247544B2 (ja) * | 1994-05-19 | 2002-01-15 | 株式会社東芝 | 半導体装置 |
| US5998295A (en) * | 1996-04-10 | 1999-12-07 | Altera Corporation | Method of forming a rough region on a substrate |
| US5760484A (en) * | 1997-02-11 | 1998-06-02 | Mosel Vitelic Inc. | Alignment mark pattern for semiconductor process |
| US5895967A (en) * | 1997-07-07 | 1999-04-20 | Texas Instruments Incorporated | Ball grid array package having a deformable metal layer and method |
| JP3644859B2 (ja) * | 1999-12-02 | 2005-05-11 | 沖電気工業株式会社 | 半導体装置 |
| JP4361658B2 (ja) * | 2000-02-14 | 2009-11-11 | 富士通マイクロエレクトロニクス株式会社 | 実装基板及び実装方法 |
| JP3677426B2 (ja) * | 2000-02-21 | 2005-08-03 | Necエレクトロニクス株式会社 | 位置合わせ精度計測マーク |
| JP4407785B2 (ja) * | 2000-10-24 | 2010-02-03 | ソニー株式会社 | 半導体装置及びその検査方法 |
| KR100384834B1 (ko) * | 2001-03-30 | 2003-05-23 | 주식회사 하이닉스반도체 | 다중 기판 상에 형성되는 반도체 장치 및 그 제조 방법 |
| WO2002082540A1 (en) * | 2001-03-30 | 2002-10-17 | Fujitsu Limited | Semiconductor device, method of manufacture thereof, and semiconductor substrate |
| JP2002368156A (ja) * | 2001-06-11 | 2002-12-20 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| US6668449B2 (en) * | 2001-06-25 | 2003-12-30 | Micron Technology, Inc. | Method of making a semiconductor device having an opening in a solder mask |
-
2003
- 2003-07-04 KR KR1020030045304A patent/KR100546698B1/ko not_active Expired - Lifetime
-
2004
- 2004-07-01 US US10/884,082 patent/US7030508B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101333412B1 (ko) * | 2006-02-14 | 2013-11-28 | 닛토덴코 가부시키가이샤 | 배선 회로 기판 및 그 제조 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100546698B1 (ko) | 2006-01-26 |
| US7030508B2 (en) | 2006-04-18 |
| US20050001299A1 (en) | 2005-01-06 |
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