KR20040094179A - Gate-all-around carbon nanotube - field effect transistor - Google Patents

Abstract

PURPOSE: A carbon nano tube FET(field effect transistor) is provided to maximize an electric field effect of a gate by using a cylindrical carbon nano tube as a channel and by making a channel region completely surrounded by the gate. CONSTITUTION: A substrate(10) is prepared. A carbon nano tube(CNT) is disposed in parallel with the plane of the substrate. A channel(11) is formed by one of a bundle of the carbon nano tubes. A source and a drain are electrically connected to both ends of the channel. A gate(20) is formed in such a way that the channel is surrounded by the gate. A gate insulation layer(21) is interposed between the gate and the channel.

Description

Carbon nanotube field effect transistor surrounded by gate and its manufacturing method {Gate-all-around carbon nanotube-field effect transistor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal carbon nanotube transistor and a method for manufacturing the same. Specifically, a CNT-FET using a carbon nanotube surrounded by a gate and a gate insulating film as a channel. Field effect transistor) and a method of manufacturing the same.

As the integration of semiconductor devices has progressed rapidly, scaling down, or scaling, of classical CMOS semiconductor devices has reached its limit. Scaling reduces the width and length of gate electrodes, minimizes the isolation area between unit elements, and increases the thickness and junction depth of the gate insulation layer for high integration, high performance, and low power. In the direction of making the thinner. However, all of these attempts must essentially guarantee gate control, so ultimately the transistor's on-cuurent off-current ratio should be maximized. According to the 2001 Roadmap of the International Technology Roadmap for Semiconductors (ITRS), a UTB-FD ultra-thin body fully depleted using a silicon-on-insulator (SOI) substrate to improve drive current. SOI Transistor) [ S. Fung et al., IEDM-2001, p. 629 ], Band-engineered transistors that enhance electron mobility using strained Si channels [ K. Rim, et al., VLSI 2002 page 12 ]. In addition, a vertical transistor [ Oh, et al., IEDM-2000, page 65 ], Fin-FET [ Hisamoto, et al., IEEE Trans. On-electron Device 47, 2320 (2000) ], double-gate transistors [ Denton, et al., IEEE Electron Device Letters 17, 509 (1996) ] have been attempted a variety of three-dimensional silicon transistors. However, in the three-dimensional gate transistor, there is a process difficulty in modifying the gate structure in order to maximize the field effect of the gate. In particular, the silicon used as the channel has a complicated three-dimensional gate structure process because a silicon substrate or a silicon film whose three-dimensional structure is determined by deposition and patterning processes must be used.

Recently, a transistor using carbon nanotubes as a channel has been proposed as a way to overcome the problem of silicon devices having reached the limit of scaling, and carbon nanotubes that operate at room temperature such as Tans and Deckers have been proposed. Transistors have been reported [ Tans, et al., Nature 393, 49 (1998) ]. In particular, the horizontal growth technology of carbon nanotubes [ Hongjie Dai, et al., Appl. Phys. Lett. 79, 3155 (2001) ] and techniques for vertically growing carbon nanotubes from nanopores [ Choi, et al., Adv. Mater. 14, 27 (2002); Duesberg, et al., Nano Letters ] have been developed, and the research to apply them to the device is being actively conducted. In this research, development of a structure for securing the gate control force of a carbon nanotube transistor and a method of easily manufacturing the same is one problem to be solved.

Accordingly, the present invention provides a "gate-all-around CNT transistor" and a method of manufacturing the same, which improve gate controllability and facilitate manufacturing since the gate completely surrounds the carbon nanotube channel. The purpose is to provide.

1A is a diagram illustrating the concept of a transistor according to the present invention.

1B is a longitudinal cross-sectional view of a transistor according to the present invention conceptually shown in FIG. 1A.

2A to 2D are schematic perspective views of a carbon nanotube and carbon nanotube bundle applied to a transistor of the present invention.

3 is a schematic cross-sectional view of an enclosed gate carbon nanotube transistor according to the present invention.

4A to 4K are manufacturing process diagrams of the transistor according to the present invention.

Figure 5a shows a distribution diagram of the electric potential around the CNT of the transistor according to the present invention, Figure 5b shows the magnitude of the electrical potential of the CNT surface.

In order to achieve the above object, the transistor of the present invention is:

A substrate;

Channels by one or more carbon nanotubes disposed side by side in the plane of the substrate;

Source and drain electrically connected at both ends of the channel;

A gate provided to surround the channel;

And a gate insulating layer interposed between the gate and the channel.

According to a preferred embodiment of the transistor of the present invention,

A buried layer further comprising a first layer on the lower side of the carbon nanotubes and a second layer on the upper side of the carbon nanotubes;

The carbon nanotubes are buried between the first layer and the second layer.

According to a more preferred embodiment of the transistor according to the present invention, a well corresponding to the channel is formed in the buried layer,

The gate insulating layer is formed on the inner wall of the well and the surface of the carbon nanotubes exposed from the well.

In the transistor according to the present invention, it is preferable that both sides of the buried layer has a side surface at which the carbon nanotubes are exposed.

In addition, it is preferable that a source and a drain connected to both ends of the carbon nanotubes are formed on the side of the buried layer.

In the transistor of the present invention, the side of the buried layer is more preferably formed to be inclined, and the catalyst layer used to grow the carbon nanotubes is preferably formed on the side of the buried layer.

In order to achieve the above object, a method of manufacturing a transistor according to the present invention is:

A) forming a first buried layer having electrical insulation on the substrate;

B) forming a sacrificial layer for forming a cavity for carbon nanotube growth on the first buried layer;

C) forming a second buried layer having electrical insulation on the sacrificial layer and the first buried layer;

D) etching the laminate structure into the first buried layer, the sacrificial layer and the second buried layer to form two opposite sides each having exposed ends of the sacrificial layer;

E) forming a conductive layer for source and drain on the surface of the laminate comprising the two sides;

F) forming a well penetrating a middle portion of the sacrificial layer from an upper portion of the laminated structure;

G) supplying an etchant through the well to remove the sacrificial layer and forming a cavity in a portion where the sacrificial layer is removed;

H) growing carbon nanotubes in the cavity;

I) forming a gate insulating layer on the exposed portion of the carbon nanotubes in the well;

G) forming a gate material on the gate insulating layer;

K) patterning the conductive material and the gate material to form a source and a drain electrically contacting both ends of the carbon nanotubes and a gate surrounding an intermediate portion of the carbon nanotubes.

In the transistor of the present invention and a method of manufacturing the same, the buried layer is preferably formed of borosilicate glass (BSG).

Further, in the method of manufacturing a transistor of the present invention, it is more preferable to form a gate insulating layer on the inner wall and the bottom of the well in the step of forming the gate insulating layer, the gate and gate insulating layer is a chemical vapor deposition method Or it is preferable to form by the atomic layer deposition method.

In addition, in the method of manufacturing a transistor of the present invention, both sides of the buried layer is inclined to form an effective source and drain, and the steps d) and e) to form carbon nanotubes having good crystallinity. It is preferable to further comprise the step of forming a catalyst layer on the side of the buried layer d) -1).

Carbon nanotubes used as a channel in the transistor of the present invention has the advantage that doping process is not necessary and has the advantage that electron mobility is superior to silicon due to the characteristics of the material.

FIG. 1A illustrates a structural concept of a transistor according to the present invention using a cylindrical carbon nanotube as a channel, and FIG. 1B is a longitudinal cross-sectional view thereof.

As shown in FIGS. 1A and 1B, a portion of the carbon nanotube CNT covered by the gate 20 is a channel region (hereinafter referred to as channel 11) in which an electric field is formed. The non-overlapping portions are the source region 12a and the drain region 13a as simple electrical paths. That is, the channel 20 and the source and drain regions on both sides of the carbon nanotube are defined by the gate 20 surrounding the middle portion of the carbon nanotubes. A gate insulating layer 21 is interposed between the gate 20 and the channel.

In the transistor according to the present invention having the structure as described above, since the gate completely surrounds the channel region as shown in FIG. 1B, an electric field can be effectively formed in the channel by the gate 20, thus maximizing its effect. have. In addition, since the channel 11 is completely surrounded by the gate 20, the depletion layer formed by the electric field is isolated from the substrate, thereby maximizing Ion / Ioff.

The carbon nanotubes may have a known form as shown in FIGS. 2A to 2D according to a manufacturing method. Figure 2a is a single-walled carbon nanotube (Sigle-walled carbon nanotube), Figure 2b is a multi-walled carbon nanotube (multi-walled carbon nanotube), Figure 2c is a plurality of single-layered carbon nanotubes are carbon in a circular bundle state A nanotube bundle is shown, and FIG. 2D shows a carbon nanotube array in which a plurality of single-walled carbon nanotubes are arranged in a planar state.

In the present invention, a carbon nanotube array arranged in a planar manner is preferably used as the channel material as shown in FIG. 2D.

3 is a schematic cross-sectional view of a transistor according to the present invention. Referring to FIG. 3, carbon nanotubes (CNTs) used as channels on the substrate 1 are arranged side by side on the plane of the substrate 10. The channel 11, which is an intermediate portion of the carbon nanotubes CNT, is surrounded by the gate 20, and a gate insulating layer 21 is formed between the gate 20 and the channel 11. The remaining portion of the carbon nanotubes (CNT) is protected by the buried layer 30 by an insulating layer material for protecting and supporting the carbon nanotubes (CNT). The buried layer 30 includes a first layer 31 on the lower side of the carbon nanotubes (CNT) and a second layer 32 on the upper side of the carbon nanotubes (CNT). As such, the buried layer 30 in which the carbon nanotubes are embedded has side surfaces 30a and 30b at which both ends of the carbon nanotubes CNT are exposed, and the carbon nanotubes CNT are formed on each of the side surfaces 30a and 30b, respectively. A source 12 and a drain 13 are formed which are electrically connected to the. Preferably, both side surfaces 31a and 31b of the buried layer 30 are formed to be inclined so that the source 12 and the drain 13 can be easily formed.

Meanwhile, a gate insulating layer 21 is formed between the gate 20 and the channel 11, and in particular, the gate 20 completely covers an intermediate portion of the channel 11, that is, the carbon nanotubes (CNTs). In this case, the gate 20 is separated from the first layer 31 of the buried layer 30 as well as the channel 11 by the gate insulating layer 21. have. The form of the gate insulating layer 21 is in accordance with one feature of the manufacturing method according to the present invention described below, and the structure in which the buried layer 30 and the lower portion of the gate 20 are isolated is not technical intention. In addition, catalyst layers (not shown) may exist on both side surfaces 30a and 30b of the buried layer 30. This catalyst layer is an optional element used for growing carbon nanotubes, and it is possible to grow carbon nanotubes without this catalyst layer, but the crystallinity (quality) of carbon nanotubes grown without a catalyst layer is the Inferior to crystalline.

As described above, since the gate 20 has a structure completely covering the middle portion of the channel 11, that is, the carbon nanotubes (CNTs), the electric field effect on the channel is maximized. In addition, since the channel is completely surrounded by the gate, a fully depletion layer is obtained by the gate electric field, thereby maximizing Ion / Ioff.

Hereinafter, an embodiment of a method of manufacturing a surrounding gate carbon nanotube transistor according to the present invention will be described in detail with reference to the accompanying drawings. In the following description of the process, a known technology is not described in a description of a semiconductor device manufacturing method or a related film formation method, which means that the technical scope of the present invention is not limited by these known technologies.

As shown in FIG. 4A, the first layer 31 and the second layer 32 of the above-described buried layer 30 and the sacrificial layer 40 of the object therebetween are disposed on the substrate 10. Form sequentially. Here, the first layer 31 and the second layer 32 constituting the buried layer 30 are BSG (borosilicate glass), and the sacrificial layer 40 is silicon oxide (SiO ₂ ). Here, the sacrificial layer 40 is a portion in which carbon nanotubes are grown in a process to be described later. Therefore, the sacrificial layer 40 is entirely deposited on the first layer 31 and then predetermined. Pattern to an object of width.

As shown in FIG. 4B, the laminate is patterned, but both ends of the sacrificial layer 40 are exposed to both side surfaces 30a and 30b of the structure inclined by the laminate.

As shown in FIG. 4C, a catalyst layer 50 for growing carbon nanotubes is deposited on the surface of the entire structure including both side surfaces 30a and 30b.

As shown in FIG. 4D, the conductive material 60 for the source and drain pads is deposited on the entire structure and then the top surface is polished to planarize it.

As shown in FIG. 4E, a well 60a penetrating the sacrificial layer 40 is formed at the center portion of the structure. The well 60a extends below the sacrificial layer 40 and also penetrates the first layer 31 to reach the surface of the substrate.

As shown in FIG. 4F, an etchant is supplied through the well 60a to remove the sacrificial layer 40 existing between the first layer 31 and the second layer 32. As such, when the sacrificial layer 40 is removed, the inner surface of the catalyst layer 50 formed on the inclined side surfaces 30a and 30b of the structure is exposed into the cavity 40a.

As shown in FIG. 4G, carbon nanotubes (CNTs) are grown in a direction parallel to the substrate 10 in the cavity 40a from which the sacrificial layer 40 is removed. At this time, since both inner portions of the cavity 40a are exposed to the inner surface of the catalyst layer 50, growth of carbon nanotubes starts from the surface of the catalyst layer 50 inside the cavity 40a.

As shown in FIG. 4H, an insulating layer 21a made of a dielectric material, preferably a high dielectric material, is deposited on the entire surface of the structure by chemical vapor deposition or atomic layer deposition. The insulating layer 21a is a layer for obtaining a gate insulating layer, and the surface of the conductive material 60 on the substrate 10 and the bottom and inner walls of the well 60a, and the carbon nanotubes exposed in the well 60a ( CNT) is formed throughout the surface. What is important here is that the carbon nanotube (CNT) exposed surface must be completely covered by the insulating layer 21a. The insulating layer 21a is preferably silicon oxide (SiO ₂ ).

As shown in FIG. 4I, a gate material layer 20a is formed on the stacked structure on the substrate 10. In the formation of the gate material layer 20a, a chemical vapor deposition method having excellent step coverage, and preferably an atomic layer deposition method, is applied to form a successful gate in the hole.

As shown in FIG. 4J, the source 12 and the drain 13 are polished from the surface of the laminated structure to the surface of the second layer 32 of the buried layer 30 so that the conductive material layer 60 While forming a gate 20 separated from the gate material layer 20a.

As shown in FIG. 4K, electrical pads 12b, 13b, and 20b are formed in the source 12, the drain 13, and the gate 20 to obtain a desired transistor.

5 is an embodiment of a calculation result of electrical potential for a transistor according to the present invention. Here, the length of the CNT is set to 1um and the diameter of the CNT is set to 40nm, and the insulating layer surrounding the CNT is silicon oxide and its thickness is set to 20nm. At this time, the gate voltage was 5V. This figure is the value for an Example, and has no absolute meaning. In the transistor according to the present invention illustrated in FIG. 3, it can be seen that a local electric field is formed around the CNT, while the influence of the gate and the source or drain node is not so great. As shown in FIG. 5B, the potential distribution of the surface of the CNT is changed according to the position of the CNT. The portion where the gate is located is given a maximum value of 4.5V when the gate voltage is 5V, and gradually decreases toward both ends thereof to zero at both ends. zero).

As described above, according to the present invention, the cylindrical carbon nanotube is used as a channel in the transistor, and the gate completely surrounds the channel region, thereby maximizing the field effect of the gate. In addition, since the depletion layer formed on the completely enclosed channel becomes a kind of a fully depletion layer, Ion / Ioff can be maximized. In terms of process, the cylindrical channel region, which cannot be easily implemented in silicon, can be easily manufactured by a carbon nanotube deposition process.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be defined only in the appended claims.

Claims (17)

A substrate; A channel by any one of carbon nanotubes and carbon nanotube bundles disposed side by side in the plane of the substrate; Source and drain electrically connected at both ends of the channel; A gate provided to surround the channel; And a gate insulating layer interposed between the gate and the channel. The method of claim 1, A buried layer further comprising a first layer on the lower side of the carbon nanotubes and a second layer on the upper side of the carbon nanotubes; The carbon nanotube field effect transistor surrounded by a gate, characterized in that the carbon nanotube is buried between the first layer and the second layer. The method of claim 2, The well layer corresponding to the channel is formed in the buried layer, And a gate insulating layer formed on the inner wall of the well and the surface of the carbon nanotube exposed from the well. The method of claim 2, Both sides of the buried layer has a side that the carbon nanotubes are exposed, A carbon nanotube field effect transistor surrounded by a gate, wherein a source and a drain connected to both ends of the carbon nanotube are formed on a side of the buried layer. The method of claim 3, wherein Both sides of the buried layer has a side that the carbon nanotubes are exposed, A carbon nanotube field effect transistor surrounded by a gate, wherein a source and a drain connected to both ends of the carbon nanotube are formed on a side of the buried layer. The method of claim 4, wherein The side of the buried layer is carbon nanotube field effect transistor surrounded by a gate, characterized in that formed inclined. The method of claim 4, wherein A carbon nanotube field effect transistor surrounded by a gate, characterized in that a catalyst layer used to grow the carbon nanotubes is formed on the side of the buried layer. The method of claim 6, A carbon nanotube field effect transistor surrounded by a gate, characterized in that a catalyst layer used to grow the carbon nanotubes is formed on the side of the buried layer. The method of claim 2, The buried layer is a carbon nanotube field effect transistor surrounded by a gate, characterized in that formed of borosilicate glass (BSG). The method of claim 3, wherein The well of the buried layer is a carbon nanotube field effect transistor surrounded by a gate, characterized in that extending to the surface of the substrate. A) forming a first buried layer having electrical insulation on the substrate; B) forming a sacrificial layer for forming a cavity for carbon nanotube growth on the first buried layer; C) forming a second buried layer having electrical insulation on the sacrificial layer and the first buried layer; D) etching the laminate structure into the first buried layer, the sacrificial layer and the second buried layer to form two opposite sides each having exposed ends of the sacrificial layer; E) forming a conductive layer for source and drain on the surface of the laminate comprising the two sides; F) forming a well penetrating a middle portion of the sacrificial layer from an upper portion of the laminated structure; G) supplying an etchant through the well to remove the sacrificial layer and forming a cavity in a portion where the sacrificial layer is removed; H) growing carbon nanotubes in the cavity; I) forming a gate insulating layer on the exposed portion of the carbon nanotubes in the well; G) forming a gate material on the gate insulating layer; Patterning the conductive material and the gate material to form a source and a drain electrically contacting both ends of the carbon nanotubes and a gate surrounding an intermediate portion of the carbon nanotubes; A method for producing a carbon nanotube field effect transistor surrounded by a film. The method of claim 11, And the first and second buried layers are formed of borosilicate glass (BSG). The method of claim 12, And forming a gate insulating layer on the inner wall and the bottom of the well in the forming of the gate insulating layer, wherein the carbon nanotube field effect transistor is surrounded by the gate. The method of claim 13, The method of manufacturing a carbon nanotube field effect transistor, wherein the gate insulating layer is formed by any one of chemical vapor deposition and atomic layer deposition. The method of claim 13, A method of manufacturing a carbon nanotube field effect transistor surrounded by a gate, characterized in that the inclined sides of the buried layer. The method of claim 11, A method of manufacturing a carbon nanotube field effect transistor surrounded by a gate, characterized in that it further comprises the step of forming a catalyst layer on the side of the buried layer D) -1) between step d) and d). The method of claim 11, The method of manufacturing a carbon nanotube field effect transistor surrounded by a gate, characterized in that the gate material is formed by any one of chemical vapor deposition and atomic layer deposition in the forming of the gate.