KR20040074282A - Interpolator for orthogonal frequency division multiplexing receiver and transmitter using intermediate frequency modulation - Google Patents

Abstract

PURPOSE: An interpolator using intermediate frequency modulation of an OFDM(Orthogonal Frequency Division Multiplexing) modulation transceiver is provided to simplify a circuit structure of a transmitter block. CONSTITUTION: An interpolation filter(302) receives a baseband signal comprising real data and imaginary data, and then filters them through a number of delay units. A multiplier(303) performs an intermediate frequency transform by multiplying a signal being output according to a phase from the interpolation filter by a tap coefficient of a proper sign. A switching part(301) switches a phase and control bit to control the interpolation filter and the multiplier. And an adder(304) adds data being output from the multiplier.

Description

INTERPOLATOR FOR ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING RECEIVER AND TRANSMITTER USING INTERMEDIATE FREQUENCY MODULATION}

The present invention relates to an interpolator using an intermediate frequency modulation of an orthogonal frequency multiplexing transceiver, and in particular, reduces unnecessary computation by oversampling to oversample an input signal, and reduces the unnecessary data when the intermediate frequency is modulated by f_s / 4. The present invention relates to an interpolator using intermediate frequency modulation of an orthogonal frequency multiplexing transceiver to simplify the circuit structure of a transmitter by reducing the number of multipliers by avoiding unnecessary zero multiplication for imaginary data.

Recently, due to the demand for wireless broadband data communication, there is an increasing demand for a transceiver of the IEEE 802.11a Orthogonal Frequency Division Multiplexing (OFDM) scheme.

A typical IEEE 802.11a transceiver has a configuration as shown in FIG. 1, wherein the transmitting end has a baseband having a sampling rate of 20 MHz modulated by an inverse fast fourier transform (IFFT) 106. In order to process the band signal into a passband, it is necessary to oversample the sample of the baseband, which is used by the interpolator 109 after the inverse fast Fourier transformer 106. do.

At this time, the interpolator includes a filter, which requires a large number of filter taps due to the signal spectrum of 802.11a, which greatly increases the complexity of the transmitter.

That is, since the interpolator is used to oversample the baseband signal, it is necessary to increase the sampling rate and minimize distortion of the baseband signal. Therefore, a finite impulse response (FIR) filter, in which the linearity of the filter is maintained, is widely used for the interpolation filter of the interpolator in order to minimize the distortion of the magnitude and phase of the signal before and after passage.

FIG. 2 is a block diagram showing the structure of a conventional interpolator, and includes a zero value insertion unit 201 for inserting an oversample having zero values for oversampling real data and imaginary data at predetermined intervals, respectively, with respect to an input signal. 202, FIR filter units 203 to 208 for filtering the oversampled signal, and an RF modulator 209 for modulating the filtered signal in a high frequency band.

In this case, the FIR filter unit delays the oversampled signal sequentially by a predetermined time through a predetermined delay element D, and delay coefficients 203 and 204, respectively, and coefficients h (0) to ... in the input data. multiplication operation units 205 and 206 for multiplying h (k), and addition operation units 207 and 208 for accumulating and summing outputs of the multiplication operation units.

Referring to the operation of the conventional interpolator configured as described above are as follows.

First, in the zero value inserting units 201 and 202, when the sample interval of the signal is T, and oversamples it at an interval of T / 4, an oversample having three (4-1) zero values is inserted. The oversampled signals are input to the delay element units 203 and 204 and sequentially delayed for a predetermined time through n delay elements, and the delayed signals are respectively input to the multiplication operation units 205 and 206 to n + 1 units. The multiplier multiplies each coefficient (h (0) to h (k)) and adds and outputs the multiplied signals by the add operation units 207 and 208.

The basic structure of the FIR filter which performs the above operation is composed of a delay element, a multiplier, and an adder, and the number of taps is adjusted according to its use.

However, while the FIR filter has less distortion in size and phase, the number of multipliers is increased in proportion to the number of taps of the filter, and as a result, the system complexity of the interpolator is greatly increased.

Accordingly, the present invention has been made to solve the above-mentioned problems, and reduces unnecessary operations by oversampling to oversample the input signal, and real data and imaginary number when f_s / 4 is modulated by intermediate frequency. The purpose of the present invention is to provide an interpolator using intermediate frequency modulation of an orthogonal frequency multiplexing transceiver to simplify the circuit structure of a transmitting end by reducing the number of multipliers by not performing unnecessary zero multiplication on data.

The present invention for achieving the above object, an interpolation filter unit for receiving a baseband signal consisting of real and imaginary data, and filtering through a plurality of delay; A multiplier for multiplying the signal output according to the phase from the interpolation filter by the tap coefficient of an appropriate sign to convert the intermediate frequency; A switching unit for switching phase and control bits for controlling the interpolation filter unit and the multiplier; And an adder for summing and outputting data output from the multiplier.

1 is a block diagram showing the configuration of a typical IEEE 802.11a transceiver.

Figure 2 is a block diagram showing the configuration of a conventional general interpolator.

3 is a block diagram showing a configuration of an interpolator according to the present invention.

* Description of the symbols for the main parts of the drawings *

301: switching unit 302: interpolation filter unit

303: multiplication unit 304: adder

D: Delay MUX: Multiplexer

The interpolation filter according to the present invention reduces unnecessary computation by inserting an oversample having a zero value for oversampling the input signal at predetermined intervals, and by f_s / 4 (where f_s is a sampling frequency). ), It reduces the number of multipliers for unnecessary zero multiplication for real and imaginary data.

In general, the transmitter baseband signal of an IEEE 802.11a transceiver is composed of a complex signal, and since the baseband spectrum is symmetric around 0 Hz, an interpolation filter requires a real low pass FIR filter with a symmetric frequency response. Shall be. That is, as shown in FIG. 2, an independent operation is required to multiply the tap coefficients of the real FIR filter by the real part and the imaginary part of the baseband signal.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described.

Figure 3 is a block diagram showing the configuration of an interpolator according to the present invention, an interpolation filter unit 302 for receiving a baseband signal consisting of real and imaginary data and filtering through a plurality of delayers (D), A multiplier 303 for multiplying the signal output according to the phase from the interpolation filter unit 302 by an appropriate sign and converting the intermediate frequencies, and a phase for controlling the interpolation filter unit 302 and the multiplier 303. And a switching unit 301 for switching the control bits b ₀ b ₁ , and an adder 304 for summing and outputting data output from the multiplier 303.

Here, the interpolation filter unit 302 comprises a plurality of serially connected delay units (D) in four rows, in which one row and three rows receive the same real data from each row of the delay lines, and two and four rows. Are multiple plural multiplexers (MUX) for selectively outputting data output from each delay stage of each row in response to the control bits b ₀ b ₁ switched by the switching unit 301. ).

In this case, since the retarder D of the interpolation filter unit 302 does not insert zero oversampled data for oversampling, the number of retarders can be reduced by that amount.

In addition, the multiplier 303 selectively outputs corresponding tap coefficients h (0) to h (N−1) corresponding to the control bits b ₀ b ₁ switched by the switching unit 301. And a plurality of multipliers 303a to 303N for multiplying and outputting the tap coefficients output from the multiplexer MUX and the data output from the interpolation filter unit 302.

The control bit b ₀ b ₁ output by the switching of the switching unit 301 is used as a control bit of a phase and a multiplexer (MUX) for selecting a delay row of the interpolation filter unit 302 and multiplies. It is used as a control bit of the multiplexer (MUX) for selecting tap coefficients of the section 303.

Hereinafter, the operation and operation of the present invention by the above configuration will be described.

The present invention changes the phase of the multiplexer (MUX) at a rate four times faster than the original signal to oversample the baseband signal by four times the original signal. That is, in Phase 1, the value when the control bit (b ₀ b ₁ ) of the multiplexer (MUX) is 00 is used as the filter tap coefficient. In Phase 2, the value when 01 is used, and in Phase 3, the value when 10 is used. In phase 4, the value at 11 is used as the filter tap coefficient.

The input data of the filter at this time uses a value of 00 for phase 1, 01 for phase 2, 10 for phase 3, and finally phase 4, similarly to selecting the filter tap coefficient from the multiplexer (MUX). Is a value of 11, and the sum of the tap coefficients in each phase and the result of the selected input data becomes the output of the interpolator.

For example, '1, 2, 3, 4, 5, ...' is input as real part data for the delay unit D of the interpolation filter 302, and as imaginary part data. When '9, 8, 7, 6, 5, ...' is input, the switching unit 301 operates at a speed four times faster than the input so that '00, 01, 10, 11, 00, 01, 10, 11, ... 'in order. That is, four operations occur sequentially for one input.

First, when the switching unit 301 indicates 00, the inputs of the respective delayers D become '1, 0, 0, 0, ...' in the case of the delay unit of the first row, For delays, '9, 0, 0, 0, ...', the delay in the third row is '1, 0, 0, 0, ...', as in the delay in the first row, the delay in the fourth row The phase becomes '9, 0, 0, 0, ...' as with the delay of the second row. At this time, the control bit (b ₀ b ₁ ) of the multiplexer (MUX) of the interpolation filter is 00, so that the delay output of the 00 stage (output of the delays of the first row) is' 1, 0, 0, 0, 0, ... 'is determined by the output of the multiplexer (MUX).

Next, the multiplexer MUX for applying tap coefficients to each of the multipliers 303a to 303N of the multiplier 303 has a tap coefficient when the switching control bit b ₀ b ₁ of the switching unit 301 is 00. Let h (0) 1 and h (4) 5, h (8) 9, ... be selected.

Next, the outputs of the delay unit D output through the multiplexer MUX of the interpolation filter 302 and the tap coefficients output through the multiplexer MUX of the multiplier 303 are multipliers 303a to 303N. Multiplication operation (1X1, 0X5, 0X9, ...) becomes '1, 0, 0, 0, 0, ...', respectively, and the sum of the final operation result of each multiplier through the adder 304 1 is output.

In this case, when the switching unit 301 indicates 01, the input values of the delay units D of the interpolation filter 302 are selected as '9, 0, 0, 0, 0, ...', which are 01 steps, and are multiplied. As the tap coefficients applied to the multiplier through the multiplexer MUX of the unit 303, '2, 6, 10, 14, 18, ...' corresponding to 01 is selected. Therefore, if the multiplier operation (9X2, 0X6, 0X10, 0X14, ...) is performed through the multipliers 303a to 303N, the delay output and the tap coefficient selected in step 01 are respectively '18, 0, 0, 0 '. , 0, ... ', and 18 is output as the sum of the final calculation results of each multiplier through the adder 304.

In this case, when the switching unit 301 indicates 01, the input values of the delay units D of the interpolation filter 302 are selected in step 10, '1, 0, 0, 0, 0, ...', and multiplication is performed. As the tap coefficients applied to the multiplier through the multiplexer MUX of the unit 303, '3, 7, 11, 15, ...' corresponding to 10 is selected. Accordingly, if the multiplier operation (1X3, 0X7, 0X11, ...) is performed through the multipliers 303a to 303N, the delay output and the tap coefficient selected in step 01 are respectively '3, 0, 0, 0,'. ... ', 3 is output as the sum of the result of the final operation of each multiplier through the adder 304.

Finally, when the switching unit 301 indicates 11, the input values of the delay units D of the interpolation filter 302 are selected as '9, 0, 0, 0, ...', which are 11 steps, and the multiplier unit. A tap coefficient applied to the multiplier through the multiplexer MUX of 303 is selected as '4, 8, 12, 16, 20, ...' corresponding to 11. Therefore, when the multiplier operation (9X4, 0X8, 0X12, ...) is performed through the multipliers 303a to 303N, the delay output and the tap coefficient selected in step 01 are respectively '36, 0, 0, 0, '. 36 'is output as the sum of the final calculation results of each multiplier through the adder 304.

This time, the new inputs 2 (real) and 8 (imaginary) of the delays come in, so the outputs of the uppermost delays are '2, 1, 0, 0, 0, 0, ...' The delays in the first row are '8, 9, 0, 0, 0, 0, ...', and the delays in the third row are '2, 1, 0, 0, 0, 0, ...', The delays of the first row become '8, 9, 0, 0, 0, ...'.

In this case, when the switching unit 301 indicates 00, the input values of the delay units D of the interpolation filter 302 are 00, and '2, 1, 0, 0, 0, 0, ...' is selected. , '1, 5, 9, 13, ...' corresponding to 00 is selected as the tap coefficient applied to the multiplier through the multiplexer MUX of the multiplier 303. Therefore, if the multiplier operation (2X1, 1X5, 0X9, 0X13, ...) is performed through the multipliers 303a to 303N, the delay output and the tap coefficient selected in step 01 are respectively '2, 5, 0, 0'. , ... ', and 7 (2 + 5) is output as the sum of the final calculation result of each multiplier through the adder 304.

In this case, when the switching unit 301 indicates 01, the input values of the delay units D of the interpolation filter 302 are selected as '8, 9, 0, 0, 0, ...', which are 01 steps, and are multiplied. As the tap coefficients applied to the multiplier through the multiplexer MUX of the unit 303, '2, 6, 10, 14, ...' corresponding to 01 is selected. Therefore, when the multiplier operation (8X2, 9X6, 0X10, 0X14, ...) is performed through the multipliers 303a to 303N, the delay output and the tap coefficient selected in step 01 are respectively '16, 54, 0, 0 '. ', 70 (16 + 54) is output as the sum of the final calculation result of each multiplier through the adder 304.

In this case, when the switching unit 301 indicates 10, the input values of the delay units D of the interpolation filter 302 are selected in step 10, '2, 1, 0, 0, 0, ...', and the multiplication is performed. As the tap coefficients applied to the multiplier through the multiplexer MUX of the unit 303, '3, 7, 11, 15, 19, ...' corresponding to 01 is selected. Therefore, if the multiplier operation (2X3, 1X7, 0X11, 0X15, 0X19, ...) of the delay output and the tap coefficient selected in step 10 is performed through the multipliers 303a to 303N, respectively, '6, 7, 0' , 0, 0, ... ', and 13 (6 + 7) is output as the sum of the final calculation results of each multiplier through the adder 304.

Next, when the switching unit 301 indicates 11, the input values of the delay units D of the interpolation filter 302 are selected by '8, 9, 0, 0, 0, 0, ...', which are 11 steps. As a tap coefficient applied to the multiplier through the multiplexer MUX of the multiplier 303, '4, 8, 12, 16, 20, ...' corresponding to 01 is selected. Therefore, if the multiplier operation (8X4, 9X8, 0X12, 0X16, 0X20, ...) is performed through the multipliers 303a to 303N, the delay output and the tap coefficient selected in step 10 are respectively '32, 76, 0 '. , 0, 0, ... ', and 109 (32 + 76) is output as the sum of the final calculation results of each multiplier through the adder 304. Hereinafter, the same process is repeated for other input data.

Meanwhile, referring to the filter tap coefficients multiplied by the multiplier in the configuration of FIG. 3, in the case of 01 in phase 2 and 10 in phase 3, the tap coefficient has a negative value, which is an intermediate frequency IF. When modulating by f_s / 4, the real part is multiplied by 1,0, -1,0, and the imaginary part is multiplied by 0,1,0, -1 and the sum of these results is output. Only the multiplied tap coefficient is used. In phase 2, only the tap coefficient multiplied by 1 in the imaginary part is used, but the negative sign is obtained due to the product of the imaginary signal and the imaginary one.

In phase 3, only the tap coefficient multiplied by -1 of the real part is used. In phase 4, the tap coefficient multiplied by -1 of the imaginary part is used, but the sign has a positive value due to the product of the imaginary signal and the imaginary -1. Due to

Therefore, when the intermediate frequency modulation is performed at the f_s / 4 frequency, a multiplier of 8 times or less of the existing interpolation filter may be reduced.

As described above, the interpolator using the intermediate frequency modulation of the orthogonal frequency multiplexing modulation transceiver of the present invention reduces unnecessary operation by the oversample inserted to oversample the input signal, and real data if the intermediate frequency is modulated by f_s / 4. By reducing the number of multipliers by avoiding unnecessary zero multiplication operations on the imaginary data, the circuit structure of the transmitting end is simplified.

In addition, in the present invention, when IF modulation is performed on a supersampled signal at a quarter of the oversample frequency, the multiplication operation reduced to a quarter level can be attenuated back to a half level. The multiplication operation can be reduced to 8 levels, which greatly reduces the transmitter complexity due to the use of the FIR filter, thereby improving the efficiency of the transmitter design.

Claims (4)

An interpolation filter unit for receiving a baseband signal consisting of real and imaginary data and filtering the plurality of delayers; A multiplier for multiplying the signal output according to the phase from the interpolation filter by the tap coefficient of an appropriate sign to convert the intermediate frequency; A switching unit for switching phase and control bits for controlling the interpolation filter unit and the multiplier; And an adder for summing and outputting data output from the multiplier. An interpolator using intermediate frequency modulation of an orthogonal frequency multiple modulation transceiver. 2. The interpolation filter unit of claim 1, wherein the interpolation filter unit comprises a plurality of serially connected delayers having four rows, in which one row and three rows receive the same real data, and the second and fourth rows have the same imaginary data. And a plurality of multiplexers for selectively outputting data output from the rear end of each delayer of each row in response to the control bits switched by the switching unit. Interpolator using frequency modulation. 2. The apparatus of claim 1, wherein the multiplier comprises: a multiplexer for selectively outputting a corresponding tap coefficient in response to a control bit switched by the switching unit; And a plurality of multipliers for multiplying and outputting the tap coefficients output from the multiplexer and the data output from the interpolation filter unit. The interpolator using intermediate frequency modulation of an orthogonal frequency multiple modulation transceiver. The method of claim 1, wherein the control bit output by the switching of the switching unit is used as a control bit of the delay row of the interpolation filter unit and a control bit of the multiplexer, and used as a control bit of the multiplexer for selecting the tap coefficient of the multiplier. Interpolator using intermediate frequency modulation of quadrature frequency modulated transceiver.