KR20040043892A - Method for manufacturing liquid crystal display - Google Patents

Abstract

PURPOSE: A method for manufacturing an LCD(Liquid Crystal Display) is provided to reduce a crosstalk between a storage wiring and a data line and increase an aperture ratio, without increasing a surplus metal wiring area for forming a storage electrode. CONSTITUTION: A gate electrode(10), a storage electrode(15) and a pad electrode(20) are formed simultaneously on a glass substrate(5). A first, second and third insulation films(35) are sequentially deposited on an upper portion of the substrate(5) including the gate electrode(10), the storage electrode(15) and the pad electrode(20). An amorphous silicon layer(40) is deposited on an upper portion of the third insulation film(35). After depositing an ohmic layer, an active pattern is formed by a photolithography process. Thereafter the amorphous silicon layer(40) and the third insulation layer(35) are etched and then the second insulation layer(30) is etched. In the storage electrode, a via hole is formed to a storage electrode portion including the storage electrode(15) for increasing the storage capacity. Pixel electrodes(65a)(65b)(65c) are formed by using a transparent conductive film. At this time, the storage electrode(15) is positioned in parallel to a data line at the inside of a black matrix line formed at a color filter substrate.

Description

Method for manufacturing liquid crystal display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a liquid crystal display device capable of simultaneously increasing an aperture ratio while reducing cross talk between a gate wiring and a data line.

In general, a thin film transistor liquid crystal display drives a transistor every predetermined period (gate signal period) to charge a signal received from a data line to a storage capacitor formed between a pixel electrode and a storage electrode until the next gate signal.

In such a thin film transistor liquid crystal display device, there are largely an independent wiring method and a Cst-on-gate method for installing a storage capacitor.

However, in the case of the independent wiring method, there is a problem in that the aperture ratio is reduced because a dedicated wiring for the storage capacitive electrode (the metal is used and remains as a non-transmissive region) must be additionally installed in the array.

In addition, in the case of the Cst-on-gate method, the aperture ratio is improved than the independent wiring method, but there is a problem that the aperture ratio is inevitable because the line width of the gate line must be increased to secure sufficient storage capacity.

Therefore, since the storage capacitance is proportional to the overlapping area of the storage electrode and the pixel electrode and inversely proportional to the distance between the two electrodes, in order to secure sufficient storage capacity, the overlapping area between the storage electrode and the pixel electrode is increased or It has been improved by reducing the distance between the pixel electrodes (that is, reducing the thickness of the insulating film).

However, as described above, when the overlapping area is increased to secure sufficient storage capacity, the area of the storage electrode increases, and the aperture ratio decreases. Also, when the thickness of the insulating film is reduced to secure sufficient storage capacity, the gate wiring and data are reduced. There is a problem that cross talk between lines occurs.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and does not involve an increase in an extra metal wiring area for forming a storage electrode, and reduces aperture ratio while reducing crosstalk between the storage wiring and the data line. It is an object of the present invention to provide a method of manufacturing a liquid crystal display device which can be increased.

1A to 1E are plan views illustrating processes for manufacturing a liquid crystal display device according to the present invention.

2A to 2E are cross-sectional views of processes according to FIGS. 1A to 1E.

(Code description of main parts of drawing)

5 glass substrate 10 gate electrode

15: storage electrode 20: pad electrode

25: first insulating film 30: second insulating film

35: third insulating film 40: amorphous silicon layer

45: source / drain electrodes 55a, 55b, 55c: via hole

60: protective film 65, 65a, 65b, 65c: pixel electrode

70: black matrix line

According to an aspect of the present invention, a gate electrode, a storage electrode, and a pad electrode are simultaneously formed on a transparent insulating substrate; a first insulating layer and a second insulating layer on the substrate including the gate electrode, the storage electrode, and the pad electrode. And sequentially forming a third insulating film; Forming an amorphous layer on the third insulating film; Forming a source and a drain electrode on the amorphous layer above the gate electrode; Forming a passivation layer on the resultant and selectively patterning the passivation layer to form first, second and third via holes exposing the source electrode, the second insulating layer on the storage electrode and the pad electrode; And forming a transparent electrode on the protective film including the first, second and third via holes.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1E are plan views illustrating a process of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention, and a thin film transistor unit and a storage electrode unit, and FIGS. 2A to 2E are thin film transistor units and storage units according to FIGS. 1A to 1E, respectively. It is sectional drawing by process of an electrode part and a pad electrode part.

First, as shown in FIGS. 1A and 2A, the gate electrode 10, the storage electrode 15, and the pad electrode 20 are simultaneously formed on the glass substrate 5. In this case, in the capacitor-on-gate method, the gate wiring 10 and the storage wiring 15 are the same.

Subsequently, as shown in FIGS. 1B and 2B, the first insulating layer 25 and the second insulating layer are formed on the substrate 5 including the gate electrode 10, the storage electrode 15, and the pad electrode 20. 30 and the third insulating film 35 are sequentially deposited.

In this case, the second insulating layer 30 is formed of a material capable of selective etching with the third insulating layer 35 and the subsequent protective layer.

For example, SiNx, SiC, and Al ₂ O ₃ may be used as the first insulating layer 25 and the third insulating layer 35, and SiO ₂ or SiON may be selectively used as the second insulating layer 30. use. In addition, the third insulating layer 35 is deposited to have a thickness of 500 mV to 10,000 mV to reduce crosstalk between the storage electrode 15 and the data line electrode.

Next, an amorphous silicon layer 40 to be used as an active layer is deposited on the third insulating layer 35.

Subsequently, after the ohmic layer (not shown) is deposited, the active pattern 17 is formed by photolithography to etch the amorphous silicon layer 40 and the third insulating layer 35 and then selectively etch the first insulating layer. The second insulating film 30 is etched away.

In this case, the amorphous silicon layer 40 and the third insulating layer 35 are etched using SF ₆ , O ₂ , and He gas, and the second insulating layer 30 is an EPD (End Point) using CHF ₃ gas. Detect) to eliminate some overetching time for the second insulating film thickness.

Next, as shown in FIGS. 1C and 2C, the source / drain electrode 45 and the source / drain metal pattern 45a are formed, and a channel region is formed through back channel etching.

Subsequently, as shown in FIGS. 1D and 2D, the passivation layer 60 is deposited and then subjected to a photolithography method. In this case, the thin film transistor unit including the gate electrode 10 includes a via hole for connecting a pixel and a source electrode. 55a).

In addition, a via hole 55b having only the third insulating layer 35 is removed in the storage electrode part including the storage electrode 15 to increase the storage capacitance.

In addition, a via hole 55c from which the third, second and first insulating layers 25 are removed from the passivation layer 60 is formed in the pad electrode portion including the pad electrodes 20.

In the preferred embodiment, since the SiN is used as the passivation layer 60, the passivation layer 60 and the first insulating layer 25 are simultaneously etched in the pad portion via hole 55c during dry etching, while the via hole 55b of the storage electrode portion is etched at the same time. In the etching method, the protective layer 60, the amorphous silicon layer 40, and the third insulating layer 35 are sequentially etched. However, since the second insulating layer 30 is a SiO ₂ layer having a high etching selectivity, no further etching is performed in the storage electrode part. Do not.

Therefore, only the thicknesses of the first and second insulating layers 25 and 30 contribute to the storage capacitance in the storage electrode unit. As shown in FIG. 1D, the storage electrodes 15 have the first and second thicknesses even though the area of the storage electrode 15 is small. Since the thickness of the insulating films 25 and 30 is thin, sufficient charging capacity can be obtained.

Finally, as shown in FIGS. 1E and 2E, the pixel electrodes 65, 65a, 65b and 65c are formed using a transparent conductive film.

In this case, the storage electrode 15 is disposed in parallel to the data line inside the black matrix line 70 formed on the color filter substrate.

As described above, the present invention increases the aperture ratio by arranging the storage electrode inside the black matrix in a form parallel to the data line, and at the same time, selecting the etching of the third insulating layer between the first insulating layer and the third insulating layer during the deposition of the gate insulating layer. By depositing a large second insulating layer to protect the first insulating layer under the second insulating layer of the storage capacitor during the protective layer etching process, only the first and second insulating layers are left between the pixel electrode and the storage electrode. By reducing the thickness of the insulating film, a sufficient accumulation capacity can be secured. Also, by increasing the thickness of the third insulating film removed from the storage electrode during etching of the protective film, crosstalk between the storage wiring and the data line can be reduced. have.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (7)

Simultaneously forming a gate electrode, a storage electrode, and a pad electrode on the transparent insulating substrate; Sequentially forming a first insulating film, a second insulating film, and a third insulating film on the substrate including the gate electrode, the storage electrode, and the pad electrode; Forming an amorphous layer on the third insulating film; Forming a source and a drain electrode on the amorphous layers on both sides of the gate electrode; A passivation layer is formed on the resultant, and the source electrode, the second insulating layer on the storage electrode, and the pad electrode are exposed by selective etching of the first and third insulating layers and the second insulating layer having a relatively high etching ratio with respect to the protective layer. Forming first, second and third via holes to be made; And And forming a transparent electrode on the passivation layer including the first, second and third via holes. The method of claim 1, wherein the second insulating layer is formed of a material having an etch selectivity different from that of the third insulating layer. The method of claim 1, wherein the storage electrode is formed parallel to the data line and disposed in the black matrix. The method of claim 1, wherein the storage electrode unit forms a storage capacitor with the first insulating film and the second insulating film. The method of claim 1, wherein the third insulating film is formed to a thickness of 500 kV to 10,000 kV. The method of claim 1, wherein the first insulating layer and the third insulating layer are formed of SiNx, SiC, or Al ₂ O ₃ . The method of claim 1, wherein the second insulating layer is formed of SiON or SiO ₂ .