KR20040025804A - Method for forming a gate line using of semiconductor dual damascene structure - Google Patents
Method for forming a gate line using of semiconductor dual damascene structure Download PDFInfo
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- KR20040025804A KR20040025804A KR1020020056405A KR20020056405A KR20040025804A KR 20040025804 A KR20040025804 A KR 20040025804A KR 1020020056405 A KR1020020056405 A KR 1020020056405A KR 20020056405 A KR20020056405 A KR 20020056405A KR 20040025804 A KR20040025804 A KR 20040025804A
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000009977 dual effect Effects 0.000 title claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 3
- 239000000126 substance Substances 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 3
- 230000007423 decrease Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000007261 regionalization Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000010485 coping Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
Description
본 발명은 반도체 소자의 게이트 제조 기술에 관한 것으로, 특히, 노치(notch) 또는 풋(foot) 현상이 없는 수직적(vertical)인 프로파일(profile)과 높은 CD(Critical Dimension)를 갖는 게이트 라인을 형성하는데 적합한 이중 다마신(Dual Damascene) 기법을 이용한 반도체 소자의 게이트 라인 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a technique for manufacturing a gate of a semiconductor device, and more particularly, to forming a gate profile having a vertical profile and a high critical dimension without a notch or foot phenomenon. A method for forming a gate line of a semiconductor device using a suitable dual damascene technique.
반도체 제조 공정 기술의 발달과 함께, 디자인 룰(design rule)의 감소로 인해 디바이스의 고집적화 정도는 점점 더 높아지고 있으며, 이에 비례하여 게이트 크기 역시 점차 축소되고 있는 추세이다.With the development of semiconductor manufacturing process technology, the degree of high integration of devices is increasing due to the reduction of design rules, and the gate size is gradually decreasing in proportion to this.
도 1a 내지 도 1h는 종래의 전형적인 반도체 게이트 라인 제조 과정을 나타낸 단면도이다.1A to 1H are cross-sectional views illustrating a conventional semiconductor gate line fabrication process.
먼저, 도 1a 및 도 1b에 도시한 바와 같이, 실리콘 기판(10)상에 게이트 산화막(11)을 형성한 후, 폴리실리콘(12)을 증착한다.First, as shown in FIGS. 1A and 1B, after forming the gate oxide film 11 on the silicon substrate 10, polysilicon 12 is deposited.
이후, 도 1c에서는, 게이트 라인을 형성하기 위하여 BARC(Bottom of Anti Reflection Coating : 하부 반사방지막)(13)를 코팅하고 포토레지스트를 도포하여 게이트 패턴을 형성한다.Subsequently, in FIG. 1C, a bottom of anti reflection coating (BARC) 13 is coated to form a gate line, and a photoresist is applied to form a gate pattern.
게이트 패턴을 형성한 다음, 도 1d에서는, 상술한 BARC(13)를 먼저 식각한 후 식각 장비, 예를 들어, EPD(End Point Detection) 장비(도시 생략됨)를 이용하여 폴리실리콘(12)을 식각한다. 이때, 게이트 라인의 CD는 BARC(13)의 오버에칭 시간을 조절함으로써 달성될 수 있다.After forming the gate pattern, in FIG. 1D, the above-described BARC 13 is first etched and then the polysilicon 12 is etched using etching equipment, for example, an end point detection (EPD) device (not shown). Etch it. At this time, the CD of the gate line can be achieved by adjusting the overetching time of the BARC 13.
한편, 도 1e 및 도 1f에서는 LDD(Lightly Doped Drain)(14) 형성 공정과 질화막(15) 증착 공정을 각각 수행한다.1E and 1F, a process of forming a lightly doped drain (LDD) 14 and a process of depositing a nitride film 15 is performed, respectively.
그리고, 도 1g 및 도 1h에서는 질화막 패턴없이 블랑켓(Blanket) 식각을 진행하여 질화막 측벽(15)을 형성하고, 소스/드레인 이온주입 공정을 실시하여 소스/드레인 영역(16)을 형성한다.In FIGS. 1G and 1H, a blanket etching is performed without a nitride film pattern to form the nitride film sidewall 15, and a source / drain ion implantation process is performed to form the source / drain region 16.
이상과 같이, 통상의 게이트 라인 제조 공정에서는, 일반적인 패터닝 및 식각 공정에 의해 게이트 프로파일을 형성하는 바, 디자인 룰 감소에 따른 게이트 CD 제어 및 프로파일 구현에 많은 제약이 따른다는 문제가 있었다.As described above, in the conventional gate line manufacturing process, the gate profile is formed by a general patterning and etching process, and thus there is a problem that many restrictions are imposed on the control of the gate CD and the profile implementation due to the reduction of design rules.
또한, 종래의 게이트 라인 제조 공정에서는, 폴리실리콘 증착 후 식각 공정을 진행할 때, 도핑(doping) 효과에 의해 노치 또는 풋 현상이 발생할 수 있다는 문제가 제기되었다.In addition, in the conventional gate line manufacturing process, when the etching process is performed after polysilicon deposition, a problem arises that a notch or a foot phenomenon may occur due to a doping effect.
본 발명은 상술한 문제를 해결하기 위해 안출한 것으로, 질화막 식각 공정을 선 진행한 후 이중 다마신 기법을 이용하여 협폭 게이트(narrow gate)를 형성함으로써, 디자인 룰의 감소에 따른 패턴 형성에서의 한계를 극복하고 안정적으로 게이트 CD를 제어하도록 한 이중 다마신 기법을 이용한 반도체 게이트 라인 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and the narrow gate is formed using the dual damascene technique after the advance of the nitride film etching process, thereby limiting the pattern formation due to the reduction of the design rule. An object of the present invention is to provide a method for forming a semiconductor gate line using a dual damascene technique to overcome the problem and stably control the gate CD.
이러한 목적을 달성하기 위하여 본 발명은, 반도체 게이트 라인 형성 방법에 있어서, 실리콘 기판상에 게이트 산화막을 형성한 후, LDD(Lightly Doped Drain) 패터닝 및 이온주입 공정을 실시하여 LDD 영역을 형성하는 제 1 단계와; 질화막을 증착한 후, 포토레지스트를 도포하여 광폭(wide) 질화막 패턴을 형성하고, 형성된 광폭 질화막 패턴을 마스크로 하여 질화막을 식각하는 제 2 단계와; 포토레지스트를 도포하여 협폭 게이트를 형성하기 위한 협폭 질화막 패턴을 형성하고, 형성된 협폭 질화막 패턴을 마스크로 하여 게이트 산화막이 드러날 때까지 질화막을 식각함으로써 게이트 CD를 제어하는 제 3 단계와; 폴리실리콘을 증착하는 제 4 단계와; 폴리실리콘이 증착된 부분을 상부 질화막 영역까지 CMP(Chemical Mechanical Polishing)를 진행하여 이중 다마신 게이트를 형성하는 제 5 단계와; 형성된 이중 다마신 게이트에 측벽 질화막 패턴을 형성한 후 측벽 질화막 식각 공정을 진행함으로써 측벽을 형성하는 제 6 단계와; 소스/드레인 이온주입 공정을 실시하여 소스/드레인 영역을 형성하는 제 7 단계를 포함하는 것을 특징으로 하는 이중 다마신 기법을 이용한 반도체 게이트 라인 형성 방법을 제공한다.In order to achieve the above object, the present invention provides a first method of forming a LDD region by forming a gate oxide film on a silicon substrate and then performing a lightly doped drain (LDD) patterning and ion implantation process in a semiconductor gate line forming method. Steps; After depositing a nitride film, forming a wide nitride film pattern by applying a photoresist, and etching the nitride film using the wide nitride film pattern as a mask; Forming a narrow nitride film pattern for forming a narrow gate by applying a photoresist, and controlling the gate CD by etching the nitride film until the gate oxide film is exposed using the formed narrow nitride film pattern as a mask; A fourth step of depositing polysilicon; A fifth step of forming a dual damascene gate by performing CMP (Chemical Mechanical Polishing) on the polysilicon deposited portion to the upper nitride film region; Forming a sidewall by forming a sidewall nitride layer pattern on the formed double damascene gate and then performing a sidewall nitride layer etching process; A method of forming a semiconductor gate line using a dual damascene technique is provided, comprising a seventh step of forming a source / drain region by performing a source / drain ion implantation process.
도 1a 내지 도 1h는 종래의 전형적인 반도체 게이트 라인 형성 과정을 나타낸 공정 단면도,1A to 1H are cross-sectional views illustrating a process of forming a typical semiconductor gate line in the related art;
도 2a 내지 도 2j는 본 발명의 바람직한 실시예에 따른 이중 다마신 기법을 이용한 반도체 게이트 라인 형성 과정을 나타낸 공정 단면도.2A to 2J are cross-sectional views illustrating a process of forming a semiconductor gate line using a dual damascene technique according to a preferred embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
20 : 실리콘 기판 21 : 게이트 산화막20 silicon substrate 21 gate oxide film
22 : LDD 23 : 질화막22: LDD 23: nitride film
24, 25 : 포토레지스트 26 : 폴리실리콘24, 25 photoresist 26 polysilicon
27 : 소스/드레인 영역27: source / drain area
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2j는 본 발명의 바람직한 실시예에 따른 이중 다마신 기법을 이용한 반도체 게이트 라인 형성 과정을 나타낸 단면도이다.2A through 2J are cross-sectional views illustrating a process of forming a semiconductor gate line using a dual damascene technique according to an exemplary embodiment of the present invention.
먼저, 도 2a 및 도 2b에 도시한 바와 같이, 실리콘 기판(20)상에 게이트 산화막(21)을 형성한 후, LDD 패터닝 및 이온주입 공정을 실시한다.First, as shown in FIGS. 2A and 2B, after the gate oxide film 21 is formed on the silicon substrate 20, LDD patterning and ion implantation processes are performed.
도 2c에는 이러한 공정 결과에 따른 LDD 영역(22)이 형성된다.In FIG. 2C, the LDD region 22 is formed according to the process result.
이후, 도 2d에서는, 질화막(23), 예를 들어, 약 2500 내지 3000Å 두께의 질화막을 증착한 후, 포토레지스트(24)를 도포하여 광폭(wide) 질화막 패턴을 형성한다.Then, in FIG. 2D, a nitride film 23, for example, a nitride film having a thickness of about 2500 to 3000 Pa is deposited, and then a photoresist 24 is applied to form a wide nitride film pattern.
그리고, 도 2e에서는, 형성된 광폭 질화막 패턴을 마스크로 하여 질화막(23)을 식각한다. 이때, 이러한 1차 광폭 질화막 패터닝 및 식각은, 바람직하게는, 잔류 질화막이 500 내지 1000Å 정도 되도록 진행한다.In FIG. 2E, the nitride film 23 is etched using the formed wide nitride film pattern as a mask. At this time, such primary wide nitride film patterning and etching, Preferably, it progresses so that a residual nitride film may be about 500-1000 GPa.
한편, 도 2f에서는, 이러한 층상에 포토레지스트(25)를 도포하여 본 발명에 따른 협폭 게이트를 형성하기 위한 협폭 질화막 패턴을 형성한다.On the other hand, in Fig. 2F, a photoresist 25 is applied on such a layer to form a narrow nitride film pattern for forming a narrow gate according to the present invention.
그리고, 도 2g에서는, 형성된 협폭 질화막 패턴을 마스크로 하여 게이트 산화막(21)이 드러날 때까지 질화막(23)을 식각함으로써 게이트 CD를 제어한 후, 폴리실리콘(26)을 증착한다. 이때, 폴리실리콘(26)의 두께는 질화막(23)의 두께보다 500에서 1000Å정도 두껍게 증착한다. 이러한 폴리실리콘(26)의 증착은, 예컨대, CVD 기법에 의해 구현될 수 있으며, 이러한 사실은 본 발명의 기술 분야에서 통상의 지식을 가진 자는 용이하게 알 수 있을 것이다.In FIG. 2G, the gate CD is controlled by etching the nitride film 23 until the gate oxide film 21 is exposed using the formed narrow nitride film pattern as a mask, and then polysilicon 26 is deposited. At this time, the thickness of the polysilicon 26 is deposited by 500 to 1000 Å thicker than the thickness of the nitride film 23. Such deposition of polysilicon 26 may be implemented, for example, by CVD techniques, which will be readily apparent to one of ordinary skill in the art.
도 2h에서는, 이렇게 폴리실리콘(26)이 증착된 부분을 상부 질화막 영역까지 CMP를 진행하여 이중 다마신 게이트를 형성한다. 이러한 CMP 공정에 의해 폴리실리콘(26) 층이 약 2000 내지 2500Å이 되도록 한다.In FIG. 2H, the polysilicon 26 is deposited by CMP to the upper nitride film region to form a double damascene gate. This CMP process results in a polysilicon 26 layer of about 2000 to 2500 microns.
다음으로, 도 2i에서는, 형성된 이중 다마신 게이트에 측벽 질화막 패턴을 형성한 후 측벽 질화막 식각 공정을 진행함으로써 측벽을 형성한다.Next, in FIG. 2I, after forming the sidewall nitride film pattern on the formed double damascene gate, the sidewall nitride film is etched to form sidewalls.
그리고, 도 2j에서는 소스/드레인 이온주입 공정을 실시하여 소스/드레인 영역(27)을 형성한다.In FIG. 2J, the source / drain ion implantation process is performed to form the source / drain region 27.
이상과 같이, 본 발명은, 게이트 형성 방법을 폴리실리콘 식각 방법이 아닌 질화막 식각 공정을 먼저 진행한 후 이중 다마신 방식으로 협폭 게이트를 형성함으로써 점점 축소되는 게이트 사이즈(size)에 보다 효율적으로 대처하도록 한 것이다.As described above, the present invention provides a method for more efficiently coping with gate size, which is gradually reduced by forming a narrow gate in a double damascene method after first performing a nitride film etching process instead of a polysilicon etching method. It is.
따라서, 본 발명은 반도체 디자인 룰 감소에 따른 패턴 형성에서의 한계 상황을 해결함과 동시에 안정적으로 CD를 제어함으로써 기존 공정에서 대두되던 식각 공정의 재현성 문제를 배제할 수 있으며, 이로 인해 안정된 DC 전류를 유지하여 궁극적으로 반도체 수율을 높일 수 있는 효과가 있다.Accordingly, the present invention solves the limitations of pattern formation due to the reduction of semiconductor design rules and at the same time, can stably control the CD, thereby eliminating the problem of reproducibility of the etching process that has emerged in the existing process, thereby reducing the stable DC current. It is effective in maintaining and ultimately increasing semiconductor yield.
이상, 본 발명을 실시예에 근거하여 구체적으로 설명하였지만, 본 발명은 이러한 실시예에 한정되는 것이 아니라, 후술하는 특허청구범위내에서 여러 가지 변형이 가능한 것은 물론이다.As mentioned above, although this invention was demonstrated concretely based on the Example, this invention is not limited to such an Example, Of course, various deformation | transformation are possible for it within the following Claim.
Claims (3)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5688704A (en) * | 1995-11-30 | 1997-11-18 | Lucent Technologies Inc. | Integrated circuit fabrication |
| US5960270A (en) * | 1997-08-11 | 1999-09-28 | Motorola, Inc. | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions |
| US6077733A (en) * | 1999-09-03 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing self-aligned T-shaped gate through dual damascene |
| US6159781A (en) * | 1998-10-01 | 2000-12-12 | Chartered Semiconductor Manufacturing, Ltd. | Way to fabricate the self-aligned T-shape gate to reduce gate resistivity |
| KR20030064958A (en) * | 2002-01-29 | 2003-08-06 | 삼성전자주식회사 | Method of forming mos transistor having notched gate |
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2002
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5688704A (en) * | 1995-11-30 | 1997-11-18 | Lucent Technologies Inc. | Integrated circuit fabrication |
| US5960270A (en) * | 1997-08-11 | 1999-09-28 | Motorola, Inc. | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions |
| US6159781A (en) * | 1998-10-01 | 2000-12-12 | Chartered Semiconductor Manufacturing, Ltd. | Way to fabricate the self-aligned T-shape gate to reduce gate resistivity |
| US6077733A (en) * | 1999-09-03 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing self-aligned T-shaped gate through dual damascene |
| KR20030064958A (en) * | 2002-01-29 | 2003-08-06 | 삼성전자주식회사 | Method of forming mos transistor having notched gate |
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