KR20040003970A - Method for fabricating capacitor in semiconductor device - Google Patents
Method for fabricating capacitor in semiconductor device Download PDFInfo
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- KR20040003970A KR20040003970A KR1020020039003A KR20020039003A KR20040003970A KR 20040003970 A KR20040003970 A KR 20040003970A KR 1020020039003 A KR1020020039003 A KR 1020020039003A KR 20020039003 A KR20020039003 A KR 20020039003A KR 20040003970 A KR20040003970 A KR 20040003970A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims description 21
- 239000010408 film Substances 0.000 claims abstract description 56
- 239000010409 thin film Substances 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 5
- 230000002776 aggregation Effects 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 3
- 238000005054 agglomeration Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000008187 granular material Substances 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 claims 1
- 239000000463 material Substances 0.000 description 9
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910019899 RuO Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
- H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/694—Electrodes comprising noble metals or noble metal oxides
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- Semiconductor Memories (AREA)
Abstract
본 발명에 의해 금속전극을 사용하는 고집적반도체 장치의 캐패시턴스를 향상 시킬수 있는 반도체 장치의 캐패시터 제조방법을 제공하기 위한 것으로, 이를 위한 본 발명은 기판상에 금속막으로 제1 하부전극을 형성하는 단계; 상기 제1 하부전극의 표면에 알루미늄막을 형성하는단계; 상기 알루미늄막상에 절연성 막을 형성하는 단계: 상기 절연성 막과 상기 알루미늄이 알갱이형태로 응집되어 상기 제1 하부전극상에 요철이 생기도록 하는 단계; 요철이 생긴 상기 제1 하부전극 상에 제2 하부전극을 형성하는 단계; 상기 제2 하부전극상에 유전체 박막을 형성하는 단계; 및 상기 유전체 박막상에 상부전극을 형성하는 단계를 포함하는 반도체 장치의 캐패시터 제조방법을 제공한다.The present invention provides a method of manufacturing a capacitor of a semiconductor device capable of improving the capacitance of a highly integrated semiconductor device using a metal electrode, and the present invention for forming a first lower electrode on the substrate with a metal film; Forming an aluminum film on a surface of the first lower electrode; Forming an insulating film on the aluminum film, wherein the insulating film and the aluminum are aggregated in a granular form to cause irregularities on the first lower electrode; Forming a second lower electrode on the uneven first lower electrode; Forming a dielectric thin film on the second lower electrode; And it provides a method of manufacturing a capacitor of a semiconductor device comprising the step of forming an upper electrode on the dielectric thin film.
Description
본 발명은 반도체 제조기술에 관한 것으로, 특히 반도체 소자의 캐패시터제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.
반도체 소자, 특히 DRAM(Dynamic Random Access Memory)의 반도체 메모리의 집적도가 증가함에 따라 정보 기억을 위한 기본 단위인 메모리 셀의 면적이 급격하게 축소되고 있다.As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.
이러한 메모리 셀 면적의 축소는 셀 캐패시터의 면적 감소를 수반하여, 센싱 마진과 센싱 속도를 떨어뜨리고, α-입자에 의한 소프트 에러(Soft Error)에 대한 내구성이 저하되는 문제점을 유발하게 된다. 따라서, 제한된 셀 면적에서 충분한 정전용량을 확보할 수 있는 방안이 필요하게 되었다.Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.
캐패시터의 정전용량(C)은 하기의 수학식 1과 같이 정의된다.The capacitance C of the capacitor is defined as in Equation 1 below.
여기서, ε은 유전률, As는 전극의 유효 표면적, d는 전극간 거리를 각각 나타낸 것이다.Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.
따라서, 캐패시터의 정전용량을 늘리기 위해서는 전극의 표면적을 넓히거나, 유전체 박막의 두께를 줄이거나, 유전률을 높여야 한다.Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.
이 중에서 전극의 표면적을 넓히는 방안이 제일 먼저 고려되어 왔다. 콘케이브(concave) 구조, 실린더(sylinder) 구조, 다층 핀(fin) 구조 등과 같은 3차원 구조의 캐패시터는 모두 제한된 레이아웃 면적에서 전극의 유효 표면적을 증대시키기 위하여 제안된 것이다. 그러나, 이러한 방법은 반도체 소자가 초고집적화 되면서 전극의 유효 표면적을 증대시키는데 한계를 보이고 있다.Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, multilayer fin structures, and the like, are all proposed to increase the effective surface area of electrodes in a limited layout area. However, this method has a limitation in increasing the effective surface area of the electrode as the semiconductor device is very high integration.
그리고, 전극간 거리(d)를 최소화하기 위해 유전체 박막의 두께를 감소시키는 방안은 유전체 박막의 두께가 감소함에 따라 누설전류가 증가하는 문제 때문에 역시 그 한계에 직면하고 있다.In addition, the method of reducing the thickness of the dielectric thin film in order to minimize the distance between electrodes (d) also faces the limitation due to the problem that the leakage current increases as the thickness of the dielectric thin film is reduced.
따라서, 근래에 들어서는 주로 유전체 박막의 유전율의 증대를 통한 캐패시터의 정전용량 확보에 초점을 맞추어 연구, 개발이 진행되고 있다. 전통적으로, 실리콘산화막이나 실리콘질화막을 유전체 박막 재료로 사용한 소위 NO(Nitride-Oxide) 구조의 캐패시터가 주류를 이루었으나, 최근에는 Ta2O5, (Ba,Sr)TiO3(이하 BST라 함) 등의 고유전체 물질이나, (Pb,Zr)TiO3(이하 PZT라 함), (Pb,La)(Zr,Ti)O3(이하 PLZT라 함), SrBi2Ta2O9(이하 SBT라 함), SrBi2(Ta1-x,Nbx)2O9(이하 SBTN이라 함), Bi4-xLaxTi3O12(이하 BLT라 함), Bi4Ti3O12(이하, BIT라 함)등의 강유전체 물질을 유전체 박막 재료로 적용하고 있다.Therefore, in recent years, research and development have been focused on securing capacitance of a capacitor mainly by increasing the dielectric constant of a dielectric thin film. Traditionally, so-called NO (Nitride-Oxide) capacitors using silicon oxide or silicon nitride as the dielectric thin film have become mainstream, but recently, Ta 2 O 5 , (Ba, Sr) TiO 3 (hereinafter referred to as BST) High dielectric materials such as (Pb, Zr) TiO 3 (hereinafter referred to as PZT), (Pb, La) (Zr, Ti) O 3 (hereinafter referred to as PLZT), SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT) SrBi 2 (Ta 1-x , Nbx) 2 O 9 (hereinafter referred to as SBTN), Bi 4-x La x Ti 3 O 12 (hereinafter referred to as BLT), Bi 4 Ti 3 O 12 (hereinafter referred to as BIT Ferroelectric materials are applied as dielectric thin film materials.
이러한 고유전체 물질 또는 강유전체 물질을 유전체 박막 재료로 사용하는 고유전체 캐패시터 또는 강유전체 캐패시터를 제조함에 있어서, 고유전체 물질 또는 강유전체 물질 특유의 유전 특성을 구현하기 위해서는 유전체 주변 물질 및 공정(예컨대 고온열공정)의 적절한 제어가 수반되어야 한다. 일반적으로, 고유전체 캐패시터나 강유전체 캐패시터의 상, 하부전극 물질로서 노블메탈(noble metal) 또는 이들의 화합물, 예컨대 Pt, Ir, Ru, RuO2, IrO2등을 사용하고 있다.In the manufacture of high dielectric capacitors or ferroelectric capacitors using such high dielectric materials or ferroelectric materials as dielectric thin film materials, dielectric materials and processes (for example, high temperature and thermal processes) in order to realize dielectric properties unique to high dielectric materials or ferroelectric materials Proper control of the In general, a noble metal or a compound thereof, such as Pt, Ir, Ru, RuO 2 , IrO 2, or the like is used as the upper and lower electrode materials of the high dielectric capacitor and the ferroelectric capacitor.
도1a 내지 도1c는 종래기술에 의한 캐패시터 제조방법을 나타내는 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a capacitor according to the prior art.
먼저 도1a에 도시된 바와 같이, 활성영역(11)이 형성된 반도체기판(10)상에 층간절연막(12)을 형성한 후, 층간절연막(12)을 관통하여 반도체기판(10)의 활성영역(11)과 연결되는 콘택홀을 형성한다. 콘택홀을 도전성 물질로 매립하여 콘택플러그(13)를 형성한다. 이어서 캐패시터가 형성될 크기만큼 캐패시터절연막(14)을 형성한다. 이어서 콘택플러그(13)가 노출되도록 캐패시터절연막(14)을 선태적으로 식각하여 캐패시터홀(15)을 형성하고, 캐패시터홀(15) 내부에 폴리실리콘막으로 하부전극(16)을 형성한다.First, as shown in FIG. 1A, the interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the active region 11 is formed, and then penetrates the interlayer insulating film 12 to form an active region ( A contact hole connected to 11) is formed. A contact plug 13 is formed by filling the contact hole with a conductive material. Subsequently, the capacitor insulating film 14 is formed as large as the capacitor is formed. Subsequently, the capacitor insulating film 14 is selectively etched to expose the contact plug 13 to form the capacitor hole 15, and the lower electrode 16 is formed of a polysilicon film in the capacitor hole 15.
이어서 도1b에 도시된 바와 같이, 캐패시터절연막(14)를 제거하고, 하부전극(16) 상에 전극의 유효면적을 증가시키기 위한반구형실리콘그레인(hemispherical shaped grains;HSG)(17)을 형성한다.Subsequently, as shown in FIG. 1B, the capacitor insulating film 14 is removed, and hemispherical silicon grains (HSG) 17 are formed on the lower electrode 16 to increase the effective area of the electrode.
HSG 공정은 전하저장의 표면에 실리콘 알갱이를 이용하여 요철을 주어 유효 면적을 증가시키기 위한 것으로, 이렇게 함으로서 캐패시턴스를 확보하려는 시도인데, 준안정성 폴리실리콘(Metastable PolySilicon; MPS) 그레인(Grain) 공정이라고도 한다. HSG공정으로 인해 전극의 표면에 요철을 만들어 표면적을 증가시킬 경우, 평탄화된 전극 구조에 비해 약 2배 가량 캐패시턴스를 증가시킬 수 있다.The HSG process is to increase the effective area by using irregularities of silicon grains on the surface of the charge storage. This is an attempt to secure capacitance, also called metastable polysilicon (MPS) grain process. . When the surface area of the electrode is increased by making the uneven surface due to the HSG process, the capacitance can be increased by about 2 times compared to the planarized electrode structure.
이어서 도1c에 도시된 바와 같이, 하부전극(16) 상에 유전체박막(18)을 형성하고 그 상부에 상부전극(19)을 형성한다.Subsequently, as shown in FIG. 1C, the dielectric thin film 18 is formed on the lower electrode 16 and the upper electrode 19 is formed thereon.
제한된 면적에서 일정한 캐패시턴스를 확보하기 위해 상술한 바와 같이 하부전극상에 반구형실리콘그레인을 형성시키는 방법을 사용하였으나, 0.12㎛이하 소자에서는 실리콘계의 물질들로만 사용해서는 물리적 한계에 직면할 것으로 예상되어,전극으로 금속을 사용하고 유전체박막으로 Ta2O5막, BST막등의 새로운 물질을 사용하고 있다.In order to secure a constant capacitance in a limited area, a method of forming hemispherical silicon grains on the lower electrode was used as described above. However, in the device of 0.12 μm or less, it is expected to face physical limitations by using only silicon-based materials. Metal is used and new materials such as Ta 2 O 5 film and BST film are used as dielectric thin film.
그러나 향후 0.1㎛ 이하의 미세소자에서는 단순히 유전체박막을 새로운 물질사용하여도 제한된 면적에서 원하는 양의 일정한 캐패시턴스를 확보하기가 어려운 실정이다. 따라서 Ta2O5막, BST막과 같이 고유전율을 가지는 유전체 박막을 사용하여도 전극의 표면적을 증가시키는 할 필요성이 생긴다.However, in the future, it is difficult to secure a constant capacitance of a desired amount in a limited area even by using a new material for a thin film of 0.1 μm or less. Therefore, there is a need to increase the surface area of the electrode even when using a dielectric thin film having a high dielectric constant such as a Ta 2 O 5 film or a BST film.
본 발명에 의해 금속전극을 사용하는 고집적반도체 장치의 캐패시턴스를 향상 시킬수 있는 반도체 장치의 캐패시터 제조방법을 제공함을 목적으로 한다.It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device capable of improving the capacitance of a highly integrated semiconductor device using a metal electrode.
도1a 내지 도1c는 종래기술에 의한 캐패시터 제조방법을 나타내는 공정단면도.1A to 1C are process cross-sectional views showing a capacitor manufacturing method according to the prior art.
도2a 내지 도2f는 본 발명의 바람직한 실시예에 따른 반도체 캐패시터 제조방법을 나타내는 공정단면도.2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor capacitor according to a preferred embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
20 : 기판20: substrate
21 : 활성영역21: active area
22 : 층간절연막22: interlayer insulating film
23 : 콘택플러그23: Contact Plug
24 : 확산방지막24: diffusion barrier
25 : 제1 하부전극25: first lower electrode
26 : Al2O3막26: Al 2 O 3 membrane
27 : Al/Al2O3막27: Al / Al 2 O 3 film
28 : 제2 하부전극28: second lower electrode
29 : 유전체박막29: dielectric thin film
30 : 상부전극30: upper electrode
상기의 목적을 달성하기 위한 본 발명은 기판상에 금속막으로 제1 하부전극을 형성하는 단계; 상기 제1 하부전극의 표면에 알루미늄막을 형성하는단계; 상기 알루미늄막상에 절연성 막을 형성하는 단계: 상기 절연성 막과 상기 알루미늄이 알갱이형태로 응집되어 상기 제1 하부전극상에 요철이 생기도록 하는 단계; 요철이 생긴 상기 제1 하부전극 상에 제2 하부전극을 형성하는 단계; 상기 제2 하부전극상에 유전체 박막을 형성하는 단계; 및 상기 유전체 박막상에 상부전극을 형성하는 단계를 포함하는 반도체 장치의 캐패시터 제조방법을 제공한다.The present invention for achieving the above object comprises the steps of forming a first lower electrode with a metal film on a substrate; Forming an aluminum film on a surface of the first lower electrode; Forming an insulating film on the aluminum film, wherein the insulating film and the aluminum are aggregated in a granular form to cause irregularities on the first lower electrode; Forming a second lower electrode on the uneven first lower electrode; Forming a dielectric thin film on the second lower electrode; And it provides a method of manufacturing a capacitor of a semiconductor device comprising the step of forming an upper electrode on the dielectric thin film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2f는 본 발명에 의한 바람직한 실시예에 따른 반도체장치의 캐패시터 제조방법을 나타내는 도면이다.2A to 2F are views showing a capacitor manufacturing method of a semiconductor device according to a preferred embodiment of the present invention.
먼저 도2a에 도시된 바와 같이, 활성영역(21)이 형성된 반도체기판(20)상에 층간절연막(22)을 형성한 후, 층간절연막(22)을 관통하여 반도체기판(20)의 활성영역(21)과 연결되는 콘택홀을 형성한다. 이어서 콘택홀을 도전성 물질로 매립하여콘택플러그(23)를 형성한다. 여기서 도시되지는 않았으나, 콘택홀 내부에 Ti막을 증착하고 열공정을 실시하여 활성영역(21)과의 계면에 오믹 콘택을 위한 티타늄실리사이드를 형성한다.First, as shown in FIG. 2A, the interlayer insulating film 22 is formed on the semiconductor substrate 20 on which the active region 21 is formed, and then penetrates the interlayer insulating film 22 to form the active region of the semiconductor substrate 20 ( A contact hole connected to 21 is formed. Subsequently, the contact hole is filled with a conductive material to form the contact plug 23. Although not shown here, a Ti film is deposited inside the contact hole and a thermal process is performed to form titanium silicide for ohmic contact at the interface with the active region 21.
이어서 후속공정에서 하부전극과 콘택프러그 간의 상호 물질확산을 방지하기 위한 확산방지막(24)을 TiN막 또는 TiN/Ti막으로 형성하고, 루테늄 또는 텅스텐등의 전도성 물질을 이용하여 제1 하부전극용 전도막(25')을 확산방지막(24)상에 증착한다.Subsequently, in a subsequent process, a diffusion barrier 24 is formed of a TiN film or a TiN / Ti film to prevent mutual diffusion between the lower electrode and the contact plug, and the first lower electrode is conductive by using a conductive material such as ruthenium or tungsten. A film 25 ′ is deposited on the diffusion barrier film 24.
이어서 도2b에 도시된 바와 같이, 확산방지막(24) 및 제1 하부전극용 전도막(25')을 패터닝하여 제1 하부전극(25)을 형성한다.Subsequently, as shown in FIG. 2B, the diffusion barrier layer 24 and the conductive layer 25 ′ for the first lower electrode are patterned to form the first lower electrode 25.
이어서 도2c에 도시된 바와 같이, 제1 하부전극(25) 표면에 Al막(26)을 얇게 증착한다.Subsequently, as shown in FIG. 2C, an Al film 26 is thinly deposited on the surface of the first lower electrode 25.
이어서 도2d에 도시된 바와 같이, 반응기 안에 산소 또는 수초에서 수분이내로 조절하여 주입하여 Al막(26)위에 얇게(예컨대 20Å ~ 300Å) 알루미늄산화막이 형성되도록 하여 제1 하부전극 표면에 요철을 가지는 Al/Al2O3막(27)이 형성되도록한다. 이 때 알루미늄 산화막의 두께가 300Å이하로 얇을 경우 자체의 표면/계면에너지를 줄이기 위하여 서로 응집하는 현상이 일어난다. 즉 이러한 응집은 제1 하부전극의 표면에 요철을 주게되어 표면적을 넓히게 되며, 이러한 요철상에 전극물질로 제2 하부전극을 형성하게 되면 표면적은 넓어지면서도 하부전극과 캐패시터 절연막과의 특성도 만족하는 캐패시터를 형성할 수 있다.Then, as shown in FIG. 2D, the aluminum oxide film is formed on the Al film 26 (for example, 20 kPa to 300 kPa) to form a thin (eg, 20 kPa to 300 kPa) aluminum oxide film formed on the Al film 26 by controlling the oxygen or water within a few seconds. / Al 2 O 3 film 27 to be formed. At this time, when the thickness of the aluminum oxide film is less than 300Å, the phenomenon of aggregation occurs to reduce the surface / interface energy of itself. In other words, the agglomeration causes unevenness on the surface of the first lower electrode, thereby increasing the surface area. When the second lower electrode is formed of the electrode material on the unevenness, the surface area becomes wider and the characteristics of the lower electrode and the capacitor insulating film are also satisfied. The capacitor can be formed.
또한 여기서 질소를 사용하여 알루미늄 질화물을 응집시켜 상기의 효과를 얻을 수 있다.In addition, the above effects can be obtained by agglomeration of aluminum nitride using nitrogen here.
또한, 반응기안의 산소를 주입할 때 산소의 유량 및 주입시간을 조절하여 Al막위에 형성되는 산화막 두께를 조절하여 최종적으로 응집되는 알루미늄 산화막의 반지름을 조절하거나, 알루미늄 산화물을 형성시킨 후 열처리를 통해 응집의 크기 및 분포를 조절할 수 있다.In addition, when the oxygen is injected into the reactor, the flow rate and injection time of the oxygen are adjusted to control the thickness of the oxide film formed on the Al film, thereby controlling the radius of the aluminum oxide film to be finally aggregated, or forming an aluminum oxide, followed by heat treatment. The size and distribution of can be adjusted.
이어서, 도2d에 도시된 바와 같이, 루테늄막 또는 백금막을 이용하여 요철을 가지는 Al/Al2O3막(27)상에 제2 하부전극(28)을 형성한다. 결국 하부전극은 제1 하부전극(25)/Al/Al2O3막(27)/제2 하부전극(28)의 형태로 구성되는 것이다.Next, as shown in FIG. 2D, a second lower electrode 28 is formed on the Al / Al 2 O 3 film 27 having irregularities using a ruthenium film or a platinum film. As a result, the lower electrode is configured in the form of the first lower electrode 25 / Al / Al 2 O 3 film 27 / second lower electrode 28.
이어서 도2f에 도시된 바와 같이, 제2 하부전극(28) 상에 유전체 박막(29) 및 상부전극(30)을 형성한다. 여기서 유전체 박막은 Ta2O5 또는 BST와 같은 고유전체 물질이나, PZT, PLZT, SBT, SBTN, BLT, BIT등의 강유전체 물질을 사용할 수 있다.Subsequently, as illustrated in FIG. 2F, the dielectric thin film 29 and the upper electrode 30 are formed on the second lower electrode 28. The dielectric thin film may be a high dielectric material such as Ta2O5 or BST, or a ferroelectric material such as PZT, PLZT, SBT, SBTN, BLT, or BIT.
본 발명에 의해 향후 차세대 반도체 장치에서 고유전율을 가지는 신물질의 도입과 더불어 표면적 증가를 통해 보다 고집적 반도체 장치의 캐패시터를 효율적으로 만들수 있다.According to the present invention, a capacitor of a higher density semiconductor device can be efficiently made through the introduction of a new material having a high dielectric constant and increasing the surface area in the next generation semiconductor device.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 의해 금속막을 이용하는 캐패시터에서 같은 면적에서 보다 표면적이 증가된 고집적 캐패시터를 제공할 수 있다.According to the present invention, it is possible to provide a highly integrated capacitor having an increased surface area at the same area in a capacitor using a metal film.
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