KR20040002237A - A method for forming a submicron contact of a semiconductor device - Google Patents
A method for forming a submicron contact of a semiconductor device Download PDFInfo
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- KR20040002237A KR20040002237A KR1020020037684A KR20020037684A KR20040002237A KR 20040002237 A KR20040002237 A KR 20040002237A KR 1020020037684 A KR1020020037684 A KR 1020020037684A KR 20020037684 A KR20020037684 A KR 20020037684A KR 20040002237 A KR20040002237 A KR 20040002237A
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- forming
- contact
- semiconductor device
- illumination system
- photoresist pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
Abstract
Description
본 발명은 반도체소자의 미세 콘택 형성방법에 관한 것으로, 특히 바이너리 마스크 ( binary mask ) 와 변형 조명계를 이용하여 반도체소자의 고집적화에 충분한 미세 콘택을 용이하게 실시할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact of a semiconductor device, and more particularly, to a technique for easily performing a fine contact sufficient for high integration of a semiconductor device using a binary mask and a modified illumination system.
일반적으로, 반도체소자의 콘택홀을 형성할 때 위상반전마스크 ( phase shift mask ) 나 감광막의 리플로우 ( reflow ) 의 방법을 사용하였다.In general, a method of forming a contact hole of a semiconductor device has used a method of reversing a phase shift mask or a photoresist film.
그러나, 반도체소자의 고집적화에 따른 미세 콘택홀 형성 공정시 상기 위상반전마스크를 이용하여 실시하는 경우는, 패터닝 공정시 사이드롭 ( side-lobe ) 현상이나 해상도 ( resolution ) 저하 등의 현상이 유발될 수 있다.However, in the case of using the phase shift mask in the process of forming a fine contact hole due to the high integration of semiconductor devices, side-lobe phenomenon or a decrease in resolution may occur during the patterning process. have.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 미세 콘택 형성방법을 도시한 평면도이다.1A to 1C are plan views illustrating a method for forming a micro contact of a semiconductor device according to the prior art.
상기 도 1a 는 종래기술에 따라 콘택홀을 형성하기 위한 콘택홀 형성용 위상반전마스크의 평면도로서, 석영기판(11) 상부에 콘택홀 영역(15)을 투광시키는 차광패턴(13)이 형성된 것이다.1A is a plan view of a phase shift mask for forming a contact hole for forming a contact hole according to the prior art, in which a light shielding pattern 13 for transmitting a contact hole region 15 is formed on a quartz substrate 11.
상기 도 1b 는 반도체기판(21) 상부에 피식각층(도시안됨)을 형성하고 그 상부에 감광막패턴(23)을 형성한 것이다.In FIG. 1B, an etched layer (not shown) is formed on the semiconductor substrate 21, and a photoresist pattern 23 is formed on the semiconductor substrate 21.
상기 도 1c 는 상기 감광막패턴(23)을 리플로우시켜 콘택홀로 예정된 부분의 CD를 적게 형성한 것이다.In FIG. 1C, the CD of the portion predetermined as the contact hole is formed by reflowing the photoresist pattern 23.
상기한 바와 같이 종래기술에 따른 반도체소자의 미세 콘택 형성방법은, 위상반전마스크를 이용하여 실시함으로써 그로 인한 사이드롭 현상이 유발되거나 해상도가 저하되는 문제점이 있다.As described above, the method for forming a micro contact of a semiconductor device according to the related art has a problem in that a sidedrop phenomenon is caused or a resolution is lowered by using a phase inversion mask.
본 발명은 상기한 종래기술에 따른 문제점을 해결하기 위하여, 수정된 바이너리 마스크와 변형 조명계를 이용하여 미세 콘택홀을 형성함으로써 반도체소자의특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 미세 콘택 형성방법을 제공하는데 그 목적이 있다.The present invention provides a method for forming a fine contact of a semiconductor device that can improve the characteristics and reliability of the semiconductor device by forming a fine contact hole using a modified binary mask and a modified illumination system in order to solve the problems according to the prior art. The purpose is to provide.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 미세 콘택 형성방법을 도시한 평면도.1A to 1C are plan views illustrating a method for forming a micro contact of a semiconductor device according to the prior art.
도 2a 내지 도 2c 는 본 발명의 실시예에 따른 반도체소자의 미세 콘택 형성방법을 도시한 평면도.2A to 2C are plan views illustrating a method of forming fine contacts in a semiconductor device according to an embodiment of the present invention.
도 3 은 본 발명의 실시예에 사용된 변형 조명계를 도시한 평면도.3 is a plan view showing a modified illumination system used in the embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31 : 석영기판13,33 : 차광패턴11,31: quartz substrate 13,33: shading pattern
15,35 : 투광영역, 콘택홀 영역21,41 : 반도체기판15,35: light emitting area, contact hole area 21,41: semiconductor substrate
23,43 : 감광막패턴23,43: photoresist pattern
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 미세콘택 형성방법은,In order to achieve the above object, the method for forming a micro contact of a semiconductor device according to the present invention,
예정된 크기와 다르게 디자인된 콘택용 바이너리 마스크를 이용한 노광 및 현상공정으로 반도체기판 상에 예정된 크기의 콘택용 감광막패턴을 형성하되, 상기 노광 공정시 변형 조명계를 이용하여 실시하는 공정과,Forming a contact photoresist pattern of a predetermined size on a semiconductor substrate by an exposure and development process using a contact binary mask designed differently from a predetermined size, using a modified illumination system during the exposure process;
상기 감광막패턴을 리플로우시켜 미세 콘택용 감광막패턴을 형성하는 공정을 포함하는 것과,Reflowing the photoresist pattern to form a photoresist pattern for a fine contact;
상기 변형 조명계는 크로스폴 ( cross pole ), 쿼드로폴 ( quadrupole ), 애뉼러 ( annular ) 또는 컨벤셔널 ( conventional ) 타입 중에서 임의로 선택된 한가지 타입이 사용되는 것과,The modified illumination system may be one of a cross pole, quadrupole, annular or conventional type selected arbitrarily from one of the following types;
상기 바이너리 마스크의 콘택영역이 예정된 크기보다 긴 직사각형으로 디자인된 것과,The contact area of the binary mask is designed as a rectangle longer than a predetermined size,
상기 변형 조명계는 다이폴 ( dipole ) 타입이 사용되는 것을 특징으로 한다.The modified illumination system is characterized in that a dipole type is used.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c 는 본 발명의 실시예에 따른 반도체소자의 미세 콘택 형성방법을 도시한 평면도로서,2A to 2C are plan views illustrating a method for forming a micro contact of a semiconductor device according to an embodiment of the present invention.
상기 도 2a 는 수정된 바이너리 마스크로서, 콘택홀 영역(35)을 길게 디자인하여 형성한 것이다.2A illustrates a modified binary mask formed by designing a long contact hole region 35.
여기서, "31" 은 석영기판, "33" 은 차광패턴 그리고 "35" 는 콘택홀 영역(35)으로서 상기 차광패턴(33)에 의하여 투광되는 영역이다.Here, "31" is a quartz substrate, "33" is a light shielding pattern, and "35" is a contact hole region 35 which is a region to be transmitted by the light shielding pattern 33.
상기 도 2b 는 반도체기판(41) 상부에 피식각층(도시안됨)을 형성하고 그 상부에 감광막을 도포한 다음, 상기 도 2a 의 바이너리 마스크를 이용한 노광 및 현상 공정으로 콘택홀 형성용 감광막패턴(43)을 형성한 것이다.FIG. 2B illustrates an etching layer (not shown) on the semiconductor substrate 41 and a photoresist film on the upper portion of the semiconductor substrate 41, and then a photoresist pattern 43 for forming a contact hole by an exposure and development process using the binary mask of FIG. 2A. ) Is formed.
이때, 상기 노광 공정은 변형 조명계를 이용하여 형성한 것이다.At this time, the exposure step is formed using a modified illumination system.
여기서, 상기 변형 조명계는 크로스폴 ( cross pole ), 쿼드로폴 ( quadrupole ), 애뉼러 ( annular ), 다이폴 ( dipole ) 또는 컨벤셔널 ( conventional ) 타입 중에서 임의로 선택된 한가지 타입을 사용한 것이다.Here, the modified illumination system uses one type arbitrarily selected from a crosspole, quadrupole, annular, dipole, or conventional type.
상기 도 2c 는 상기 감광막패턴(43)을 리플로우시켜 상기 콘택홀 형성용 감광막패턴(43)의 CD 크기를 작게 형성한 것이다.In FIG. 2C, the CD size of the contact hole forming photoresist pattern 43 is reduced by reflowing the photoresist pattern 43.
도 3 은 본 발명의 실시예에 사용된 다이폴 타입의 변형 조명계를 도시한 것이다.3 shows a dipole type modified illumination system used in an embodiment of the invention.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 미세 콘택 형성방법은, 수정된 바이너리 마스크와 변형 조명계를 이용하여 콘택용 감광막패턴을 형성하고 이를 리플로우시켜 미세 콘택홀용 감광막패턴을 형성한 다음, 후속공정으로 미세 콘택홀을 형성하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과를제공한다.As described above, the method for forming a fine contact of a semiconductor device according to the present invention comprises forming a contact photoresist pattern using a modified binary mask and a modified illumination system and reflowing it to form a photoresist pattern for a fine contact hole. Forming a fine contact hole in the process provides an effect that can improve the characteristics and reliability of the semiconductor device.
Claims (4)
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KR1020020037684A KR20040002237A (en) | 2002-06-29 | 2002-06-29 | A method for forming a submicron contact of a semiconductor device |
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KR1020020037684A KR20040002237A (en) | 2002-06-29 | 2002-06-29 | A method for forming a submicron contact of a semiconductor device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100819673B1 (en) * | 2006-12-22 | 2008-04-04 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming pattern of the same |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100819673B1 (en) * | 2006-12-22 | 2008-04-04 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming pattern of the same |
US7776750B2 (en) | 2006-12-22 | 2010-08-17 | Hynix Semiconductor Inc. | Semiconductor device and method for forming a pattern in the same with double exposure technology |
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