KR20030089120A - Clock signal generating circuit and method of system on a chip - Google Patents

Abstract

PURPOSE: A circuit and a method for generating a clock signal of a SOC(System On a Chip) are provided to prevent the increase of the number of pins in the SOC by including two more than phase-locked loops to generate clock signals in various frequencies. CONSTITUTION: A crystal oscillator(OSC) generates a clock signal(XIN). A NAND gate(NA2) inverses the clock signal(XIN) to generate a clock signal(XOUT) in response to a high level of an oscillator enable signal(OSCEN) and a high level of the clock signal(XOUT) in response to a low level of the oscillator enable signal(OSCEN). An inverter(12) inverses the clock signal(XOUT) to generate a clock signal(CLK1). A first phase-locked loop(20) inputs the clock signal(CLK1) in response to a control signal(CON1) and generates a clock signal(CLK2) having a frequency different from that of a clock signal. A second phase-locked loop(30) inputs the clock signal(CLK1) in response to a control signal(CON2) and generates a clock signal(CLK3) having a frequency different from those of the clock signals(CLK1,CLK2). A first selection circuit(40) selects the clock signal(CLK2) or the clock signal(CLK3) to generate a clock signal(CLK4) in response to a first selection signal(SEL1). A distributer(50) distributes the clock signal(CLK4) to generate a clock signal(CLK5). A distributer(60) distributes the clock signal(CLK1) to generate a clock signal(CLK6). A second selection circuit(70) selects one out of clock signals(CLK4,CLK5,CLK6,CLK1) to generate a clock signal(CLK7) in response to a second selection signal(SEL2).

Description

Clock signal generating circuit and method of system on a chip

The present invention relates to a single chip system, and more particularly to a clock signal generation circuit and method of a single chip system.

A conventional method of generating a clock signal of a system on a chip (SOC) includes a method of applying a clock signal having a corresponding frequency to an input terminal directly from the outside.

However, this method is not easy to adjust the system clock frequency when it is necessary to operate fast or slow depending on the application where a single chip system is applied. That is, this method is inconvenient to change the frequency of the crystal oscillator mounted in a single chip system. Therefore, there is an inconvenience in that the product must be manufactured by dividing the frequency of the crystal oscillator into several groups during mass production.

If there is a block operated by a clock signal having a frequency other than the system clock frequency inside the single chip system, a separate pin may be provided to directly apply a clock signal having the corresponding frequency from the outside, or It is configured to generate a clock signal with the corresponding frequency by embedding one phase-locked loop inside without additional pin.

However, if the additional pins are additionally provided, the number of pins of the single-chip system increases and the crystal oscillator for generating the corresponding frequency must be separately provided.

And, if one phase-locked loop is embedded inside, for example, if a single-chip system embeds a phase-locked loop for a block such as a universal serial bus operating on a 48 MHz clock signal, the system clock Since a clock signal with 48MHz besides the frequency is necessary, the phase locked loop is limited to the clock signal generating circuit for the general purpose serial bus. In addition, there is a problem that the frequency of the clock signals that can be generated from the built-in phase locked loop must be fixed at an integer multiple of 48 MHz.

Therefore, the conventional clock signal generation circuit and method of the single-chip system has a problem that it is not possible to generate clock signals of various frequencies required in the system.

It is an object of the present invention to provide a clock signal generation circuit and method of a single chip system capable of generating clock signals of various frequencies.

A clock signal generation circuit of a single chip system of the present invention for achieving the above object is a first clock for inputting a clock signal applied from the outside and generating a first clock signal synchronized with the clock signal in response to the first control signal And a second clock signal generation means for inputting the clock signal and generating at least one second clock signal synchronized with the clock signal in response to a second control signal.

The clock signal generation circuit may further include third clock signal generation means for inputting the clock signal, the first clock signal, and the second clock signal to generate a predetermined number of clock signals having various frequencies. It features.

Clock signal generation method of a single chip system of the present invention for achieving the above object is a first clock signal generation step of inputting a clock signal applied from the outside and generating a first clock signal synchronized with the clock signal, and the clock And a second clock signal generating step of inputting a signal and generating at least one second clock signal synchronized with the clock signal.

The clock signal generating method may further include generating a third clock signal for generating a predetermined number of third clock signals having different frequencies by inputting the clock signal, the first clock signal, and the second clock signal. It is characterized by including.

1 is a block diagram showing the configuration of a clock signal generation circuit of a conventional single chip system.

Fig. 2 is a block diagram of an embodiment showing the construction of the clock signal generation circuit of the single chip system of the present invention.

* Brief description of the symbols of the main parts of the drawings *

10, 20, 30; Phase locked loop 40; First selection circuit

50, 60; Distributor 70; Second selection circuit

NA1, NA2; NAND gates I1 and I2; inverter

Hereinafter, a clock signal generating circuit of a conventional single chip system will be described with reference to the accompanying drawings before explaining a clock signal generating method and a circuit of the single chip system of the present invention.

1 is a block diagram of a clock signal generating circuit of a conventional single chip system, wherein a clock signal inside a single chip system including a NAND gate NA1, an inverter I1, a resistor R, and a phase locked loop 10 is shown in FIG. And a clock signal generation circuit external to the single-chip device system composed of a crystal oscillator (OSC) and a capacitor (C).

The function of each of the blocks shown in FIG. 1 will be described below.

The crystal oscillator OSC generates the clock signal XIN. NAND gate NA1 inverts clock signal XIN in response to oscillator enable signal OSCEN of "high" level to generate clock signal XOUT, and oscillator enable signal OSCEN of "low" level. In response to this, a clock signal XOUT of the "high" level is generated. The inverter I1 inverts the clock signal XOUT to generate the clock signal CLK1. The phase locked loop 10 inputs the clock signal CLK1 in response to the control signal CON1 to generate a clock signal CLK2 that is synchronized with the clock signal CLK1 and has a frequency different from that of the clock signal CLK1. The control signal CON1 is a parameter required for programming the output frequency of the phase locked loop 10. The control signal CON1 can be controlled by placing a system configuration register inside a single chip system.

If the general-purpose serial bus is provided in the single-chip system, the phase lock loop 10 generates the control signal CON1 such that the clock signal CLK2 of 48 MHz is generated.

That is, when the general purpose serial bus is provided in the conventional single chip system, the frequency of the clock signal CLK2 output from the phase locked loop 10 should always be fixed at 48 MHz. Therefore, a limitation arises in that a frequency of 48 MHz, 24 MHz, 12 MHz, 6 MHz, etc., which is a multiple of 48 MHz, is used as the system clock frequency.

Therefore, in this case, there are many disadvantages in optimizing the system clock frequency.

Fig. 2 is a block diagram showing the configuration of an embodiment of a clock signal generation circuit of a single chip system of the present invention. The NAND gate NA2, the inverter I2, the resistor R, the first phase synchronous loop 20, A clock signal generator circuit and a crystal oscillator (OSC) in a single-chip system composed of a two-phase synchronous loop 30, a first selection circuit 40, dividers 50 and 60, and a second selection circuit 70. And a clock signal generation circuit external to the single-chip system composed of a capacitor and a capacitor (C).

The function of each of the blocks shown in FIG. 2 will be described below.

The crystal oscillator OSC generates the clock signal XIN. NAND gate NA2 inverts clock signal XIN in response to oscillator enable signal OSCEN of "high" level to generate clock signal XOUT, and oscillator enable signal OSCEN of "low" level. In response to this, a clock signal XOUT of the "high" level is generated. The inverter I2 inverts the clock signal XOUT to generate the clock signal CLK1. The first phase synchronization loop 20 inputs the clock signal CLK1 in response to the control signal CON1 to generate a clock signal CLK2 that is synchronized with the clock signal CLK1 and has a frequency different from that of the clock signal CLK. do. The second phase synchronization loop 30 inputs the clock signal CLK1 in response to the control signal CON2 to synchronize the clock signal CLK1 with a clock signal CLK1 having a different frequency from the clock signals CLK1 and CLK2. Generate CLK3). The control signals CON1 and CON2 are parameters required for programming the output frequency of the phase locked loops 20 and 30. The first selection circuit 40 selects the clock signal CLK2 or the clock signal CLK3 in response to the first selection signal SEL1 and generates the clock signal CLK4. The divider 50 distributes the clock signal CLK4 to generate the clock signal CLK5. The divider 60 distributes the clock signal CLK1 to generate the clock signal CLK6. The second selection circuit 70 selects one of the clock signals CLK4, CLK5, CLK6, and CLK1 in response to the second selection signal SEL2 and generates the clock signal CLK7. The control signals CON1 and CON2 and the selection signals SEL1 and SEL2 can be controlled by placing a system configuration register inside a single chip system.

If the general-purpose serial bus is provided inside the single chip system, the clock signal generation circuit of FIG. 2 generates the control signal CON1 such that the phase locked loop 10 generates the clock signal CLK2 of 48 MHz. The first selection circuit 40 selects one of the two clock signals CLK2 and CLK3 to generate the clock signal CLK4 and generates the four clock signals by the second selection circuit 70. One of the clock signals (CLK4, CLK5, CLK6, CLK1) is selected and generated as a clock signal CLK7. That is, one of the five clock signals CLK2, CLK3, CLK5, CLK6 and CLK1 is generated as the clock signal CLK7 by the first and second selection signals SEL1 and SEL2. Thus, system clock signals having various frequencies can be generated.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

The clock signal generation circuit and method of the single chip system of the present invention may include at least two phase locked loops to generate clock signals having various frequencies.

Therefore, there is no need to increase the pin count of a single chip system, and there is no need to manufacture a product in several groups in mass production.

Claims (7)

First clock signal generation means for inputting a clock signal applied from the outside and generating a first clock signal synchronized with the clock signal in response to the first control signal; And And a second clock signal generating means for inputting the clock signal and generating at least one second clock signal synchronized with the clock signal in response to a second control signal. . The method of claim 1, wherein the first clock signal is And a clock frequency generating circuit having a frequency different from that of the clock signal and the second clock signal. The circuit of claim 1, wherein the clock signal generation circuit comprises: And a third clock signal generating means for inputting the clock signal, the first clock signal, and the second clock signal to generate a predetermined number of clock signals having various frequencies. Signal generating circuit. The method of claim 3, wherein the third clock signal generating means First selecting means for selectively outputting the first clock signal or the second clock signal in response to a first selection signal; First distribution means for distributing an output signal of the first selection means; Second distribution means for distributing the clock signal; And And second selection means for selectively outputting an output signal of the first selection means, an output signal of the first distribution means, an output signal of the second distribution means, or the clock signal in response to a second selection signal. Clock signal generation circuit of a single chip system, characterized in that the. A first clock signal generation step of inputting a clock signal applied from the outside and generating a first clock signal synchronized with the clock signal; And And a second clock signal generation step of inputting the clock signal and generating at least one second clock signal synchronized with the clock signal. The method of claim 5, wherein the first clock signal is And a clock frequency different from the clock signal and the second clock signal. The method of claim 5, wherein the clock signal generation method And a third clock signal generating step of inputting the clock signal, the first clock signal, and the second clock signal to generate a predetermined number of third clock signals having different frequencies. How to generate the clock signal of the system.