KR20030057808A - Method and Apparatus for detecting and transmitting of Error using PLD - Google Patents

Abstract

PURPOSE: A method and device for detecting and transmitting an error using a PLD(Programmable Logic Device) is provided to simplify configuration of an IPC module and to reduce a cost for designing a system. CONSTITUTION: A line interface module(300) communicates with a management module(320). The line interface module(300) transmits data to an IPC module(310). The IPC module(310) processes data transmitted from the line interface module(300) through the management module(320). The IPC module(310) includes a switch module(314) and a PLD(318). The switch module(314) selects a path of the data transmitted from the line interface module(300) and transmits the data through the path to the management module(320). The PLD(318) senses a signal transmission process between the line interface module(300) and the management module(320) and recognizes an error. The PLD(318) transmits a recognized error signal to the management module(320). The management module(320) receives the error signal transmitted from the PLD(318) and controls the error.

Description

Method and Apparatus for detecting and transmitting errors using PLD {Method and Apparatus for detecting and transmitting of Error using PLD}

The present invention relates to a method and apparatus for detecting and transmitting an error in an IPC (Interprocess Communication) module without a central processing unit (CPU). In particular, an error can be detected in an IPC module using a programmable logic device (PLD). A method and apparatus for detecting and communicating errors using a PLD.

IPC is a set of programming interfaces that allow programmers to create and manipulate individual programs that will run concurrently on one operating system, allowing one program to handle the needs of many users at the same time.

Because the needs of a single user can result in running multiple processes in the operating system, interprocess communication is required for these users, and IPC can make this possible.

However, there is a problem that an error occurs in the communication between processes.

Various techniques for detecting errors have been proposed to reduce the problem of such errors. For example, there is a method of detecting an error by having a separate CPU in the IPC module. Here, the method of detecting and transmitting the error through the CPU and the method of detecting the error by providing a separate error detecting pin in the line interface module will be described.

1 is a configuration diagram of an error detection and transmission apparatus through a conventional CPU.

Referring to Figure 1, the error detection and transmission system via the CPU is a line interface module (Line intrerface Module) (100a, 100b ... hereinafter referred to as 100), IPC (Interprocess Communication) module 110, management module (Management) Module 120). The line intrerface module 100 is a system that can communicate with the management module 120.

That is, the line interface module 100 transmits data to the IPC module 110.

The IPC module 110 processes data transmitted from the line interface module 100 through communication with the management module 120.

The IPC module 110 includes a switch module 114 and a CPU 118. The switch module 114 selects a path of data transmitted from the line interface module 100 and transmits the data to the management module 120. The CPU 118 monitors signal transmission processes of the line interface module 100 and the management module 120 to detect an error.

The CPU 118 transmits the detected error signal to the management module 120.

The management module 120 controls an error by receiving an error signal transmitted from the CPU 118. That is, the management module 120 controls the entire system.

2 is a configuration diagram of a system for error detection and transmission without using a conventional CPU.

Referring to FIG. 2, a system for detecting and transmitting an error without using a CPU includes a line intrerface module (200a, 200b ... hereinafter referred to as 200), an IPC module 210, and a management module. Module 220).

The line interface module 200 is a system for communicating with the management module 220. In addition, the line interface module 210 includes a separate error detection pin for detecting an error signal for each module and transmitting the detected error signal to the management module 220. The IPC module 210 includes a switch module.

Hereinafter, a detailed description of portions overlapping with FIG. 1 will be described with reference to FIG. 1. Here, referring to the difference between FIG. 1 and FIG. 2, FIG. 1 detects an error by a CPU and transmits the detected error signal to a management module. In FIG. 2, there is a separate pin for error detection in the line interface module. The error detecting pin detects an error and transmits the detected error signal to the management module.

However, in the related art, since the CPU must be used to detect and transmit an error in the IPC module, the cost is high and the configuration of the IPC module is complicated.

In addition, there is a problem that the processing time of the software takes a long time because the CPU is used in the IPC module.

In addition, since a separate error detecting pin is used in each line interface module, an error detection method is distributed to each line intrerface module.

In addition, since the management module must be connected to a plurality of line interface modules (Line intrerface Module) pins, error processing is distributed, and the back plane is complicated.

In addition, since an error signal is transmitted to the main system whenever an error occurs, the main system is overloaded.

Accordingly, an object of the present invention is to provide a method and apparatus for detecting and transmitting an error using a PLD which makes the configuration of the IPC module simple and reduces the cost of system design since the error is detected and transmitted using the PLD. .

Another object of the present invention is to provide a method and apparatus for detecting and transmitting an error using a PLD that can reduce processing time of software.

Still another object of the present invention is to provide a method and apparatus for detecting and transmitting an error using a PLD that can be processed at a high speed because error processing is concentrated because a PLD is used instead of a separate error detecting pin. .

It is still another object of the present invention to provide a method and apparatus for detecting and transmitting an error using a PLD that can reduce an input / output pin of a PLD in half using a multiplexer and reduce a MACRO CELL. It is.

Another object of the present invention is to store an error signal without transmitting an error signal to the main system whenever an error occurs, and when the error signal is a predetermined number of times, an error signal is transmitted, thereby reducing the overload of the main system. It is to provide a method and apparatus for detecting and transmitting an error using.

1 is a configuration diagram of an error detection and transmission apparatus through a conventional CPU.

2 is a configuration diagram of an apparatus for error detection and transmission without using a conventional CPU.

3 is a block diagram of an error detection and transmission apparatus using a programmable logic device (PLD) according to an embodiment of the present invention.

4A illustrates a state diagram for implementing a PLD according to a preferred embodiment of the present invention.

4B is a flow diagram for implementing a PLD according to another preferred embodiment of the present invention.

5 is a block diagram of an error detection and transmission apparatus using a PLD and a redundant CPU according to another embodiment of the present invention.

6 is a flowchart illustrating an error detection and transmission method using a PLD and a redundant CPU according to an embodiment of the present invention.

7 is a flowchart illustrating an error detection and transmission method using a PLD and a redundant CPU according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 200, 300, 500: line interface module

110, 210, 310, 510: IPC module 114, 214, 314, 514: switch module

118: CPU 120, 220, 320, 520: management module

318, 518: PLD 530: multiplexer

524: Activity CPU 528: Spare CPU

According to an aspect of the present invention to achieve the above object, in the method for detecting and transmitting an error in the data transmission process between the interface module and the management module, it is determined whether an error signal is detected, the determination result error When the signal is detected, storing the information of the state in which the error signal is detected, increasing the error counter, and using the PLD for transmitting an error signal to the management module when the increased error counter exceeds a predetermined number of times. To provide a method for detecting and communicating errors.

Information of each state in which the error signal is detected includes storing at the last stage of data transmission.

When the error signal is detected as a result of the determination, the information on the state where the error signal is detected is stored, and when the error counter is increased, the state where the error signal is detected may return to an initial state after a predetermined time elapses. .

When the incremented error counter exceeds a predetermined number of times, the controller may return to an initial state after a predetermined time elapses in transmitting an error signal to the management module.

According to another aspect of the present invention, a method for detecting and transmitting an error in a data transmission process between an interface module and a management module, wherein the management module receives active CPU information and spare CPU information and determines whether an error signal is detected. If it is determined whether or not the error signal is detected, the information on the detected state of the error signal is stored, and if the error counter is increased, and if the increased error counter exceeds a predetermined number of times, the error signal and the When the received activity CPU information is transmitted to the multiplexer, the multiplexer may provide a method for detecting and transmitting an error using a PLD for transmitting the received error signal to the activity CPU corresponding to the received activity CPU information. .

The active CPU is a CPU that is currently operating, and the spare CPU is a CPU for operating by replacing the active CPU when the active CPU has a problem.

According to another aspect of the invention, in the device for detecting an error in the signal transmission process between the interface module and the management module, switching means for switching the transmission and reception signals between the interface module and the management module, in the signal transmission process A PLD including error signal detecting means for detecting an error, storing information of the detected state, increasing the error counter, and transmitting an error signal when the increased error counter exceeds a predetermined number of times; It is possible to provide a method and apparatus for detecting and conveying an error by using the same.

The error signal detecting means may be a PLD.

According to another aspect of the present invention, an apparatus for detecting and transmitting an error in a signal transmission process between an interface module and a management module, the switching means for switching the transmission and reception signals between the interface module and the management module, the management module Receives the CPU information, stores the information of the detected state of the error signal, increases the error counter, and if the increased error counter exceeds a predetermined number of times, And a method and apparatus for detecting and transmitting an error using a PLD including an error signal detecting means for transmitting the received CPU information and a transmitting means for transmitting the received error signal to an active CPU in the received CPU information. can do.

The management module is a redundant CPU including an active CPU and a spare CPU, and the CPU information is distinguishing information between the active CPU and the spare CPU.

The transmission means may be a multiplexer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an error detection and transmission apparatus using a programmable logic division (PLD) according to an embodiment of the present invention.

Referring to FIG. 3, an error detection and transmission apparatus using a programmable logic division (PLD) includes a line intrerface module (300a, 300b, hereinafter referred to as 300), an IPC module 310, and a management module ( Management module 320).

The line intrerface module 300 is a system capable of communicating with the management module 320.

That is, the line interface module 300 transmits data to the IPC module 310.

The IPC module 310 processes data transmitted from the line interface module 300 through communication with the management module 320. The IPC module 310 includes a switch module 314 and a PLD 318.

The switch module 314 selects a path of data transmitted from the line interface module 100 and transmits the selected path to the management module 320.

The PLD 318 detects an error by monitoring a signal transmission process between the line interface module 300 and the management module 320. The PLD 318 transmits the detected error signal to the management module 320.

The management module 320 controls an error by receiving an error signal transmitted from the PLD 318. That is, the management module 320 serves to control and manage the entire system.

Hereinafter, a detailed description of a method of detecting and transmitting an error signal in a PLD will be described with reference to FIGS. 4A to 4B.

4A is a diagram illustrating a state diagram for implementing a PLD according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, since the state of S0 is a state before the system is initialized, Reset is applied, so both the clock and the count are zero. The state of S1 may be 'reset = 1' and may be an initialization step. For example, if the counter is a 3-bit count, S1 is in a '000' state.

S2 is a state where the counter is increased in the state of S1. For example, the count of S2 may be '001'. If an error occurs in the state of the S2, the information of the S2 is transmitted and stored in the last step S4. In addition, if an error occurs in S2, S4 may increase the error counter by one. Therefore, in S4, the information of S2 is stored in the form of a counter of S2 in the form of "001", an error count "once", or the like.

If an error occurs in S3 as in S2, the information of S3 is transmitted to and stored in S4, which is the last step. In addition, the S4 may increase the error counter by one. Therefore, in S4, information is stored in the form of a count '011', an error count 'twice', and the like.

Here, if the error counter of S4 is full, S4 sends an error signal to the management module. After the predetermined time elapses after the error signal is transmitted, S4 enters the state of S1.

4B is a flowchart illustrating a PLD according to another preferred embodiment of the present invention.

Referring to FIG. 4B, the reset, clock, and counter are S1, that is, an initialization state (S400). When the signal is transmitted, the state is S2 (for example, in the case of 3 bits, the counter may be 001) (S405).

If an error is detected in S2 (S410), the S2 information is transmitted and stored in S4 (S415). Then, the error counter of S4 is incremented once (S420). For example, consider the case of a 3-bit counter. When the counter of S2 is '001', the counter of S2 is stored in the form of '001' in the counter of S4. The error counter of S4 may be stored in the form of '001' or 'once'.

After performing step 420, it is determined whether the error counter of S4 is full (S425). If the result of step 425 is the error counter of S4 is full, S4 may transmit an error signal to the management module (S430).

If, as a result of step 425, the error counter of S4 is not full, S2 determines whether a predetermined time has elapsed after detecting the error (S450).

As a result of the determination in step 450, if a predetermined time elapses after the detection of the error in S2, the S2 is in the initialization state of S1 (S400). The predetermined time may be arbitrarily set or changed by a system developer or an administrator.

If the error signal is not detected in S2 as a result of the determination of step 410, the S2 is in the S3 state (S435). For example, S3 may be '010' when the counter has 3 bits. Then, it is determined whether an error signal is detected in S3 (S440).

As a result of the determination of step 440, if an error signal is detected in S3, S3 is transmitted to S4, and the counter is stored in S4 in the form of '011' or the like (S445). Then, the error counter of S4 is incremented in the form of '010' or 'twice', etc. (S420).

If an error is not detected in S3 as a result of the determination of step 440, S3 transmits data to S4 (S455).

After performing step 420, it is determined whether the error counter of S4 is full (S425). If the result of step 425 is the error counter of S4 is full, S4 transmits an error signal to the management module (S430). For example, consider the case where the maximum acceptance error counter of S4 is set to 'twice'. If an error is detected in S2 and S3, the error counter of S4 becomes full and transmits an error signal to the management module.

S4 is automatically initialized to S1 after transmitting the error signal.

5 is a diagram illustrating a configuration of an error detection and transmission apparatus using a PLD and a redundant CPU according to an exemplary embodiment of the present invention.

Referring to FIG. 5, an error detection and transmission system using a PLD and a redundant CPU includes a line intrerface module (500a, 500b,... 500 hereinafter), an IPC module 510, a management module. 520, a multiplexer (MUX) 530.

The IPC module 510 includes a switch module 514 and a programmable logic device (PLD) 518. The switch module 514 transmits and receives data between the redundant CPU and the line interface module 500.

The management module 520 includes an active CPU 524 and a standby CPU 528. The active CPU 524 may be a CPU currently operating. The standby CPU 528 may be a CPU to replace the active CPU 524 when the active CPU 524 has a problem.

In addition, the management module 520 transmits signals to and from the active CPU 524 and the spare CPU 528 to each other to the PLD 518.

The PLD 518 receives a signal transmitted from the management module 520 to distinguish the active CPU 524 from the spare CPU 528. For example, consider the case where the active CPU 524 transmits a signal at 'low' or '0', and the spare CPU 528 transmits a signal at 'HIGH' or '1'. When a signal is sent in the 'LOW' state, the PLD 518 may know that the CPU that sent the signal is an active CPU 524. As above, the PLD 518 may determine which CPU is the active CPU 524.

In addition, the PLD 518 detects an error and transmits an error signal corresponding to the detected error to the multiplexer 530. That is, the PLD 518 transmits CPU information including the information of the active CPU 524 and the spare CPU 528 and an error signal to the multiplexer 530.

The multiplexer 530 receives the CPU information and the error signal transmitted from the PLD 518 and transmits the error signal to the active CPU 524.

That is, the multiplexer 530 selects and outputs at least one input signal among error information input from a plurality of output circuits of the PLD 518.

6 is a flowchart illustrating an error detection and transmission method using a PLD and a redundant CPU according to an embodiment of the present invention.

Referring to FIG. 6, CPU information of the management module is received in a data transmission process between the line interface module and the management module (S600). That is, the discrimination information between the active CPU and the spare CPU is received from the management module. For example, consider the case where the active CPU sends a signal at 'low' or '0' and the spare CPU sends a signal at 'HIGH' or '1'. When a signal is transmitted in the 'LOW' state, the CPU that transmits the signal is an active CPU, and when the signal is transmitted in the 'HIGH' state, the CPU that transmits the signal may be a spare CPU.

After performing step 600, it is determined whether an error is detected in the data transmission process (S610). If an error is detected as a result of step 610, the CPU information and an error signal indicating an active CPU are transmitted to the multiplexer from the received CPU information (S620). Then, the multiplexer transmits the error signal to the active CPU (S630).

If, as a result of step 610, no error is detected, the step ends.

7 is a flowchart illustrating an error detection and transmission method using a PLD and a redundant CPU according to another exemplary embodiment of the present invention.

Referring to FIG. 7, in the data transmission process between the line interface module and the management module, CPU information of the management module is received (S700). The CPU information may be distinguishing information between an active CPU and a spare CPU.

After performing step 700, it is determined whether an error is detected in the data transmission process (S710). If an error is detected as a result of step 710, after storing the information of the detected state, the error counter is incremented (S720).

Then, it is determined whether the increased error counter has exceeded a predetermined number of times (S730). As a result of the determination in step 730, if the error counter exceeds a predetermined number of times, CPU information indicating an active CPU and an error signal are transmitted from the received CPU information to the multiplexer (S740). Then, the multiplexer transmits the error signal to the active CPU (S750).

If the error counter does not exceed a predetermined number of times as a result of step 730, data may be transmitted to the management module (S760).

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

As described above, according to the present invention, there is provided a method and apparatus for detecting and transmitting an error using a PLD, which simplifies the configuration of an IPC module by detecting and transmitting an error using a PLD and reduces the cost of system design. Can be.

In addition, according to the present invention, it is possible to provide a method and apparatus for detecting and transmitting an error using a PLD that can reduce the processing time of the software.

In addition, according to the present invention, since a PLD is used instead of a separate error detecting pin, a method and an apparatus for detecting and transmitting an error using a PLD capable of high-speed processing of an error can be provided. have.

In addition, according to the present invention can provide a method and apparatus for detecting and transmitting an error using a PLD that can reduce the input and output pins of the PLD in half and reduce the MACRO CELL using a multiplexer. Can be.

In addition, according to the present invention, when the error occurs, the error information is stored without transmitting the error information to the main system, and when the error information is a certain number of times, the error information is transmitted, thereby reducing the overload of the main system. It is possible to provide a method and apparatus for detecting and conveying an error by using the same.

Claims (12)

In the method for detecting and transmitting an error in the data transmission process between the interface module and the management module, Determining whether an error signal is detected; If the error signal is detected as a result of the determination, storing information of the state where the error signal is detected, and incrementing an error counter; And If the incremented error counter exceeds a predetermined number of times, transmitting an error signal to the management module; Method for detecting and transmitting errors using a PLD, characterized in that it comprises a. The method of claim 1, Information of each state in which the error signal is detected is stored at the last stage of data transmission. The method of claim 1, If the error signal is detected as a result of the determination, storing the information of the state in which the error signal is detected, and returning to the initial state after the predetermined time elapses when the error signal is detected in the step of increasing the error counter A method for detecting and communicating errors using a PLD characterized in that is performed. The method of claim 1, If the incremented error counter exceeds a predetermined number of times, the step of returning to an initial state after a predetermined time elapses in the step of transmitting an error signal to the management module is performed using the PLD. How to detect and deliver. In the method for detecting and transmitting an error in the data transmission process between the interface module and the management module, Receiving activity CPU information and spare CPU information at the management module; Determining whether an error signal is detected; If the error signal is detected, storing information on a state in which the error signal is detected, and incrementing an error counter; If the incremented error counter exceeds a predetermined number of times, transmitting the error signal and the received activity CPU information to a multiplexer; And The multiplexer transmitting the received error signal to an active CPU corresponding to the received active CPU information. Method for detecting and transmitting errors using a PLD, characterized in that it comprises a. The method of claim 5, The active CPU is a CPU that is currently operating, and the spare CPU is a CPU for operating by replacing the active CPU when the active CPU has a problem. . An apparatus for detecting and transmitting an error in a signal transmission process between an interface module and a management module, Switching means for switching transmission and reception signals between the interface module and the management module; Error signal detecting means for detecting an error in the signal transmission process, storing information of the detected state, increasing the error counter, and transmitting an error signal when the increased error counter exceeds a predetermined number of times. Apparatus for detecting and transmitting errors using a PLD comprising a. The method of claim 7, wherein And the error signal detecting means is a PLD. An apparatus for detecting and transmitting an error in a signal transmission process between an interface module and a management module, Switching means for switching transmission and reception signals between the interface module and the management module; When the management module receives the CPU information, when the error signal is detected, stores the information of the detected state of the error signal, increases the error counter, and when the incremented error counter exceeds a predetermined number of times, Error signal detecting means for transmitting an error signal and the received CPU information; And Transmission means for transmitting the received error signal to an active CPU in the received CPU information Apparatus for detecting and transmitting errors using a PLD comprising a. The method of claim 9, And the management module is a redundant CPU including an active CPU and a spare CPU. The method of claim 9, And the CPU information is distinguishing information between an active CPU and a spare CPU. The method of claim 9, And said transmitting means is a multiplexer.