KR20030053541A - Method for forming isolation layer - Google Patents
Method for forming isolation layer Download PDFInfo
- Publication number
- KR20030053541A KR20030053541A KR1020010083294A KR20010083294A KR20030053541A KR 20030053541 A KR20030053541 A KR 20030053541A KR 1020010083294 A KR1020010083294 A KR 1020010083294A KR 20010083294 A KR20010083294 A KR 20010083294A KR 20030053541 A KR20030053541 A KR 20030053541A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- oxide film
- diffusion barrier
- trench
- thermal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000002955 isolation Methods 0.000 title claims abstract description 35
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 30
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000009792 diffusion process Methods 0.000 claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000009413 insulation Methods 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910019142 PO4 Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
본 발명은 트렌치 모서리 상단부의 갭필옥사이드막이 실리콘 계면으로 꺼지는 모우트(moating) 현상을 방지할 수 있는 소자분리막 형성 방법에 관해 개시한다.The present invention discloses a method of forming a device isolation film capable of preventing a gap phenomenon in which a gap fill oxide film at an upper end of a trench corner is turned off to a silicon interface.
개시된 본 발명의 소자분리막 형성 방법은 소자의 활성영역과 분리영역이 정의된 반도체기판을 제공하는 단계와, 기판 상에 분리영역을 노출시키는 각각의 패드 산화막 및 실리콘 질화막을 형성하는 단계와, 실리콘 질화막 측면에 절연 스페이서를 형성하는 단계와, 절연 스페이서를 포함한 실리콘 질화막을 마스크로 하고 기판의 분리영역의 일부를 식각하여 트렌치를 형성하는 단계와, 트렌치 내부에 제 1열산화막을 형성 및 제거하는 단계와, 상기 결과의 트렌치 내부에 제 2열산화막을 형성하는 단계와, 제 2열산화막을 포함한 트렌치를 덮는 확산방지층을 형성하는 단계와, 확산방지층을 포함한 트렌치를 덮는 소자분리막을 형성하는 단계와, 기판 표면이 노출되는 시점까지 실리콘 질화막, 패드 산화막, 절연 스페이서 및 확산방지층을 각각 제거하되, 기판 표면으로부터 절연 스페이서 및 확산방지층의 일부를 잔류시키는 단계와, 잔류된 절연 스페이서 및 확산방지층을 포함한 기판을 덮는 제 3열산화막을 형성하는 단계와, 잔류된 절연 스페이서, 확산방지층 및 제 3열산화막을 각각 제거하는 단계를 포함한다.A method of forming a device isolation film according to the present invention includes providing a semiconductor substrate in which active regions and isolation regions of a device are defined, forming respective pad oxide and silicon nitride films exposing the isolation regions on the substrate, and forming a silicon nitride film. Forming a trench by forming an insulating spacer on the side surface, etching a part of the isolation region of the substrate using a silicon nitride film including the insulating spacer as a mask, and forming and removing the first thermal oxide film in the trench; Forming a second thermal oxide film in the resulting trench, forming a diffusion barrier layer covering the trench including the second thermal oxide film, forming a device isolation film covering the trench including the diffusion barrier layer, a substrate; The silicon nitride film, the pad oxide film, the insulating spacer, and the diffusion barrier layer are respectively removed until the surface is exposed. Leaving a portion of the insulating spacer and the diffusion barrier layer from the substrate surface, forming a third thermal oxide film covering the substrate including the remaining insulation spacer and the diffusion barrier layer, and remaining residual spacer, diffusion barrier and third layer. Removing each of the thermal oxide films.
Description
본 발명은 반도체장치의 제조 방법에 관한 것으로, 보다 상세하게는 트렌치 (trench) 모서리 상단부의 갭필옥사이드막이 실리콘 계면으로 꺼지는 모우트(moat) 현상을 방지할 수 있는 소자분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a device isolation film forming method capable of preventing a moat phenomenon in which a gap fill oxide film at an upper end of a trench is turned off to a silicon interface.
도 1a 내지 도 1d는 종래 기술에 따른 소자분리막 형성 방법을 보이기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a device isolation film according to the related art.
종래 기술에 따른 소자분리막 형성 방법은, 도 1a에 도시된 바와 같이, 먼저 실리콘기판(100) 전면에 완충 역할을 하는 패드 산화막(102)과 산화를 억제하는 실리콘 질화막(104)을 차례로 형성한다. 도면부호Ⅰ는 소자의 활성영역을 도시한 것이다.In the method of forming a device isolation film according to the related art, as shown in FIG. 1A, first, a pad oxide film 102 serving as a buffer and a silicon nitride film 104 for inhibiting oxidation are sequentially formed on the entire surface of the silicon substrate 100. Reference I shows the active area of the device.
이어서, 상기 실리콘 질화막(104) 상에 감광막(photoresist)을 도포한 후, 노광 및 현상하여 분리영역(Ⅱ)을 노출시키는 감광막 패턴(PR)(108)을 형성한다.Subsequently, a photoresist is applied on the silicon nitride film 104, and then exposed and developed to form a photoresist pattern PR 108 that exposes the separation region II.
그 다음, 도 1b에 도시된 바와 같이, 상기 감광막 패턴(108)을 식각마스크로 하고, 상기 실리콘 질화막, 패드 산화막 및 기판의 소정 깊이만큼 식각하여 샬로우 트렌치(110)를 형성한다. 그리고 감광막 패턴을 제거한다.Next, as shown in FIG. 1B, the photoresist pattern 108 is used as an etch mask, and the shallow trench 110 is formed by etching the silicon nitride film, the pad oxide film, and a predetermined depth of the substrate. Then, the photoresist pattern is removed.
이 후, 상기 트렌치 식각시 유발되는 실리콘 표면의 디펙트(defect)를 회복하기 위해, 트렌치(110)가 형성된 실리콘 기판(100)상에 1차 열산화 공정을 진행시키어 제 1열산화막(112)을 형성한다.Thereafter, in order to recover a defect of the silicon surface caused during the trench etching, a first thermal oxidation process is performed on the silicon substrate 100 on which the trench 110 is formed, and thus the first thermal oxide film 112 is formed. To form.
이어서, 도 1c에 도시된 바와 같이, 상기 제 1열산화막을 습식 식각 방법으로 제거하고, 다시 노출된 트렌치 내부에 제 2열산화 공정을 진행시키어 제 2열산화막(114)을 형성한 후, 습식 식각 공정에 의해 제 2열산화막을 제거한다. 이때, 상기 2회에 걸친 열산화 공정에 의해 각진 소자의 분리영역(Ⅱ)의 모서리가 완만하게 된다.Subsequently, as shown in FIG. 1C, the first thermal oxide film is removed by a wet etching method, and a second thermal oxidation process is performed in the exposed trench again to form a second thermal oxide film 114. The second thermal oxide film is removed by an etching process. At this time, the edges of the separation region II of the angled element are smoothed by the two times of thermal oxidation processes.
그 다음, 도 1d에 도시된 바와 같이, 상기 결과물 상에 트렌치(110) 내부를매립하는 갭필옥사이드막을 형성한 후, 상기 갭필옥사이드막을 화학기계연마(Chemical Mechanical Polishing: 이하, CMP라 칭함)공정에 의해 식각하여 실리콘 질화막이 노출되도록 평탄화시킨다.(도면부호 114)Next, as shown in FIG. 1D, after forming a gap fill oxide film filling the inside of the trench 110 on the resultant, the gap fill oxide film is subjected to chemical mechanical polishing (hereinafter referred to as CMP) process. Etched and planarized so that the silicon nitride film is exposed (reference numeral 114).
이때, 실리콘 질화막(104)과 갭필옥사이드막 사이에는 접착용 산화막(미도시)을 개재시키어 실리콘 질화막(104)과 갭필옥사이드막 간의 접착강도를 향상시킬 수도 있다.In this case, the adhesion strength between the silicon nitride film 104 and the gap fill oxide film may be improved by interposing an adhesion oxide film (not shown) between the silicon nitride film 104 and the gap fill oxide film.
그 다음, 상기 잔류된 실리콘 질화막을 인산용액을 이용하여 습식 식각한 후, 상기 잔류된 패드 산화막을 차례로 제거한다. 이때, 상기 트렌치(120) 내부에 잔류된 갭필옥사이드막이 소자분리막(114)이 된다.Then, the residual silicon nitride film is wet etched using a phosphate solution, and then the remaining pad oxide film is sequentially removed. In this case, the gap fill oxide layer remaining in the trench 120 becomes the device isolation layer 114.
그리고 도면에는 도시되어 있지 않지만, 후속으로 진행되는 이온주입 공정 시 유발되는 기판의 디펙트를 줄이기 위해, 먼저 제 3열산화막을 성장시키고 나서 웰을 형성한다. 이어, 상기 제 3열산화막을 습식 식각 공정으로 제거하고 게이트 형성 공정을 진행한다.Although not shown in the figure, in order to reduce the defect of the substrate caused during the subsequent ion implantation process, the third thermal oxide film is first grown, and then a well is formed. Subsequently, the third thermal oxide layer is removed by a wet etching process and a gate forming process is performed.
그러나, 종래의 기술에서는 3회에 걸친 열산화막의 습식 식각 공정 시, 소자영역과 분리영역의 경계부분의 패드산화막이 과도하게 식각되어 트렌치 모서리 상단부의 갭필옥사이드막이 기판 아래로 꺼져서 모우트(moat)현상이 발생된다. 따라서, 소자 구동시 소자영역의 끝단에 전기적 집중 현상이 유발되어서 소자의 전기적 열화를 가져올 뿐만 아니라, 심한 경우에는 상기 소자분리막의 과도 식각된 부위에 게이트 형성용 물질이 잔류하게 됨으로써 게이트와 이웃한 게이트의 사이가 분리되지 않아 전기적 쇼트(short)가 유발하는 문제점이 있었다.However, in the prior art, in the wet etching process of the thermal oxide film three times, the pad oxide film at the boundary between the device region and the isolation region is excessively etched so that the gap fill oxide film at the upper edge of the trench is turned off under the substrate to moat. Phenomenon occurs. Therefore, when the device is driven, an electric concentration phenomenon occurs at the end of the device region, thereby causing electrical deterioration of the device, and in severe cases, a gate forming material remains in an excessively etched portion of the device isolation layer, so that the gate is adjacent to the gate. There is a problem that the electrical short (short) caused by not separated between.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 트렌치 모서리 상단부의 갭필옥사이드막이 실리콘 계면으로 꺼지는 모우트 현상을 방지할 수 있는 소자분리막 형성 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a device isolation film capable of preventing a phenomena in which a gap fill oxide film in an upper portion of a trench corner is turned off to a silicon interface.
도 1a 내지 도 1d는 종래 기술에 따른 소자분리막 형성 방법을 보이기 위한 공정단면도.1A to 1D are cross-sectional views illustrating a method of forming a device isolation film according to the related art.
도 2a 내지 도 2h는 본 발명에 따른 소자분리막 형성 방법을 보이기 위한 공정단면도.2A through 2H are cross-sectional views illustrating a method of forming a device isolation film according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
200. 반도체기판 202.패드 산화막200. Semiconductor substrate 202. Pad oxide film
203. 절연 스페이서 204. 실리콘 질화막203. Insulation spacer 204. Silicon nitride film
208, 감광막 패턴 210. 트렌치208, photoresist pattern 210. trench
212, 214, 218. 열산화막 216. 확산방지층212, 214, 218. Thermal oxide film 216. Diffusion barrier layer
221. 소자분리막221. Device isolation film
상기 목적을 달성하기 위한 본 발명의 소자분리막 형성 방법은 소자의 활성영역과 분리영역이 정의된 반도체기판을 제공하는 단계와, 기판 상에 분리영역을 노출시키는 각각의 패드 산화막 및 실리콘 질화막을 형성하는 단계와, 실리콘 질화막 측면에 절연 스페이서를 형성하는 단계와, 절연 스페이서를 포함한 실리콘 질화막을 마스크로 하고 기판의 분리영역의 일부를 식각하여 트렌치를 형성하는 단계와, 트렌치 내부에 제 1열산화막을 형성 및 제거하는 단계와, 상기 결과의 트렌치 내부에 제 2열산화막을 형성하는 단계와, 제 2열산화막을 포함한 트렌치를 덮는 확산방지층을 형성하는 단계와, 확산방지층을 포함한 트렌치를 덮는 소자분리막을 형성하는 단계와, 기판 표면이 노출되는 시점까지 실리콘 질화막, 패드 산화막, 절연 스페이서 및 확산방지층을 각각 제거하되, 기판 표면으로부터 절연 스페이서 및 확산방지층의 일부를 잔류시키는 단계와, 잔류된 절연 스페이서 및 확산방지층을 포함한 기판을 덮는 제 3열산화막을 형성하는 단계와, 잔류된 절연 스페이서, 확산방지층 및 제 3열산화막을 각각 제거하는 단계를 포함한 것을 특징으로 한다.The device isolation film forming method of the present invention for achieving the above object is to provide a semiconductor substrate in which the active region and the isolation region of the device is defined, and forming each of the pad oxide film and silicon nitride film exposing the isolation region on the substrate; Forming a trench by forming an insulating spacer on the side of the silicon nitride film, etching a part of the isolation region of the substrate using the silicon nitride film including the insulating spacer as a mask, and forming a first thermal oxide film inside the trench. And removing, forming a second thermal oxide film in the resulting trench, forming a diffusion barrier layer covering the trench including the second thermal oxide film, and forming a device isolation film covering the trench including the diffusion barrier layer. And silicon nitride film, pad oxide film, insulating spacer and diffusion until the substrate surface is exposed. Removing each of the layers, leaving a portion of the insulating spacer and the diffusion barrier layer from the substrate surface, forming a third thermal oxide film covering the substrate including the remaining insulation spacer and the diffusion barrier layer, and remaining residual spacer and diffusion. And removing the prevention layer and the third thermal oxide film, respectively.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 본 발명에 따른 소자분리막 형성 방법을 보이기 위한 공정단면도이다.2A to 2H are cross-sectional views illustrating a method of forming a device isolation film according to the present invention.
본 발명의 소자분리막 형성 방법은, 도 2a에 도시된 바와 같이, 먼저, 소자의 분리영역(Ⅳ) 및 활성영역(Ⅲ)이 정의된 반도체기판(200) 전면에 완충 역할을 하는 패드 산화막(202)과 산화를 억제하는 실리콘 질화막(204)을 차례로 형성한다. 이때, 상기 패드 산화막(202)은 30∼300Å두께로 열산화하여 형성하고, 상기 실리콘 질화막(204)은 1000∼5000Å두께로 형성한다.In the method of forming a device isolation film of the present invention, as shown in FIG. 2A, first, a pad oxide film 202 serving as a buffer on the entire surface of the semiconductor substrate 200 in which the isolation region IV and the active region III are defined. ) And the silicon nitride film 204 which inhibits oxidation are formed in this order. At this time, the pad oxide film 202 is formed by thermal oxidation to a thickness of 30 to 300 kPa, and the silicon nitride film 204 is formed to a thickness of 1000 to 5000 kPa.
이어서, 상기 실리콘 질화막(204) 상에 감광막을 도포하고, 노광 및 현상하여 분리영역(Ⅳ)을 노출시키는 감광막 패턴(PR)(208)을 형성한다.Subsequently, a photoresist film is coated on the silicon nitride film 204, and the photoresist pattern PR (208) for exposing the isolation region (IV) is formed by exposing and developing.
그 다음, 도 2b에 도시된 바와 같이, 상기 감광막 패턴을 제거하고 나서, 상기 잔류된 실리콘 질화막(204)을 포함한 기판 전면에 실리콘 산화막을 증착한 후, 상기 실리콘 산화막에 화학적 기계적 연마 공정을 실시하여 절연 스페이서(203)를 형성한다. 이 후, 절연 스페이서(203)을 포함한 잔류된 실리콘 질화막을 마스크로 하고 상기 기판의 분리영역(Ⅳ)을 1000∼5000Å 두께로 식각하여 샬로우 트렌치(210)를 형성한다.Next, as shown in FIG. 2B, the photoresist pattern is removed, a silicon oxide film is deposited on the entire surface of the substrate including the remaining silicon nitride film 204, and then a chemical mechanical polishing process is performed on the silicon oxide film. The insulating spacer 203 is formed. Subsequently, the shallow trench 210 is formed by using the remaining silicon nitride film including the insulating spacer 203 as a mask and etching the isolation region IV of the substrate to a thickness of 1000 to 5000 microns.
이어서, 도 2c에 도시된 바와 같이, 상기 샬로우 트렌치(210) 내부를 700∼1100℃로 열산화시키어 제 1열산화막(212)을 형성한다. 이때, 상기 제 1열산화막(212)은 50∼300Å두께로 형성된다.Subsequently, as illustrated in FIG. 2C, the inside of the shallow trench 210 is thermally oxidized to 700 to 1100 ° C. to form a first thermal oxide film 212. At this time, the first thermal oxide film 212 is formed to a thickness of 50 ~ 300Å.
그 다음, 도 2d에 도시된 바와 같이, 상기 제 1열산화막을 습식 식각 공정에 의해 제거하고 나서, 상기 결과의 트렌치를 다시 열산화시키어 제 2열산화막(214)을 형성한다. 이때, 제 2열산화막(214)는 50∼300Å두께로 형성된다.Next, as shown in FIG. 2D, the first thermal oxide film is removed by a wet etching process, and the resulting trench is thermally oxidized to form a second thermal oxide film 214. At this time, the second thermal oxide film 214 is formed to have a thickness of 50 to 300 kPa.
또한, 상기 제 1, 제 2열산화막의 열산화 공정은 산소분위기에서 건식 산화 공정으로 진행하여 소자의 분리영역(Ⅳ)의 모서리 부분을 완만하게 한다.In addition, the thermal oxidation process of the first and second thermal oxide films proceeds from the oxygen atmosphere to the dry oxidation process to smooth the corners of the isolation region (IV) of the device.
도 2d에서, 점선 처리된 부분은 제 2열산화막(214) 형성 전의 도 2c에 도시된 절연 스페이서 및 제 1열산화막을 나타낸 것이다.In FIG. 2D, the dotted lines show the insulating spacer and the first thermal oxide film shown in FIG. 2C before the second thermal oxide film 214 is formed.
이 후, 도 2e에 도시된 바와 같이, 상기 결과물을 덮도록 실리콘 질화막을 증착한다. 상기 실리콘 질화막은 후속 열산화 공정 시에 유발되는 산소의 확산을 방지하는 확산방지층(216) 역할을 한다. 이때, 상기 확산방지층(216)은 30∼300Å두께로 형성된다.Thereafter, as illustrated in FIG. 2E, a silicon nitride film is deposited to cover the resultant product. The silicon nitride film serves as a diffusion barrier layer 216 to prevent diffusion of oxygen caused in a subsequent thermal oxidation process. At this time, the diffusion barrier layer 216 is formed to a thickness of 30 ~ 300Å.
이어서, 도 2f에 도시된 바와 같이, 확산방지층을 포함한 트렌치 내부를 채우도록 고밀도 플라즈마(high density plasma) 산화막, 오존티오스(O3-TEOS) 및 CVD(Chemical Vapor Deposition) 산화막 등을 이용하여 갭필옥사이드막을 증착한 후, 상기 갭필옥사이드막에 화학적 기계적 연마 공정 및 습식 식각 공정을 진행하여 단차를 조절하여 소자분리막(221)을 형성한다. 이때, 갭필옥사이드막의 연마 공정에서, 상기 갭필옥사이드막은 실리콘 질화막(204)이 충분히 노출되도록 갈아낸다. 또한, 상기 습식 식각 공정에서, 절연 스페이서의 일부가 제거된다.Subsequently, as shown in FIG. 2F, a gap fill is performed using a high density plasma oxide film, an O 3 -TEOS, a chemical vapor deposition (CVD) oxide film, or the like to fill the inside of the trench including the diffusion barrier layer. After depositing an oxide film, a chemical mechanical polishing process and a wet etching process are performed on the gap fill oxide film to form a device isolation layer 221 by adjusting a step. At this time, in the polishing process of the gap fill oxide film, the gap fill oxide film is ground so that the silicon nitride film 204 is sufficiently exposed. In addition, in the wet etching process, a part of the insulating spacer is removed.
그 다음, 도 2g에 도시된 바와 같이, 인산용액으로 실리콘 질화막을 습식 식각하고 나서, 불산 용액으로 패드 산화막을 습식 식각하여 기판을 노출시킨다. 이때, 노출된 기판 표면에는 패드 산화막 제거 시 절연 스페이서(203)는 인산용액의침투가 어려워서 일부 잔류하게 되고, 또한 실리콘 질화막 성분의 확산방지층이 일부 잔류된다. 따라서, 소자의 분리영역의 모서리 끝단부의 패드 산화막이 과도하게 식각되어 발생되는 모우트 현상을 상기 잔류된 절연 스페이서가 1차로 막아주고 2차로 확산방지층이 방지해 준다.Next, as shown in FIG. 2G, the silicon nitride film is wet-etched with a phosphoric acid solution, and the pad oxide film is wet-etched with a hydrofluoric acid solution to expose the substrate. At this time, when the pad oxide film is removed, the insulating spacer 203 is difficult to penetrate the phosphoric acid solution and remains partially on the exposed substrate surface, and the diffusion barrier layer of the silicon nitride film component remains. Accordingly, the remaining insulation spacers primarily prevent the residual phenomenon caused by excessive etching of the pad oxide film at the corner end of the isolation region of the device, and prevent the diffusion barrier layer secondarily.
이 후, 상기 습식 식각 공정이 진행된 기판에 열산화 공정을 진행하여 제 3열산화막(218)을 형성한 후, 웰 형성용 이온주입 공정을 진행한다.Thereafter, a thermal oxidation process is performed on the substrate on which the wet etching process is performed to form a third thermal oxide film 218, and then an ion implantation process for forming a well is performed.
이어서, 도 2h에 도시된 바와 같이, 상기 제 3열산화막을 제거하여 소자분리막 형성 공정을 완료한다.Subsequently, as shown in FIG. 2H, the third thermal oxide film is removed to complete the device isolation film forming process.
이상에서와 같이, 본 발명의 방법에서는 패드 산화막 및 열산화막 습식 식각 공정 시, 상기 절연 스페이서 및 확산방지층이 식각액의 침투를 방지하여 트렌치 모서리 상단부의 갭필옥사이드막이 실리콘 계면밑으로 꺼지는 모우트를 형성을 억제한다.As described above, in the method of the present invention, during the pad oxide film and the thermal oxide film wet etching process, the insulating spacer and the diffusion barrier layer prevent the infiltration of the etchant to form a moat in which the gap fill oxide film at the top of the trench corner is turned off under the silicon interface. Suppress
따라서, 소자의 전기적 열화를 방지할 뿐만 아니라 이 후 게이트 형성용 물질이 잔류됨에 따른 쇼트 현상을 방지할 수 있다.Therefore, not only the electrical deterioration of the device can be prevented, but also a short phenomenon due to the remaining material for forming a gate can be prevented.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010083294A KR20030053541A (en) | 2001-12-22 | 2001-12-22 | Method for forming isolation layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010083294A KR20030053541A (en) | 2001-12-22 | 2001-12-22 | Method for forming isolation layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030053541A true KR20030053541A (en) | 2003-07-02 |
Family
ID=32212209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010083294A Withdrawn KR20030053541A (en) | 2001-12-22 | 2001-12-22 | Method for forming isolation layer |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030053541A (en) |
-
2001
- 2001-12-22 KR KR1020010083294A patent/KR20030053541A/en not_active Withdrawn
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6326282B1 (en) | Method of forming trench isolation in a semiconductor device and structure formed thereby | |
| US6093621A (en) | Method of forming shallow trench isolation | |
| US4755477A (en) | Overhang isolation technology | |
| US6277709B1 (en) | Method of forming shallow trench isolation structure | |
| JPH0580148B2 (en) | ||
| KR100248888B1 (en) | Trench isolation manufacturing method | |
| KR100270464B1 (en) | Method of forming recessed oxide isolation | |
| JPH10335441A (en) | Manufacture of semiconductor device | |
| KR20020085390A (en) | Trench isolation method | |
| KR100245307B1 (en) | Device Separation Method of Semiconductor Device | |
| KR100289663B1 (en) | Device Separator Formation Method of Semiconductor Device | |
| KR100687854B1 (en) | Device Separating Method of Semiconductor Device | |
| KR20030053541A (en) | Method for forming isolation layer | |
| KR0172240B1 (en) | Device Separation Method of Semiconductor Devices | |
| KR20010001201A (en) | Shallow trench manufacturing method for isolating semiconductor devices | |
| KR100439105B1 (en) | Method for fabricating isolation layer of semiconductor device to improve cut-off characteristic at both corners of trench and inwe between narrow lines | |
| KR20040058798A (en) | Method for forming device isolation film of semiconductor device | |
| KR100273244B1 (en) | Method for fabricating isolation region of semiconductor device | |
| KR100408863B1 (en) | Method of forming a gate oxide in a semiconductor device | |
| KR0161727B1 (en) | Element isolation method of semiconductor device | |
| KR20030052663A (en) | method for isolating semiconductor device | |
| JP2002100670A (en) | Semiconductor device and its manufacturing method | |
| KR100245097B1 (en) | Field oxide film manufacturing method | |
| KR20010061041A (en) | Forming method for a field oxide of semiconductor device | |
| KR20000051689A (en) | Shallow trench manufacturing method for isolating semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20011222 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |