KR20030037214A - Image sensor for measuring the sheet resistance and fabricating method of the same - Google Patents

Abstract

PURPOSE: An image sensor for measuring sheet resistance is provided to increase the lifetime of an image sensor by more precisely measuring the sheet resistance of a photodiode in a deep level such that the sheet resistance is one of important process parameters. CONSTITUTION: A pixel array is prepared on a substrate(30) to substantially operate a device, including a pinned photodiode having a structure in which a p¬0 region, an n¬- region(31) and a p-epi layer are stacked. A test pattern measures the sheet resistance of the n¬- region, integrated in the substrate together with the pixel array. A test n¬- region is formed in a test p-epi layer. A dummy gate pattern(36) comes in direct contact with a test n¬- region. The p-epi layer without the p¬0 region, the test n¬- region and the dummy gate pattern are included in the test pattern.

Description

Image sensor for measuring the sheet resistance and its manufacturing method {Image sensor for measuring the sheet resistance and fabricating method of the same}

The present invention relates to an image sensor, and more particularly, to an image sensor including a test pattern for measuring sheet resistance (hereinafter referred to as Rs) in a deep photodiode region and a manufacturing method thereof.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. In a double charge coupled device (CCD), individual metal-oxide-silicon (MOS) capacitors are very different from each other. A device in which charge carriers are stored and transported in a capacitor while being located in close proximity, and CMOS (Complementary MOS) image sensor is a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. Is a device that employs a switching method that creates MOS transistors by the number of pixels and sequentially detects the output using them.

In manufacturing such various image sensors, efforts are being made to increase the photo sensitivity of the image sensor, and one of them is a light condensing technology. For example, a CMOS image sensor is composed of a photodiode for detecting light and a portion of a CMOS logic circuit for processing the detected light into an electrical signal to make data. To increase light sensitivity, the ratio of the photodiode to the total image sensor area is increased. Efforts have been made to increase (usually referred to as Fill Factor).

FIG. 1 is a unit pixel circuit diagram of a conventional CMOS image sensor, and a submicron CMOS Epi process is applied to increase sensitivity and reduce cross talk effects between unit pixels.

The operation principle of obtaining an output from such a unit pixel is as follows.

end. Turn off Tx, Rx, Sx. The low voltage buried photodiode is then fully depletion.

I. Photogenerated charge is collected in a low voltage buried photo diode.

All. After a proper integration time, the Rx is turned on to reset the floating sensing node first.

la. The unit pixel is turned on by turning on Sx.

hemp. The output voltage V1 of the source follower buffer is measured. This value merely represents the CD level shift of the floating sensing node.

bar. Turn on Tx.

four. All photogenerated charges are transported to Floating Sensing Nodes.

Ah. Turn off Tx.

character. Measure the output voltage (V2) of the source follower buffer.

car. The output signals V1-V2 are the result of the photocharge transport resulting from the difference between V1 and V2 and are pure signal values without noise. This method is called CDS (Corelated Double Sampling).

Ka. Repeat the process of 'a' to 'tea'. However, the low voltage buried photodiode is fully depleted during the 'dead' process.

On the other hand, one of the biggest factors that influence the performance of the image sensor is a photodiode. Therefore, it is also very important to accurately test the characteristics of the photodiode, and the electrical characteristics in the deep n-region of the photodiode is just as important as the capacitance.

FIG. 2 (a) is a plan view showing a test pattern of an image sensor for measuring sheet resistance in a deep n-region according to the prior art, and FIG. 2 (b) is taken along the line A-A 'of FIG. It is a cross section.

Referring to FIGS. 2A and 2B, a photodiode 21 is formed through ion implantation on a substrate 20 on which a P ++ layer and a P-epi layer are formed. It is formed under the substrate 20 and is formed in the active region 22. A field insulating film 22 is formed to separate the active region 22 from other elements. The photodiode 21 and the photodiode 21 An n + region (source / drain junction) is formed so as to overlap. In addition, a metal line 23 is formed to flow a current through the test pattern to measure sheet resistance for measuring sheet resistance, and a '+' terminal is formed at one side 24a and a '-' terminal at the other side. Connect it.

The photodiode is formed by the test pattern having the above-described structure, which is formed on the same chip as the actual image sensor element, and thus is formed through the same step in the manufacturing process, but it is defined as Rs of the photodiode n-region. Since it is for measuring, a gate electrode or the like is not formed.

Rs is one of the most important process control monitoring (PCM) parameters to determine whether or not n- ion implantation proceeds in the form of tilt or twist.

In addition, in the early image sensor manufacturing process, a mask for forming the P0 region of the photodiode was manufactured and used separately, but recently, impurity concentration and energy are controlled during ion implantation due to the complexity of the process and the increase in manufacturing cost. Blank IMP is used to control the profile alone.

On the other hand, there is an advantage in the formation of the unit pixel (Unit pixel) during the front ion implantation, the following problem occurs in the test pattern for measuring the Rs of the n-region shown in FIG.

That is, in the unit pixel, a P / N / P structure is formed to form an ideal photodiode. However, in this case, the same structure, that is, a P / N / P structure, is formed in the test pattern region for measuring Rs. Is formed.

The sheet resistance of the n-region can be accurately measured only in pure form, that is, in a P-type substrate having a P-type substrate and an n-region. Thus, as described above, since P0 is formed on the n-region, pure sheet resistance of n- becomes virtually difficult.

The present invention proposed to solve the above problems of the prior art, an object thereof is to provide an image sensor and a method of manufacturing the same that can more accurately measure the sheet resistance of the deep n-region of the photodiode.

1 is a unit pixel circuit diagram of a conventional CMOS image sensor;

2 (a) is a plan view showing a test pattern of an image sensor for measuring sheet resistance in a deep n-region according to the prior art;

2 (b) is a cross-sectional view taken along the line A-A 'of FIG. 2 (a);

3 (a) and 3 (b) are a plan view and a cross-sectional perspective view of a test pattern for measuring sheet resistance according to an embodiment of the present invention;

4A to 4B are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention;

5A to 5B are cross-sectional views illustrating a manufacturing process of an image sensor according to another embodiment of the present invention;

Figure 6 is a plan view showing a test pattern of the image sensor according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30: substrate

31: n-region

32: field insulating film

33: metal line

34a, 34b: external terminal

35: source / drain

36: dummy gate pattern

In order to achieve the above object, the present invention provides a pixel array including a pinned photodiode having a structure in which a P0 region / n-region / P epi layer is stacked; And a test pattern integrated on the same substrate together with the pixel array and measuring a sheet resistance of the n-region, wherein the test pattern is provided to the P epi layer and the test P epi layer without a P 0 region. And a dummy gate pattern directly contacted on the test n-region.

Preferably, the test pattern may further include an ion implantation blocking layer provided to overlap the n- region in a partial region in which the dummy gate pattern is opened.

The ion implantation blocking layer has a width of 0.3 ㎛ to 0.4 ㎛,

The test pattern may include: a source / drain junction for overlapping the n-region and a part thereof to provide a flow of an electrical signal to the n-region when measuring sheet resistance; And a metal line contacting the source / drain junction in a region where the n-region and the source / drain junction overlap each other, for inputting and outputting an electrical signal from the outside.

The present invention also provides a pixel array including a pinned photodiode having a structure in which a P0 region / n-region / P epi layer is stacked, and a test pattern for measuring sheet resistance of the n-region on the same substrate. An image sensor manufacturing method for simultaneously integrating an image sensor, the method comprising: forming a test pattern in a test n-region without using a test P0 region using a gate pattern of the pixel array as a mask. do.

The present invention also provides a pixel array including a pinned photodiode having a structure in which a P0 region / n-region / P epi layer is stacked, and a test pattern for measuring sheet resistance of the n-region on the same substrate. An image sensor manufacturing method for simultaneously integrating a semiconductor device, the method comprising: forming a gate pattern in the pixel array region, and forming a dummy gate pattern having a groove having a predetermined width in the test pattern region; The ion implantation is performed to simultaneously form an n-region for a photodiode in which one side overlaps with the gate pattern and a n-region for surface current measurement on a substrate under the groove of the test pattern region under the substrate of the pixel array region. Making; Forming an insulating layer on an entire surface of the substrate on which the n-region is formed; Forming a spacer on the gate pattern sidewall of the pixel array region by etching the entire surface of the insulating layer and forming an ion implantation blocking layer remaining in the groove on the test pattern; And P0 extended from the substrate surface to the n-region by performing ion implantation on the entire surface of the substrate including the pixel array region where the n-region is formed and the test pattern region where the ion implantation blocking layer is formed. It provides a method for manufacturing an image sensor comprising forming a region.

The present invention also provides a pixel array including a pinned photodiode having a structure in which a P0 region / n-region / P epi layer is stacked, and a test pattern for measuring sheet resistance of the n-region on the same substrate. A method of manufacturing an image sensor for simultaneously integrating a photovoltaic device, the method comprising: implanting ions into an n-region for a photodiode under a substrate of the pixel array region and an n-region for measuring surface current under the substrate of the test pattern region; Simultaneously forming; A gate pattern may be formed in the pixel array region, the gate pattern aligned to overlap one side of the n-region, and the test pattern region may cover at least the n-region and n of the test pattern region during ion implantation to form a subsequent P0 region. Forming a dummy gate pattern for blocking ion implantation into the region; And implanting ion into the entire surface of the substrate including the pixel array region having the gate pattern and the test pattern region having the dummy gate pattern, thereby forming a P0 region extending from the substrate surface to the n-region only in the pixel array region. It provides an image sensor manufacturing method comprising the step of forming.

The present invention relates to a pixel array having a P / N / P structure photodiode and an n-region in a test pattern region during a front ion implantation process for forming a P0 region when an image sensor is integrated with a test pattern for measuring sheet resistance. It is possible to measure the sheet resistance of the pure n-region by preventing the formation of the P0 region on the phase.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 (a) and 3 (b) show a plan view and a cross-sectional perspective view of a test pattern for measuring sheet resistance according to an embodiment of the present invention, respectively, and FIG. 3 (b) shows BB ′ of FIG. 3 (a). It shows a cut in the direction.

3 (a) to 3 (b), the image sensor of the present invention includes a pinned photodiode having a structure in which a P0 region / n-region / P epi layer is stacked to provide a substrate for substantial device driving. A pixel array provided at 30) and integrated with the pixel array on the same substrate, and including a test pattern for measuring sheet resistance of the n-region 31, wherein the test pattern includes a P epi layer without a P0 region, and a test pattern. The test n-region 31 provided in the P epitaxial layer and a partial region in which the dummy gate pattern 36 and the dummy gate pattern 36 directly contacted on the test n-region 31 are opened. and an ion implantation blocking layer 37 provided overlapping with the n-region 31.

Here, the ion implantation blocking layer 37 has a width of 0.3 μm to 0.4 μm, and the test pattern overlaps an n-region 31 with a part thereof, so that an electrical signal to the n-region 31 when measuring sheet resistance. The source / drain junction 35 and n / region 31 and the source / drain junction 35 in contact with the overlapped region of the source / drain junction 35 to provide a flow of the electrical signal from the outside are contacted. A metal line 33 for inputting and outputting is further provided, and the metal line 33 is connected to external terminals 34a and 34b for inputting and outputting electrical signals.

In the image sensor having the above-described configuration, the n-region 31 is formed on the n-region 31 because the formation of the P0 region by the subsequent front ion implantation process is blocked in the test pattern region by the ion implantation blocking layer 37. Since it is in direct contact with the upper dummy gate pattern 36, it is possible to measure Rs in the pure test n-region 31.

Here, since the dummy test pattern 36 is formed at the same time as the gate pattern of the pixel array region during the manufacturing process, the constituent material is the same, but the pixel array region together with the ion implantation blocking layer 37 is not performed as a gate electrode. In the test pattern region according to the ion implantation for the formation of the subsequent P0 region in, the n-region and the P0 region are blocked from contacting each other.

Here, the sheet resistance measurement is as follows, for example, '+ a' terminal '34b' to '34a' among the external terminals 34a and 34b connected to the metal line 33 contacted to the source / drain junction 35. When the voltage is applied by connecting the '-' terminals to each other, a current flowing across the n-region 31 flows in the source / drain junction 35. Based on this, the resistance per unit area in the n-region 31 is defined. Rs can be measured.

An image sensor manufacturing process according to an embodiment of the present invention having the above-described configuration will be described in detail with reference to FIGS. 4A to 4B, wherein the substrate 40 has a high concentration of a P ++ layer and a P epi layer. As used herein, the substrate 40 is referred to for simplicity of the drawings.

The image sensor of the present invention simultaneously integrates a pixel array including a pinned photodiode having a stacked structure of a P0 region / n-region / P epi layer and a test pattern for measuring Rs of an n-region on the same substrate. It relates to an image sensor manufacturing process.

First of all, the drive gate (Dx) serving as a source follower and the switching gate (addressing) can be addressed by switching. A step of forming a P-well (not shown) is carried out so as to contain (Select Gate, Sx).

Subsequently, the field insulating film 41 is locally formed on the substrate 40, and then gate patterns 42a and 43a, for example, transfer gates are formed in the pixel array region away from the field insulating film 41. This serves to transport the photoelectrons from the photodiode to the floating sensing node (hereinafter referred to as FD), in which the gate insulating layer 42a and the gate conductive layer 43a are stacked. At this time, dummy gate patterns 42b and 43b having grooves 44 having a width of 0.3 μm to 0.4 μm are formed in the test pattern area, and the dummy gate patterns 42b and 43b are gate patterns in the pixel array area. Since the constituent materials are not the same as the gate electrodes (42a, 43a), only the constituent materials are the same, and thus, the names are described above, which prevents the formation of the P0 region on the test n-region during subsequent P0 ion implantation. It serves as a kind of ion implantation blocking layer.

Subsequently, ion implantation is performed to form an n-region for photodiodes in which one side overlaps the gate patterns 42a and 43a in the lower portion of the substrate 40 in the pixel array region. In this case, the groove 44 is formed in the test pattern region. A test n-region is formed below the formed substrate 40 for measuring Rs, which is performed at the same time.

Specifically, using the ion implantation mask 45 to dope the N-type impurities in a low concentration using a high energy, for example 160KeV to 180KeV energy, n- for the photodiode of the pixel array under the open substrate 40 The test n-regions of the region and the test pattern region are formed.

Next, as illustrated in FIG. 4B, the ion implantation mask 45 is removed through a PR strip, and a nitride film or the like is deposited on the entire surface, and then the entire surface is etched. In the pixel array region, a gate pattern ( Spacers 46a are formed on sidewalls 42a and 43a, and an ion implantation blocking layer 46b buried in the grooves 44 is formed in the test pattern region, which is a narrow width as described above. 44 is formed to remain in the groove 44, and the nitride film material deposited on the dummy gate pattern 43b is removed during the entire etching process, and the spacers are formed on the sidewalls of the gate patterns 42a and 43a of the pixel array region. 46a) remain in the form. Therefore, it is preferable to achieve the above profile after etching by appropriately etching conditions.

Here, the spacer 46a in the pixel array region is to form a lightly doped drain (LDD) through subsequent ion implantation to suppress a hot carrier effect and the like, and a test pattern region. The ion implantation blocking layer 46b at is intended to block P0 ion implantation into the test n-region following subsequent P0 frontal implantation (Blanket IMP).

Subsequently, a high concentration of N-type impurities for FD formation are ion-implanted to form an n + region, that is, a source / drain, whereby an FD is formed in the pixel array region, and the test pattern region is an N-region for measuring Rs. A metal line contact is formed to provide a flow of electrical signals.

Subsequently, ion implantation is performed to form a P-type electrode for photodiodes, whereby ion implantation is carried out.

At this time, in the pixel array region, a P0 region is formed by extending from the surface of the substrate 40 into the n-region for the photodiode, thereby forming a photodiode while forming a depletion region by P / N / P junction.

On the other hand, in the test pattern region, since P0 is blocked by the ion implantation blocking layer 46b, the P0 region is not in contact with the n-region, so that the pure n-region exists.

Subsequently, although not shown in the drawing, a metal line contacted with n + is formed to form a metal line contacted with an FD or gate patterns 42a and 43a in the pixel array region, and an Rs measurement is performed in the test pattern region. A metal line for contact is made.

Subsequently, the manufacturing process of the image sensor is completed by forming the color filter and the microlens.

As described above, in one embodiment of the present invention, by changing only the dummy gate pattern in the test pattern region without changing a separate process order for forming a conventional pixel array, n-, which is one of the most variables in the process progression, When using a test pattern for measuring the sheet resistance of the region, it is possible to measure the sheet resistance of the pure n-region, thereby increasing its accuracy, and thus improving the yield of the image sensor can be expected.

FIG. 6 is a plan view illustrating a test pattern of an image sensor according to another exemplary embodiment of the present invention, which has the same configuration as that of FIG. 3 (a), but no groove is formed in the dummy gate pattern 36 ′. It is formed to cover the top of the test n-region 31 except the top of the source / drain junction 35 for subsequent metal line 33 contacts.

Here, the same configuration as that of FIG. 3A is omitted for simplicity of description.

4A to 4B are cross-sectional views illustrating an easy sensor manufacturing process according to another exemplary embodiment of the present invention, which will be described in detail with reference to FIGS. 5A to 5B, wherein the substrate 50 has a high concentration of a P ++ layer. And since the P epi layer is laminated, it is referred to as a substrate 50 for simplicity of the drawings.

The image sensor of the present invention simultaneously integrates a pixel array including a pinned photodiode having a stacked structure of a P0 region / n-region / P epi layer and a test pattern for measuring Rs of an n-region on the same substrate. It relates to an image sensor manufacturing process.

First of all, the drive gate (Dx) serving as a source follower and the switching gate (addressing) can be addressed by switching. A step of forming a P-well (not shown) is carried out so as to contain (Select Gate, Sx).

Subsequently, a field insulating film 51 is formed locally on the substrate 50, and then an ion implantation mask 52 for n-ion implantation is formed to form a photodiode forming region of the pixel array region and a field insulating layer of the test pattern region ( The test n-region formation region is opened in the region except for 51).

Subsequently, ion implantation is performed to form an n-region for a photodiode under the substrate 50 of the pixel array region. In this case, a test n-region for measuring Rs is formed below the substrate 50 in the test pattern region. Formed, which is done simultaneously.

On the other hand, since the n-ion implantation is performed in the pixel array region without the gate pattern being formed, the self-alignment to overlap with the side surface by the gate pattern cannot be performed, so that the ion implantation mask 52 is blocked to prevent the gate formation region. Manufacture precisely and control ion implantation energy and doping concentration precisely even during ion implantation.

Next, as shown in FIG. 5B, the ion implantation mask 52 is removed through a PR strip, and then gate patterns 53a and 54a, for example, transfer, are arranged on the pixel array regions aligned to overlap the n-regions. A gate is formed, which serves to transport the photoelectrons from the photodiode to the floating sensing node (hereinafter referred to as FD), the gate insulating film 53a and the gate conductive layer 54a. This is laminated. In this case, the dummy gate patterns 53b and 54b are formed in the test pattern region to cover the test n-region except for the source / drain (not shown), and the dummy gate patterns 53b and 54b are formed in the pixel array region. Since the constituent materials are not the same as the gate electrodes of the gate patterns 42a and 43a in Eq. It serves as a kind of ion implantation blocking layer that prevents it from becoming.

Subsequently, after the nitride film or the like is deposited on the entire surface, the entire surface is etched. In the pixel array region, spacers 55 are formed on the sidewalls of the gate patterns 53a and 54a, and removed in the test pattern region.

Here, the spacer 55 in the pixel array region is for forming LDD through subsequent ion implantation to suppress a hot carrier effect or the like.

Subsequently, a high concentration of N-type impurities for FD formation are ion-implanted to form an n + region, that is, a source / drain, whereby an FD is formed in the pixel array region, and the test pattern region is an N-region for measuring Rs. A metal line contact is formed to provide a flow of electrical signals.

Subsequently, ion implantation is performed to form a P-type electrode for photodiodes, whereby ion implantation is carried out.

At this time, in the pixel array region, a P0 region is formed by extending from the surface of the substrate 50 into the n-region for the photodiode, thereby forming a depletion region by P / N / P junction, thereby forming a photodiode.

On the other hand, in the test pattern region, since the P0 is blocked by the dummy gate patterns 53b and 54b, the P-region is not in contact with the n-region, so that the pure n-region exists.

Subsequently, although not shown in the drawing, a metal line contacted with n + is formed to form a metal line contacted with an FD or gate patterns 53a and 54a in the pixel array region, and an Rs measurement is performed in the test pattern region. A metal line for contact is made.

Subsequently, the manufacturing process of the image sensor is completed by forming the color filter and the microlens.

As described above, in another embodiment of the present invention, a conventional process sequence for forming a pixel array is changed, that is, ion implantation for forming an n-region is performed before forming a gate pattern. The dummy gate pattern is changed to cover the test n-region except for the test source / drain formation region, thereby reducing the pure sheet resistance of the n-region when using the test pattern for measuring the sheet resistance of the n-region, which is one of the most variables in the process progression. Since the accuracy of the measurement can be increased, the yield of the image sensor can be expected.

According to the present invention made as described above, it is possible to form a deep n-region of the pinned photodiode into a pure n-region when measuring the sheet resistance, which is one of the biggest variables in the process progress, more accurate in the sheet resistance measurement By monitoring the pure sheet resistance, it is possible to sensitively detect and take measures such as the occurrence of abnormality of the process to which the inclined or twin type ion implantation is applied and the shift of the characteristics of the ion implantation equipment when forming photodiode. It is expected to contribute.

In addition, it was found through the embodiment that the image sensor having a stable optical characteristics can be implemented through the proper control and monitoring of the deep n-region ion implantation process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can be expected to be an excellent effect that can ultimately improve the yield of the image sensor by enabling more accurate measurement of the sheet resistance at the deep level of the photodiode, which is one of the largest process parameters of the image sensor. .

Claims (8)

A pixel array provided on a substrate for substantially device driving, including a pinned photodiode having a structure in which a P0 region / n-region / P epi layer is stacked; And It is integrated on the same substrate with the pixel array, and includes a test pattern for measuring the sheet resistance of the n-region, The test pattern may include an P epi layer without a P0 region, a test n-region provided in a test P epi layer, and a dummy gate pattern directly contacted on the test n-region. sensor. The method of claim 1, The test pattern may further include an ion implantation blocking layer provided to overlap the n-region in a partial region where the dummy gate pattern is opened. The method of claim 2, The ion implantation blocking layer has a width of 0.3 ㎛ to 0.4 ㎛. The method of claim 1, The test pattern is, A source / drain junction for overlapping the n-region and a portion thereof to provide a flow of an electrical signal to the n-region when measuring sheet resistance; And A metal line contacting the source / drain junction in a region where the n-region and the source / drain junction overlap each other to input and output an electrical signal from the outside; Image sensor characterized in that it further comprises. A pixel array including a pinned photodiode having a structure in which a P0 region / n-region / P epi layer is stacked, and an image sensor manufacturing method for simultaneously integrating a test pattern for measuring sheet resistance of the n-region on the same substrate. , And using the gate pattern of the pixel array as a mask to form the test pattern in a test n-region without a test P0 region. A pixel array including a pinned photodiode having a structure in which a P0 region / n-region / P epi layer is stacked, and an image sensor manufacturing method for simultaneously integrating a test pattern for measuring sheet resistance of the n-region on the same substrate. , Forming a gate pattern in the pixel array region, and forming a dummy gate pattern having a groove having a predetermined width in the test pattern region; Ion implantation is performed to simultaneously form an n-region for a photodiode in which one side overlaps the gate pattern and a n-region for surface current measurement on a substrate under the groove of the test pattern region under the substrate of the pixel array region. Making; Forming an insulating layer on an entire surface of the substrate on which the n-region is formed; Forming a spacer on the gate pattern sidewall of the pixel array region by etching the entire surface of the insulating layer and forming an ion implantation blocking layer remaining in the groove on the test pattern; And A P0 region extending from the substrate surface to the n-region by performing ion implantation on the entire surface of the substrate including the pixel array region where the n-region is formed and the test pattern region where the ion implantation blocking layer is formed. Forming steps Image sensor manufacturing method comprising a. The method of claim 6, The groove has a width of 0.3 ㎛ to 0.4 ㎛ characterized in that the manufacturing method of the image sensor. A pixel array including a pinned photodiode having a structure in which a P0 region / n-region / P epi layer is stacked, and an image sensor manufacturing method for simultaneously integrating a test pattern for measuring sheet resistance of the n-region on the same substrate. , Performing ion implantation to simultaneously form an n-region for a photodiode under the substrate of the pixel array region and an n-region for measuring surface current under the substrate of the test pattern region; A gate pattern may be formed in the pixel array region, the gate pattern aligned to overlap one side of the n-region, and the test pattern region may cover at least the n-region and n of the test pattern region during ion implantation to form a subsequent P0 region. Forming a dummy gate pattern for blocking ion implantation into the region; And Ion implantation is performed on the entire surface of the substrate including the pixel array region in which the gate pattern is formed and the test pattern region in which the dummy gate pattern is formed to form a P0 region extending from the substrate surface to the n-region only in the pixel array region. Steps to Image sensor manufacturing method comprising a.