KR20030028603A - Pll circuit for network synchronization system - Google Patents

Pll circuit for network synchronization system Download PDF

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Publication number
KR20030028603A
KR20030028603A KR1020010058302A KR20010058302A KR20030028603A KR 20030028603 A KR20030028603 A KR 20030028603A KR 1020010058302 A KR1020010058302 A KR 1020010058302A KR 20010058302 A KR20010058302 A KR 20010058302A KR 20030028603 A KR20030028603 A KR 20030028603A
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South Korea
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clock signal
difference
network
counter
difference value
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KR1020010058302A
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Korean (ko)
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구강모
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엘지전자 주식회사
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Publication of KR20030028603A publication Critical patent/KR20030028603A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1972—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for reducing the locking time interval

Abstract

PURPOSE: A PLL(Phase Locked Loop) circuit of a network synchronous system is provided, which outputs a value corresponding to a difference between a network synchronous pulse and a feedback pulse in a difference counter, and accords phases of the network synchronous pulse and a system synchronous pulse accurately and rapidly. CONSTITUTION: According to the network synchronous system outputting a system clock signal through a PLL synthesizer(21) and a voltage controlled oscillator(23) and dividers(24,26), a difference counter(27) outputs a sign bit and a difference value between the system clock signal and a network synchronous pulse. And a divider control logic part(28) divides an output clock signal of the voltage controlled oscillator with a division ratio corresponding to the above difference value and then supplies it to the PLL synthesizer.

Description

망 동기 시스템의 피엘엘 회로{PLL CIRCUIT FOR NETWORK SYNCHRONIZATION SYSTEM}PLEL CIRCUIT FOR NETWORK SYNCHRONIZATION SYSTEM

본 발명은 망 동기 시스템에서 PLL 제어기술에 관한 것으로, 특히 보다 안정적이고 빠른 시간 내에 망 동기를 이룰 수 있도록 한 망 동기 시스템의 피엘엘 회로에 관한 것이다.The present invention relates to a PLL control technique in a network synchronization system, and more particularly, to a PEL circuit of a network synchronization system that can achieve network synchronization in a more stable and faster time.

일반적으로, 망 동기 시스템의 피엘엘 회로에 있어서는 피엘엘 신서사이저가 기준 클럭신호와 디바이더 콘트롤 로직부의 출력신호를 비교하여 그에 따른 발진 제어신호를 발진기(VCXO)측으로 출력하고, 이에 의해 발진기의 발진주파수 조정되게 되어 있었다. 이때, 상기 디바이더 콘트롤 로직부는 디퍼런스 카운터로부터 입력되는 부호비트에 따라 상기 발진기로부터 궤환되는 펄스를 제어하여 피엘엘 신서사이저에 공급한다.In general, in the PEL circuit of the network synchronization system, the PEL synthesizer compares the reference clock signal with the output signal of the divider control logic unit and outputs the oscillation control signal according to the oscillator (VCXO), thereby adjusting the oscillation frequency of the oscillator. It was supposed to be. At this time, the divider control logic unit controls the pulse fed back from the oscillator according to the code bit input from the difference counter to supply to the PEL synthesizer.

이와 같은 위상 록킹 과정을 통해 망동기 펄스와 시스템 동기펄스의 위상이 서로 일치하게 된다.Through this phase locking process, the phases of the network synchronizer pulse and the system synchronization pulse coincide with each other.

이와 같이, 종래의 망 동기 시스템의 피엘엘 회로에 있어서는 디바이더 콘트롤 로직부는 단지 디퍼런스 카운터로부터 입력되는 부호비트에 따라 피엘엘 신서사이저에 공급하는 펄스를 제어하게 되므로, 망동기 펄스와 시스템 동기 펄스간의 차가 클 때 동기를 맞추는데 시간이 많이 소요되고, 그 차가 무시할 만큼 작은 경우에는 두 펄스가 서로 일치되지 않고, 도 1에서와 같이 시스템 동기 펄스가 앞서거니 뒤서거니 하는 불일치 현상이 발생되었다.As described above, in the PEL circuit of the conventional network synchronization system, the divider control logic unit merely controls the pulse supplied to the PEL synthesizer according to the code bit input from the difference counter, so that the difference between the network synchronizer pulse and the system synchronization pulse is different. When it is large, it takes a long time to synchronize, and when the difference is small enough to neglect, the two pulses do not coincide with each other, and as shown in FIG.

따라서, 본 발명의 목적은 디퍼런스 카운터에서 망 동기펄스와 궤환되는 펄스의 차에 상응하는 값을 출력하도록 하고, 이를 이용하여 망동기 펄스와 시스템 동기펄스의 위상을 신속 정확하게 일치시키는 망 동기 시스템의 피엘엘 회로를 제공함에 있다.Accordingly, an object of the present invention is to output a value corresponding to a difference between a network synchronization pulse and a feedback pulse at a difference counter, and use the same to quickly and accurately match a phase of a network synchronization pulse with a system synchronization pulse. To provide the PIEL circuit.

도 1의 (a),(b)는 종래 기술에 의한 망동기 및 시스템 동기 펄스의 파형도.1A and 1B are waveform diagrams of a network synchronizer and a system synchronization pulse according to the prior art;

도 2는 본 발명에 의한 망 동기 시스템의 피엘엘 회로의 블록도.2 is a block diagram of a PEL circuit of a network synchronization system according to the present invention.

도 3의 (a),(b)는 본 발명에 의한 망동기 및 시스템 동기 펄스의 파형도.3 (a) and 3 (b) are waveform diagrams of a network synchronizer and a system synchronization pulse according to the present invention;

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

21 : 피엘엘 신서사이저22 : 저역필터21: Piel Synthesizer 22: Low pass filter

23 : 전압제어 발진기24,26 : 분주기23: voltage controlled oscillator 24, 26: divider

25 : 망동기 카운터27 : 디퍼런스 카운터25: Synchronous counter 27: Difference counter

28 : 디바이더 콘트롤 로직부28: divider control logic section

도 2는 본 발명에 의한 망 동기 시스템의 피엘엘 회로의 일실시 예시 블록도로서 이에 도시한 바와 같이, 외부로부터 입력되는 기준클럭신호(Ref_CLK)와 디바이더 콘트롤 로직부(28)에서 출력되는 클럭신호를 비교하여 그 차에 상응되는 레벨의 전압을 출력하는 피엘엘 신서사이저(21)와; 상기 피엘엘 신서사이저(21)의 출력 전압을 평탄화 처리하기 위해 저역 필터링하는 저역필터(22)와; 상기 저역필터(22)의 출력전압에 상응되는 주파수의 클럭신호를 생성하는 전압제어 발진기(VCXO)(23)와; 상기 전압제어 발진기(23)에서 출력되는 클럭신호를 2분주하여 시스템 클럭신호(S_CLK)로 출력하는 분주기(24)와; 상기 시스템 클럭신호(S_CLK)를 카운트하여 카운트값에 상응되는 시스템동기 펄스(SS_PLS)를 발생하는 망동기 카운터(25)와; 상기 망동기 카운터(25)를 통해 공급되는 시스템 클럭신호를 X배 분주하여 시스템동기 클럭신호(SS_CLK)로 출력하는 분주기(26)와; 상기 시스템동기 펄스(SS_PLS)와 외부로부터 입력되는 망동기 펄스(NET_PLS)를 비교하여 그에 따른 부호비트(SIG_Bit) 및 차값(DIFF_V)을 출력하는 디퍼런스 카운터(27)와; 상기 부호비트(SIG_Bit) 및 차값(DIFF_V)에 상응되는 분주비로 상기 전압제어 발진기(23)의출력 클럭신호를 분주하여 상기 피엘엘 신서사이저(21)에 공급하는 디바이더 콘트롤 로직부(28)로 구성한 것으로, 이와 같이 구성한 본 발명의 작용을 첨부한 도 3을 참조하여 상세히 설명하면 다음과 같다.FIG. 2 is a block diagram of a PEL circuit of a network synchronization system according to an exemplary embodiment of the present invention. As shown therein, a reference clock signal Ref_CLK and a clock signal output from the divider control logic unit 28 are input from the outside. A PEL synthesizer 21 for comparing and outputting a voltage having a level corresponding to the difference; A low pass filter 22 for low pass filtering to flatten the output voltage of the PEL synthesizer 21; A voltage controlled oscillator (VCXO) 23 for generating a clock signal having a frequency corresponding to the output voltage of the low pass filter 22; A divider 24 for dividing the clock signal output from the voltage controlled oscillator 23 into a system clock signal S_CLK; A synchronizer counter 25 for counting the system clock signal S_CLK and generating a system synchronization pulse SS_PLS corresponding to a count value; A divider 26 for dividing the system clock signal supplied through the network synchronizer counter 25 by X times and outputting the system clock signal SS_CLK; A difference counter 27 for comparing the system synchronization pulse SS_PLS with a network synchronization pulse NET_PLS inputted from the outside and outputting a corresponding bit SIG_Bit and a difference value DIFF_V; The divider control logic unit 28 divides the output clock signal of the voltage controlled oscillator 23 at the division ratio corresponding to the code bit SIG_Bit and the difference value DIFF_V and supplies the divided signal to the PLS synthesizer 21. When described in detail with reference to Figure 3 attached to the operation of the present invention configured as described above are as follows.

피엘엘 신서사이저(21)는 외부로부터 입력되는 기준클럭신호(Ref_CLK)와 디바이더 콘트롤 로직부(28)에서 출력되는 클럭신호를 비교하여 그 차에 상응되는 레벨의 전압을 출력하고, 저역필터(22)는 그 피엘엘 신서사이저(21)의 출력전압을 저역필터링하여 평탄화된 형태의 제어전압을 출력한다.The PEL synthesizer 21 compares the clock signal output from the divider control logic unit 28 with the reference clock signal Ref_CLK input from the outside and outputs a voltage having a level corresponding to the difference, and the low pass filter 22. Low-pass filter the output voltage of the PEL synthesizer 21 and outputs the control voltage of the flattened form.

전압제어 발진기(23)는 상기 저역필터(22)의 출력전압에 상응되는 주파수의 클럭신호를 생성하고, 이는 분주기(24)를 통해 2분주되어 시스템 클럭신호(S_CLK)로 출력된다.The voltage controlled oscillator 23 generates a clock signal having a frequency corresponding to the output voltage of the low pass filter 22, which is divided into two through the divider 24 and output as a system clock signal S_CLK.

또한, 망동기 카운터(25)는 상기 시스템 클럭신호(S_CLK)를 카운트하여 카운트값에 상응되는 시스템동기 펄스(SS_PLS)를 출력하고, 분주기(26)는 그 망동기 카운터(25)를 통해 공급되는 시스템 클럭신호를 X배 분주하여 시스템동기 클럭신호(SS_CLK)로 출력한다.In addition, the synchronizer counter 25 counts the system clock signal S_CLK to output a system synchronizer pulse SS_PLS corresponding to the count value, and the divider 26 is supplied through the synchronizer counter 25. The system clock signal is divided by X times and output as the system synchronous clock signal SS_CLK.

한편, 디퍼런스 카운터(27)는 상기 시스템동기 펄스(SS_PLS)와 외부로부터 입력되는 망동기 펄스(NET_PLS)를 비교하여 부호비트(SIG_Bit)를 출력함과 아울러, 그들간의 차값(DIFF_V)을 출력한다.On the other hand, the difference counter 27 compares the system synchronization pulse SS_PLS with the external network synchronization pulse NET_PLS, outputs a sign bit SIG_Bit, and outputs a difference value DIFF_V therebetween. .

그리고, 디바이더 콘트롤 로직부(28)는 상기 전압제어 발진기(23)의 출력 클럭신호를 분주하여 상기 피엘엘 신서사이저(21)에 공급함에 있어서, 상기 차값(DIFF_V)이 큰 경우에는 큰 분주비로, 작은 경우에는 작은 분주비로 분주하게된다.When the divider control logic unit 28 divides the output clock signal of the voltage controlled oscillator 23 and supplies it to the PEL synthesizer 21, when the difference value DIFF_V is large, the division ratio is small. In the case of a small dispensing ratio.

이에 따라, 상기 피엘엘 신서사이저(21)에서 전압제어 발진기(23)측으로 공급되는 발진 제어전압이 상기 차값(DIFF_V)에 따라 신속하게 변화되거나 서서히 변화된다. 즉, 상기 디바이더 콘트롤 로직부(28)는 상기 차값(DIFF_V)이 큰 경우에는 분주비가 크게 설정되어 상기 시스템동기 펄스(SS_PLS)가 망동기 펄스(NET_PLS)에 빠르게 접근하게 되고, 작은 경우에는 분주비가 작게 설정되어 상기 시스템동기 펄스(SS_PLS)가 망동기 펄스(NET_PLS)에 느리게 접근하므로 떨림(vibration) 현상이 방지되고 이에 의해 도 3에서와 같이 안정된 동기화를 구현할 수 있게 된다.Accordingly, the oscillation control voltage supplied from the PEL synthesizer 21 to the voltage controlled oscillator 23 side changes rapidly or gradually changes according to the difference value DIFF_V. That is, the divider control logic unit 28 sets the frequency division ratio to be large when the difference value DIFF_V is large so that the system synchronization pulse SS_PLS quickly approaches the network synchronizer pulse NET_PLS. Since the system synchronization pulse SS_PLS is set to a small size, the system synchronization pulse SS_PLS slowly approaches the network synchronization pulse NET_PLS, thereby preventing a vibration from occurring and thereby achieving stable synchronization as shown in FIG. 3.

이상에서 상세히 설명한 바와 같이 본 발명은 디퍼런스 카운터에서 망 동기펄스와 궤환되는 펄스의 차에 상응하는 값을 출력하도록 하고, 이를 이용하여 망동기 펄스와 시스템 동기펄스의 위상을 일치시킴으로써, 빠르고 안정된 동기화가 가능하게 되는 효과가 있다.As described in detail above, the present invention outputs a value corresponding to the difference between the network synchronization pulse and the feedback pulse from the difference counter, and uses the same to match the phase of the network synchronization pulse with the system synchronization pulse, thereby providing fast and stable synchronization. There is an effect that becomes possible.

Claims (3)

피엘엘 신서사이저, 전압제어 발진기 및 분주기를 통해 시스템 클럭신호를 출력하는 망 동기 시스템에 있어서, 상기 시스템 클럭신호와 망동기 펄스의 차값 및 부호비트를 출력하는 디퍼런스 카운터와; 상기 전압제어 발진기의 출력 클럭신호를 상기 차값에 상응되는 분주비로 분주하여 상기 피엘엘 신서사이저에 공급하는 디바이더 콘트롤 로직부를 포함하여 구성한 것을 특징으로 하는 망 동기 시스템의 피엘엘 회로.CLAIMS 1. A network synchronization system for outputting a system clock signal through a PEL synthesizer, a voltage controlled oscillator, and a divider, comprising: a difference counter for outputting a difference value and a sign bit between the system clock signal and a network synchronizer pulse; And a divider control logic unit configured to divide the output clock signal of the voltage controlled oscillator into a division ratio corresponding to the difference value and supply the divided clock signal to the PLS synthesizer. 제1항에 있어서, 디퍼런스 카운터는 상기 분주기의 출력단에 접속된 망동기 카운터를 통해 입력되는 시스템동기 펄스와 외부로부터 입력되는 망동기 펄스를 비교하여 그에 따른 부호비트 및 차값을 출력하도록 구성된 것을 특징으로 하는 망 동기 시스템의 피엘엘 회로.The differential counter of claim 1, wherein the difference counter is configured to compare a system synchronizer pulse input through a network synchronizer counter connected to an output terminal of the divider and a network synchronizer pulse input from the outside and output a corresponding code bit and a difference value. A PEL circuit of the network synchronization system characterized by the above-mentioned. 제1항에 있어서, 디바이더 콘트롤 로직부는 빠르고 안정된 동기화가 가능하도록, 상기 디퍼런스 카운터로부터 차값 및 부호비트를 입력받아 그 차값에 상응되는 분주비로 상기 전압제어 발진기의 출력 클럭신호를 분주하여 상기 피엘엘 신서사이저에 공급하는 것을 특징으로 하는 망 동기 시스템의 피엘엘 회로.The PEL of claim 1, wherein the divider control logic unit receives the difference value and the sign bit from the difference counter and divides the output clock signal of the voltage controlled oscillator at a division ratio corresponding to the difference value so as to enable fast and stable synchronization. A PEL circuit of a network synchronization system, characterized by supplying to a synthesizer.
KR1020010058302A 2001-09-20 2001-09-20 Pll circuit for network synchronization system KR20030028603A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2409383A (en) * 2003-12-17 2005-06-22 Wolfson Ltd Clock Synchroniser

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2409383A (en) * 2003-12-17 2005-06-22 Wolfson Ltd Clock Synchroniser
GB2409383B (en) * 2003-12-17 2006-06-21 Wolfson Ltd Clock synchroniser
US7583774B2 (en) 2003-12-17 2009-09-01 Wolfson Microelectronics Plc Clock synchroniser
US7949083B2 (en) 2003-12-17 2011-05-24 Wolfson Microelectronics Plc Clock synchroniser
US8537957B2 (en) 2003-12-17 2013-09-17 Wolfson Microelectronics Plc Clock synchroniser

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