KR20030004327A - Improved apparatus and method for multi-threaded signal processing - Google Patents

Abstract

The system and circuit design methods and apparatus implement a general functional definition 10 using multi-threaded representations. The multi-threaded representation is then profiled for parallel processing using one or more corresponding kernel logic elements 18. Preferably, the communication 26, theteworking, or media processing functionality or algorithm 12 is functionally analyzed and symbolically represented to authenticate one or more thread segments. The thread segments are each profiled 14 using temporal and / or non-temporal functions according to one or more specific fixed, parameterizable, programmable or reconfigurable logical kernels.

Description

Improved apparatus and method for multi-threaded signal processing

Traditional approaches to achieving high-performance in computing devices for digital information processing are focused on the design of architectures that provide good levels of parallelism. This is typically accomplished through the design of processors and instruction-set architectures that can develop hardware parallelism and software concurrency.

High performance is typically defined as the ability to perform a significant number of operations per second. This high performance value is strongly dependent on the type of operation and typically depends on the type of application.

The traditional design of a high performance information processing device relies on the principles of computer architecture to define the multiple key attributes of the processing device as listed below.

Instruction-set architecture; Refers to the actual programmer-visible sets of instructions, which serve as the boundary between hardware and software.

·group; Refers to a high level view of computer design such as memory system, bus structure and internal CPU design.

·hardware; Refers to specific detailed logic designs, circuit implementations, and packaging.

There are three ways to achieve high performance, which is a commonly required attribute in a particular purpose processor (ie, a processor made for a specific purpose).

(1) Instruction-level parallelism: This way of developing parallelism in hardware is to handle parallel threads through the use of very long or vectorized instructions with fields that can be analyzed as concurrent processing threads. The mechanism for developing this parallelism is realized through a scheduler, which schedules operation with one of a number of datapath processing units. This scheme has drawbacks that make the scheduler difficult to manufacture and to verify sufficient parallelism to achieve the desired throughput.

(2) superscalar technique: This approach developed a fine-grain highly-pipelined single-threaded processor architecture to achieve high performance. This scheme can achieve very high performance, but only for small classes of operation. The performance of superscalar designs is significantly reduced for operations that do not fit well into a particular datapath architecture. Therefore, the superstar technique is not suitable for a wide range of applications with high signal processing content.

(3) memory hierarchy techniques: conceal the latency of memory accesses to slow memories, fast memories, or caches, between processor units and slow memory to effectively hide the latency of slow memories. It has been widely used in fields such as microprocessor design to use caches wisely to increase the performance of the entire device.

Typically, multiprocessor devices employ multi-threaded processing to improve computing power. Multi-threaded processing is well known as a way to improve the usefulness of computational resources, ie overall throughput. However, conventional multi-threaded processing is performed using complex distributed or networked computer nodes. However, they are not easily reconfigured at lower logic or circuit levels and are not satisfactory in solving advanced functional problems such as multimode intercommunication algorithms or networking protocols. Thus, there is a need for improvements in multi-threaded processing.

TECHNICAL FIELD The present invention relates to the processing of electronic data and signals, and more particularly, to a high performance multi-threaded information processing technique.

1 is a diagram of a methodology and tool architecture for execution in software and / or hardware in accordance with a preferred embodiment of the present invention.

2A and 2B are functional block diagrams for practicing one embodiment of the present invention.

3 is a functional diagram showing another embodiment of the present invention.

4 is a functional diagram showing a reconfigurable embodiment of the present invention.

5 is a functional diagram showing the kernel embodiment of the present invention.

6 is a functional diagram showing an interface embodiment of the present invention.

7 is an apparatus methodology flow diagram illustrating the functional operations for implementing one or more embodiments of the present invention.

8 illustrates a software code stub for implementing one or more embodiments of the present invention.

9A and 9B are functional diagrams illustrating one or more applications of the present invention.

The present invention relates to a design and execution method, a processor architecture, and an apparatus for processing multi-threaded digital information (signal or data representation) to improve functional performance. Preferably, general device design or functional definitions, algorithms, electronic signals, or data files are initially provided to include one or more multi-threaded representations. Such early prototype designs or functions are profiled or otherwise specified for parallelism or effective similarity processing. In particular, one or more corresponding fixed, parameterized, programmable or configurable logic units or equivalent other functional signal processing kernels, using functionally or otherwise using temporal and / or non-temporal functional considerations, or Run on element

Preferably, relatively complex device functionality, such as applications in digital communications and / or networking and / or media processing design, is analyzed by pre-measured system design rules, mathematical operations, sequences of operations or parameters. Then, it is represented symbolically or graphically to authenticate one or more algorithms, specific sequences of operations, patterns of memory access, or segments (ie, single or multiple threads). In this case, the ones listed above are specified for profiled, configured, or optimized operation or execution using one or more specifically fixed, parameterizable, programmable or configurable logical units or kernel elements.

Such elements can be used to derive datapaths whose structure and configurability are determined through profiling, sequencers / finite-state-machines where structure and configurability are determined through profiling, and local memory characteristics. locality is provided by local memory, whose structure is determined through profiling memory access. Optionally, one or more kernel elements are executed entirely by software, programmable logic, or a combination thereof. In addition, “profiling” as mentioned above refers to the automated and / or manual processing of one or more systems or functional modules to define one or more configurable structures associated with each module.

The present invention makes it possible to process single or multiple threads, or evenly divided processing of digital data, signals, or functional representations using automated design and execution to improve processing performance. First, a device design or functional definition, algorithm, electronic signal, or data file is a single or multiple that is consistent when one or more device designs or functional modules are profiled and configured or specified for parallel or concurrent processing. Provide a thread representation.

For example, multithreaded prototypes can be executed or used in fixed, parameterizable, programmable or configurable logic units or other signal processing kernels or elements. Therefore, complex device functionality, such as digital communication, networking or multimedia applications, is analyzed according to device design rules, mathematical operations, sequences of operations, or parameters. It is then symbolized or graphically represented to authenticate certain single or multiple algorithms, specific sequences of operations, patterns of memory access, or segments. Each thread is then profiled or specified to optimize its operation or execution using fixed, parameterizable, programmable or configurable logic units or other signal processing kernels or elements.

Optionally, as the datapath structure is determined by profiling, single or multithreaded elements, sequencers and / or equivalent finite-state-machines having structure and configurability determined through profiling, and local It consists of local memory with a structure determined by profiling memory accessibility and locality to derive memory characteristics.

As used herein, profiling terms refer to one or more configurable structures associated with each module by selecting or assigning one or more functional elements or design objects, such as interconnects, signals, logic, circuits, and the like. In order to define or categorize them, it is understood to mean classification, interpretation, computer automated processing and / or manual processing of one or more systems or functional modules. Preferably, profiling is accomplished according to one or more pre- and / or dynamically defined standards or functional rule combinations.

In general, in computer automation and / or manual development techniques, one or multiple thread designs are handled by initially providing a first level of functional definition that represents a prototype system. At this time, different levels of symbolic functional definitions representing equivalent functionality are generated or effectively profiled from it. In such a hierarchical design scheme, the generated symbolic representation preferably authenticates certain threads associated with the system design at one or more functional levels.

Each thread is profiled to be processed by corresponding kernel elements, and one or more common sets of operations are authenticated for a given thread (ie, one-to-one, multiple-to-one, or one-to-multithreaded-to-kernel relationship). do. Each thread is designed to authenticate sequence or scheduling information for each set of operators that are useful for executing functional operations, sequences of control operations, and / or memory access dynamics or related memory locations and functional modules or systems.

Therefore, a multi-threaded processing architecture using the development methodology of the present invention has a different kernel of the same prototype design that handles a set of kernel elements that handle certain functions represented by corresponding threads, and other functions represented by other corresponding threads. Contains a set of elements. In this partitioned or distributed process, each thread is profiled separately or hierarchically for proper multi-level or functional group processing. For example, the first level or group kernel element and the second level or group kernel element are associated with a first thread and a second thread, respectively, corresponding thereto in a given function or system design.

In representative system designs for wireless code division multiple access (CDMA) communication applications, it is believed that various kernels will be provided to function in different functional groups. For example, front-end processing (ie data switch selector, sample interpolation, etc.); Chip-ratio processing (ie, sample epoch selection, matched filter, general spreader, general dechannelizer, code generation unit, aggregate and dump, general finder control, etc.); Symbol sequence processing (ie, transport format decoder, dynamic spreading element computer, fast Hadamard transform, etc.); Channel element processing (ie, alignment / deskewing, combiner, soft decision computer, interpass interference equalizer, lysis antenna diversity combiner, etc.); Interleaving (ie, deinterleaver controller); And channel decoding (ie, turbo decoder, convolutional decoder, etc.).

In general, the present invention performs reparameterization, reprogramming or reconstruction of kernel elements from the associated corresponding threads (ie, as determined by the profiling technique described herein) and / or of the operations. By varying the sequence (ie, as determined by mapping and / or scheduling), one or more functional or system designs can be effectively implemented through concurrent multithreading schemes in a single processor architecture.

Preferred embodiments implement functional or system design (ie, according to the so-called "DRL" processing described below) in one or more other reconfigurable logic or kernel elements.

1 is a general architecture or system block diagram showing in plan view the design methodology, functional modules, and software and / or hardware tool architecture of the present invention in one or more electronic design automation platforms. The electronic design automation platform can then support one or more single or networked computers, processors, engineering workstations, or computing facilities with appropriate operating systems, user interfaces, storage management, communication interfaces, and other computer support. Includes design and engineering tools.

Preferably, the design methodology of the present invention functions to provide a tool architecture and processor implementation and architecture, or a data file representation thereof, to enable a system architecture such as network execution.

As shown, one or more functional definition files 10, such as a high level description language (C or HDL) or design netlist, that define one or more functional modules or algorithms 12. Is provided manually or computed automatically. According to one embodiment of the present invention, the functionally selectable profiling and mapping design 14 primitives to provide or generate a multi-threaded base, one or more control communication signals 26 and the kernel 18. (primitives) 16 and functional definitions 10 are applied or applied. Profiling and mapping 14 also provides scheduling data to the schedule action table 20. Control and communication signals are processed in accordance with one or more predefined or selected functional rules or signal flags, namely communication semaphores 24. Various kernels 18 are processed and interconnected for execution 22, for example in a reconfigurable form for multithreaded signal processing.

2A and 2B are functional block diagrams illustrating kernels 18 and 28 and their physical execution including scheduling and allocation functions 30. Preferably, one or more kernels 18 are associated with or correspond to threads that are profiled or mapped, and are reconfigurably executed using sequencer 32, datapath 34, and memory 36.

Thus, in accordance with the circuit design methodology and / or computing device and the present device, a general functional definition may be implemented using single or multi-threaded re-expression, which expression may comprise one or more corresponding kernel computing elements (ie, 1-to-multiple, 1-to-1, multi-to-1, multi-to-multiple kernel-to-thread relationships) to effectively profile parallelism. For example, communication, networking, or media processing functionality or algorithms may be analyzed or encoded to authenticate one or more thread segments. The thread segments are then profiled or specified for optimized operation or execution using one or more specially specified, fixed, parameterized, programmable or reconfigurable logic kernels, respectively.

3 is a function diagram showing another reconfigurable multi-process batch.

As shown, the kernel 8 executes a "small" granularity thread function and the kernel 6 represents a "large" granular thread function. In this reconfigurable deployment, the various levels of functional granularity, which are design functions and their corresponding kernel attributes, are executed or dynamically reconfigured according to design requirements or profile mapping priorities.

4 is a functional diagram showing one or more representative or useful configurable logic and functions. The above logic and functions are employed in accordance with the present invention to execute a single or multiple threads into designated kernels. The kernels may then be reconfigurable logic or programmable functional units (PFUs) 40, multiplexers, having programmable logic elements and switch matrices (ie, for encoding bit-level operations). Reconfigurable datapath 42, address generators, memory, memory address control with reconfigurable signal flow through registers, adders, buffers and the like (i.e. dedicated datapath filters) Reconfigurable arithmetic 44 with back (i.e., arithmetic convolution kernel), and reconfigurable with data memory, datapath, program memory, instruction decoder and controller, etc. (i.e., real-time operating system processing arrangement) Control 46 corresponds.

5 is a functional diagram showing functional elements for executing a kernel 18 including a data sequencer 32, a data memory 36, and a parameterizable and configurable numerical logic unit (ALU) 34. FIG. to be.

6 is a functional diagram illustrating an arbitrary interface between a dynamically reconfigurable logic (DRL) process 64 and its associated configuration database to handle external functions for the main processor hardware model 50.

Preferably, the DRL process is different, reconfigurable and implemented using current innovation. As shown, the hardware interface 54 is associated with the library 62 and the specific function module 60 and includes a processor element 52 having a C-program model 56 and an input / output device driver 58. To an external DRL process 64.

In such embodiments, one or more single or multithreaded digital information (ie, single or data representations), such as general system design or functional definitions, algorithms, electronic signals or data files, includes one or more multithreaded representations. Initially provided. Such early prototype designs or functions are profiled or otherwise specified for parallel or effectively similar processing. In particular, in processor models 50 and 57 for functional collaboration or emulated real-time signal interaction with external DRL processes 64, one or more corresponding fixed, parameterizable, programmable or configurable It is used or executed functionally in a logical unit or other equivalent functional signal processing kernel or element.

7 is a flow chart showing the operating steps of another embodiment of the present invention. First, functions generated by the user or generated by the computer are defined for prototype or other system design (70). Then, one or more mathematical analysis or design performance optimization design is applied to the initial design definition (72). Next, one or more configuration algorithms are provided 74 for design definition, and the representation of such algorithms is preferably encoded 76 in a high level register transfer or behavioral functional format.

The algorithm is profiled and mapped 78, or otherwise optimized, using correspondingly defined kernels 80, preferably one or more specified design composition blocks, ie primitives 86. Functionally defined or manually and / or automatically categorized for execution of the derived operation or system design module, functions, signals, components or other elements. Profiled and mapped data is provided to communication semaphores 84, scheduling and finite state machine control and parameters 88. The communication semaphores 84, as well as the kernel definition 80 and FSM control parameterization and scheduling 88, are then applied to execute the single or multithreaded elements of the design as reconfigurable kernel elements 82 to the processor architecture. . 8 shows a simple design software code that illustrates the use of multi-threaded kernels 90.

According to one embodiment of the present invention, the profiling process or its reconfigurable algorithmic representation is temporal and thus includes determining the degree of change of a constant time or over time. Examples of temporal applications include receiver algorithms required in cellular wireless systems and changes in the signal processing plans associated with such algorithms (you can take advantage of this profiling methodology). In this embodiment, processing computation requirements in one path (i.e., acceptance direction) increase or decrease as processing proceeds, wherein the profiling scheme is intended to avoid hardware-software or other functional partitioning of the overall design execution. Function to decide

Further, in such cellular radio embodiments, multiple methods perform similar or equivalent signal processing, but are believed to result in different air-interface requirements or effective functionality. In particular, for hardware partitioning of a given system, various processing forms or functional elements will occur or operate at various rates. By requiring variable processing rates and varying modes of operation control to support multiple processing flows, several additional ratios can be seen in terms of useful operating performance or the capacities of the hardware architecture (ie, real-time and non-real-time profiling). Temporal and temporal profiling techniques will be applied to provide adequate functional flexibility. Other embodiments of the present invention are applicable to additional cellular wireless, including fixed wireless, unlicensed wireless LANs, cordless telephony, telemetry, and the like.

In order to determine the type and number of operations and to determine the required storage elements, a profiling technique is applied to a hardware-based algorithm that encompasses multimode operations, thereby facilitating the classification of commonly used resources. It allows operators to classify each temporally unique function.

Another profiling technique is applied to control multiple levels of hardware definition in accordance with the required frequency change. For example, a mode dependent change in the receive path of a wireless receiver may result in a transaction configuration (ie, transactions are multi-second transactions) and sub-second transactions encompassing data blocks (ie, "on the fly"). It is necessary to change at the beginning for a comprehensive reconstruction between the fly.

Appropriate levels of configurable execution are selected according to profiling results, such as handling high data rates based on cycle base. However, flexibility is required for control, and the programmable state machine provides adequate flexibility to meet the required performance requirements. Datapaths do not need to be selected over configuration time, but do not change often, and programmable interconnects are appropriate.

If datapath selection occurs in real time, the datapath-cell-based multiplexing scheme is applied. In addition, in order to control functions that require operation ordering, parameterized kernels for processing operations are applied. Additionally, where high performance requirements and low flexibility requirements are required, a designated datapath can be applied to the appropriate silicon implementation. In the case of a multi-standard radio receiver design that gives adequate flexibility to the point of performance, one or more profiling techniques may be applied.

9A illustrates a general embodiment of the present invention. As shown, an application programming interface may be provided to provide one or more configuration parameters for implementing single or multi-threaded reconfigurable systems in accordance with the techniques of the present invention using wired and / or wireless network downloads or other transmit / receive. An API 94 is depicted for passing capacities, parameters, and values to configuration table 92 in accordance with one or more industry or property standards.

Define one or more interconnected block modules 96 representing a microprocessor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), DRL or other functional block modules. Or accept configuration parameters via API 94 to execute. According to another embodiment of the present invention, one or more configurable parameters 100 are defined or executed to correspond to a thread fashion for one or more specific kernel elements. Therefore, in this configurable parameter case, the design and implementation method or system functions to process multi-threaded signals or data to improve functional performance.

Generally, system design or functional definitions, algorithms, electronic signals or data files are provided to include such multi-threaded representations, and the initial prototype function is profiled for parallel processing by one or more threads. . For example, it executes certain parameterized kernel elements that are temporarily defined.

In particular, as shown in FIG. 9B, in a digital wireless communication application, the mobile radio handset 102 transmits and receives signals wirelessly with the base station 104, and other handsets 102 or other via the digital network 105. May be connected to the base station 104. In such network applications, specific design rules, operations, or parameters, as well as representations that symbolize or diagram it, correspond to or multiply multiple threads for profiling and execution in programmable kernels or software modules.

Optionally, kernel elements are configured for operation at base station 104 and / or handset unit 102. In particular, kernels are configured according to temporal or non-temporal design constraints for profiled datapaths, sequencer / finite-state-machines, memory, or other logical structures.

The present invention has been described through the above embodiments, but is not limited to the above examples.

In particular, the Applicant believes that the invention described herein may be equally implemented in hardware, software, and / or other useful functional components or building blocks.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (15)

As an automated method for handling multi-threaded system functionality in a computer-aided design system, Providing a first functional definition representing a system design; Generating a second function definition from the first function definition that symbolically represents the first function definition, wherein the symbolic representation authenticates one or more threads associated with the system design; And Profiling each thread for processing by a specified kernel element or set thereof. The method of claim 1, further comprising: authenticating a common sequence of operations in a given thread; And associating a common sequence of operations with a set of operators. 3. The method of claim 2 further comprising associating the set of operators with a sequence of arithmetic operations. 3. The method of claim 2 further comprising associating the set of operators with a sequence of control operations. 3. The method of claim 2 further comprising associating the set of operators with a sequence of memory access operations or locations. The method of claim 1, wherein one or more threads are profiled according to a temporal function. A device for multi-threaded processing, A first kernel element and a second kernel element, wherein the first kernel element handles a first function represented by a first thread, and the second kernel element represents a second function represented by a second thread. Wherein the first thread and the second thread are profiled to be processed by the first kernel element and the second kernel element, respectively, and the first thread and the second thread are associated with a common function. Device. 8. The apparatus of claim 7, wherein the common sequence of operations is capable of being authenticated by a given thread and the common sequence of operations is associated with a set of operators. 9. The apparatus of claim 8, wherein the set of operators is associated with a sequence of arithmetic, control, or memory access operations. 8. The apparatus of claim 7, wherein the first thread or the second thread is profiled according to a time constraint. 8. The apparatus of claim 7, wherein the first kernel element and the second kernel element are executed as one or more executable software modules. 8. The apparatus of claim 7, wherein the first kernel element and the second kernel element are implemented as one or more functional modules in a fixed base station or mobile handset of a radio communication system. A signal processing method in a communication device including a base station and one or more mobile units, each mobile unit communicating wirelessly with the base station via a radio signal, Generating at the base station a first signal indicative of device configuration, wherein the first signal symbolically represents one or more function definitions associated with one or more threads in the device configuration, The thread is profiled to be processed by a kernel element specified in the mobile unit. 14. The apparatus of claim 13, further comprising the step of accepting the first signal by the mobile unit, wherein one or more kernel elements in the portable unit are in accordance with the first signal in one or more of the device designs. And processing the thread. 14. The method according to claim 13, wherein one or more threads are profiled according to temporal functional constraints.