KR20030001637A - Method for forming transistor provided with metal-gate electrode - Google Patents
Method for forming transistor provided with metal-gate electrode Download PDFInfo
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- KR20030001637A KR20030001637A KR1020010036414A KR20010036414A KR20030001637A KR 20030001637 A KR20030001637 A KR 20030001637A KR 1020010036414 A KR1020010036414 A KR 1020010036414A KR 20010036414 A KR20010036414 A KR 20010036414A KR 20030001637 A KR20030001637 A KR 20030001637A
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- gate electrode
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 56
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 125000006850 spacer group Chemical group 0.000 claims abstract description 17
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 238000010405 reoxidation reaction Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- 229910052721 tungsten Inorganic materials 0.000 description 8
- 239000010937 tungsten Substances 0.000 description 8
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- -1 tungsten (W) Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 트랜지스터의 제조방법에 관한 것으로, 보다 상세하게는, 금속 게이트전극 중 금속질화막과 금속층의 측벽에 질화막 스페이서를 형성한 후, 스페이서 하부의 선택적 에피택셜 성장에 의해 형성된 실리콘막을 재산화처리하여 폴리실리콘막의 에지영역을 라운딩지게 하여, 상기 재산화처리 시, 금속층이 산화되어 블로우업(blow-up)현상이 발생하는 것을 방지하고, 폴리실리콘막 에지영역의 라운딩에 의해 재산화막의 에지영역이 두껍게 형성되어 게이트전극 패턴과 드레인 사이의 누설전류인 게이트 인듀스드 드레인 누설(Gate Induced Drain Leakage : 이하 "GIDL" 이라함)을 최소화하도록 하는 금속 게이트전극을 갖는 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a transistor, and more particularly, by forming a nitride film spacer on the sidewalls of the metal nitride film and the metal layer of the metal gate electrode, and re-processing the silicon film formed by selective epitaxial growth under the spacer By rounding the edge region of the polysilicon film, the metal layer is oxidized during the reoxidation process to prevent blow-up, and the edge region of the reoxidized film is rounded by the rounding of the edge region of the polysilicon film. The present invention relates to a method of manufacturing a transistor having a metal gate electrode formed to be thick to minimize gate induced drain leakage (hereinafter referred to as "GIDL"), which is a leakage current between the gate electrode pattern and the drain.
최근 게이트전극 물질로서 폴리실리콘 상부에 비저항이 낮으면서도 고온에서 텅스텐(W), 티타늄(Ti), 탄탈륨(Ta) 등의 고융점 금속을 추가한 금속 게이트전극을 형성하고 있으며, 그 중에서도 텅스텐을 사용한 금속 게이트는 소자의 고집적화에 따른 신호처리 속도 개선의 측면에서 기존 폴리사이드 게이트전극을 대체하고 있는 실정에 있다.Recently, as gate electrode materials, metal gate electrodes have been formed on top of polysilicon with high melting point metals such as tungsten (W), titanium (Ti), and tantalum (Ta) at a high temperature, with tungsten being used. Metal gates are replacing existing polyside gate electrodes in terms of improving signal processing speed due to high integration of devices.
일반적으로 화학기상증착공정에 의하여 증착된 게이트전극 내 텅스텐층은 주상정(columnAs crystalline) 구조이며 후속 재산화처리 공정 시, 이러한 주상정 구조 내 결정립계는 반응성 원자의 확산 경로로 작용된다.In general, the tungsten layer in the gate electrode deposited by the chemical vapor deposition process has a columnar crystalline structure, and in the subsequent reoxidation process, the grain boundary in the columnar structure serves as a diffusion path of reactive atoms.
도 1은 종래 기술에 의한 금속 게이트전극을 갖는 트랜지스터의 문제점을 설명하기 위해 나타낸 단면도이다.1 is a cross-sectional view illustrating a problem of a transistor having a metal gate electrode according to the prior art.
도 1에 도시된 바와 같이, 반도체기판(10) 상에 게이트산화막(20), 폴리실리콘막(30), 금속질화막(40), 텅스텐층(50) 및 질화마스크(60)를 순차적으로 적층한 후, 식각 공정에 의해 금속 게이트전극이 패터닝되어 금속 게이트전극 패턴(70)이 형성된다.As shown in FIG. 1, the gate oxide film 20, the polysilicon film 30, the metal nitride film 40, the tungsten layer 50, and the nitride mask 60 are sequentially stacked on the semiconductor substrate 10. Thereafter, the metal gate electrode is patterned by an etching process to form the metal gate electrode pattern 70.
그러나, 상기 금속 게이트전극 패터닝 시, 하부 게이트산화막의 측벽의 손실이 유발되어, 이 손실을 복원하기 위해 재산화(re-oxidation)공정 또는 라이트 산화(Light oxidation)공정이 진행된다.However, when the metal gate electrode is patterned, loss of sidewalls of the lower gate oxide film is caused, and a re-oxidation process or a light oxidation process is performed to restore the loss.
그런데, 상기 재산화 공정 또는 라이트 산화 공정 진행 시, 금속 게이트전극 패턴 중 텅스텐층과 금속질화막의 측벽 원자와 산화 공정의 반응성 원자간의 급격한 화학반응에 일어나 "A"와 같이 텅스텐층의 측벽이 바깥쪽으로 변형되는 블로우업(blow-up)현상이 발생되거나, 게이트전극이 리프팅(lifting)되는 문제점이 있었다.However, during the reoxidation process or the light oxidation process, a sudden chemical reaction occurs between the tungsten layer and the sidewall atoms of the metal nitride film and the reactive atoms of the oxidation process in the metal gate electrode pattern. There is a problem in that the blow-up phenomenon is deformed or the gate electrode is lifted.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 금속 게이트전극 중 금속질화막과 금속층의 측벽에 질화막 스페이서를 형성한 후, 스페이서 하부의 선택적 에피택셜 성장에 의해 형성된 실리콘막을 재산화처리하여 폴리실리콘막의 에지영역을 라운딩지게 하여, 상기 재산화처리 시, 금속층이 산화되어 블로우업 현상이 발생하는 것을 방지하고, 폴리실리콘막 에지영역의라운딩에 의해 재산화막의 에지영역이 두껍게 형성되어 게이트전극 패턴과 드레인 사이의 누설전류인 GIDL을 최소화하도록 하는 것이 목적이다.The present invention has been made to solve the above problems, and an object of the present invention is to form a nitride film spacer on the sidewall of the metal nitride film and the metal layer of the metal gate electrode, and then to form a silicon film formed by selective epitaxial growth under the spacer. By reoxidization, the edge region of the polysilicon film is rounded, and during the reoxidation treatment, the metal layer is oxidized to prevent blow up phenomenon, and the edge region of the reoxidized film is thickened by the rounding of the polysilicon film edge area. The purpose is to minimize the GIDL which is formed to be a leakage current between the gate electrode pattern and the drain.
도 1은 종래 기술에 의한 금속 게이트전극을 갖는 트랜지스터의 문제점을 설명하기 위해 나타낸 단면도이다.1 is a cross-sectional view illustrating a problem of a transistor having a metal gate electrode according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 금속 게이트전극을 갖는 트랜지스터 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2D are cross-sectional views sequentially illustrating a method of manufacturing a transistor having a metal gate electrode according to the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 반도체 기판 110 : 필드산화막100 semiconductor substrate 110 field oxide film
120 : 게이트산화막 130 : 폴리실리콘막120: gate oxide film 130: polysilicon film
140 : 금속질화막 150 : 금속층140 metal nitride film 150 metal layer
160 : 질화마스크 170 : 실리콘막160 nitride mask 170 silicon film
175 : 이온주입 180 : 스페이서175 ion implantation 180 spacer
190 : 재산화막 200 : 금속 게이트전극 패턴190: reoxidation film 200: metal gate electrode pattern
상기 목적을 달성하기 위하여, 본 발명은 반도체기판 상에 게이트산화막, 폴리실리콘막, 금속질화막, 금속층 및 질화마스크를 순차적으로 적층한 후, 식각 공정을 진행하여 금속 게이트전극을 패터닝하는 단계와; 상기 폴리실리콘막이 매립되지 않도록 선택적 에피택셜 성장 공정을 진행하여 실리콘막을 성장시킨 후, 상기 실리콘막에 P 또는 As 이온을 주입하여 도핑하는 단계와; 상기 실리콘막이 형성된 결과물 상에 질화막을 적층한 후, 상기 질화막과 실리콘막을 블랭켓 식각공정을 진행하여 금속 게이트전극 측벽에 스페이서를 형성하는 단계와; 상기 스페이서 하부의 실리콘막에 재산화공정 또는 라이트산화공정을 진행하여 실리콘막을 산화시키는 단계를 포함하여 이루어진 것을 특징으로 하는 금속 게이트전극을 갖는 트랜지스터의 제조방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of sequentially depositing a gate oxide film, a polysilicon film, a metal nitride film, a metal layer and a nitride mask on a semiconductor substrate, and performing an etching process to pattern the metal gate electrode; Performing a selective epitaxial growth process so that the polysilicon film is not embedded and growing a silicon film, and then doping by implanting P or As ions into the silicon film; Forming a spacer on the metal gate electrode sidewall by performing a blanket etching process on the nitride film and the silicon film by laminating a nitride film on the resultant product on which the silicon film is formed; A method of manufacturing a transistor having a metal gate electrode, comprising: oxidizing a silicon film by performing a reoxidation process or a light oxidation process on a silicon film under the spacer.
본 발명은 게이트전극 물질로서 폴리실리콘 상부에 비저항이 낮으면서도 고온에서 고융점 금속인 텅스텐을 사용하여 금속 게이트전극을 형성한 후, 금속 게이트전극 측벽에 질화물로 이루어진 스페이서를 형성함으로써 텅스텐 게이트전극 측벽쪽에 WOx 화합물이 생성되는 것을 방지한다.The present invention forms a metal gate electrode using tungsten, which is a high melting point metal at a high temperature, but has a low specific resistance on polysilicon as a gate electrode material, and then forms a spacer of nitride on the sidewall of the tungsten gate electrode. Prevents the production of WOx compounds.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 금속 게이트전극을 갖는 트랜지스터 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2D are cross-sectional views sequentially illustrating a method of manufacturing a transistor having a metal gate electrode according to the present invention.
도 2a에 도시된 바와 같이, 필드산화막(110)이 형성된 반도체기판(100) 상에 게이트산화막(120), 폴리실리콘막(130), 금속질화막(140), 금속층(150) 및 질화마스크(160)를 순차적으로 적층한 후, 이방성 식각 공정을 진행하여 금속 게이트전극을 패터닝하여 금속 게이트전극 패턴(200)을 형성한다.As shown in FIG. 2A, the gate oxide film 120, the polysilicon film 130, the metal nitride film 140, the metal layer 150, and the nitride mask 160 are formed on the semiconductor substrate 100 on which the field oxide film 110 is formed. ) Is sequentially stacked, and then the metal gate electrode is patterned by anisotropic etching to form the metal gate electrode pattern 200.
이때, 상기 금속층(150)은 비저항이 낮으면서도 고온에서 고융점 금속인 텅스텐을 사용한다.In this case, the metal layer 150 uses tungsten, which is a high melting point metal at a high temperature while having a low specific resistance.
그리고, 도 2b에 도시된 바와 같이, 상기 반도체기판(100) 상에 폴리실리콘막(130)이 매립되지 않도록 선택적 에피택셜 성장(selective epitaxial growth) 공정을 진행하여 실리콘막(170)을 성장시킨 후, 상기 실리콘막(170)에 P 또는 As 이온(175)을 주입하여 도핑하며, 도핑 농도는 1.0E18∼2.0E20/㎤ 정도로 한다.As shown in FIG. 2B, the silicon film 170 is grown by performing a selective epitaxial growth process so that the polysilicon film 130 is not embedded on the semiconductor substrate 100. In addition, P or As ions 175 are implanted into the silicon film 170 and doped, and the doping concentration is about 1.0E18 to 2.0E20 / cm 3.
그 후, 도 2c에 도시된 바와 같이, 상기 실리콘막(170)이 형성된 결과물 상에 30∼200Å 정도의 두께로 질화막(미도시함)을 적층한 후, 상기 질화막(미도시함)과 실리콘막(미도시함)에 블랭켓 식각공정을 진행하여 금속 게이트전극 패턴(200) 측벽에 상부는 질화막 하부는 실리콘막으로 이루어진 스페이서(180)를 형성한다.Thereafter, as illustrated in FIG. 2C, a nitride film (not shown) is laminated on the resultant on which the silicon film 170 is formed to a thickness of about 30 to 200 Å, and then the nitride film (not shown) and the silicon film are not shown. A blanket etching process is performed on the spacer gate 180 formed on the sidewall of the metal gate electrode pattern 200 to form a spacer 180 formed of a silicon film on an upper portion of the nitride film.
이어서, 도 2d에 도시된 바와 같이, 상기 스페이서(180) 하부의 실리콘막에 재산화공정 또는 라이트산화공정을 실시하여 실리콘막을 산화시켜폴리실리콘막(130)의 에지영역을 라운딩지게 하여 재산화막(190)의 에지영역의 두께를 두껍게 형성한다.Subsequently, as shown in FIG. 2D, a reoxidation process or a light oxidation process is performed on the silicon film under the spacer 180 to oxidize the silicon film to round the edge region of the polysilicon film 130. The thickness of the edge region of 190 is formed thick.
이때, 상기 재산화공정 또는 라이트산화공정 시, 70∼250Å 정도의 실리콘막을 재산화시킨다.At this time, during the reoxidation process or the light oxidation process, the silicon film of about 70 to 250 kV is reoxidized.
따라서, 상기한 바와 같이, 본 발명에 따른 금속 게이트전극을 갖는 트랜지스터의 제조방법을 이용하게 되면, 금속 게이트전극 중 금속질화막과 금속층의 측벽에 질화막 스페이서를 형성한 후, 스페이서 하부의 선택적 에피택셜 성장에 의해 형성된 실리콘막을 재산화처리하여 폴리실리콘막의 에지영역을 라운딩지게 함으로써, 상기 재산화처리 시, 금속층이 산화되어 블로우업 현상이 발생하는 것을 방지하고, 폴리실리콘막의 에지영역이 라운딩에 의해 재산화막의 에지영역이 두껍게 형성되어 게이트전극 패턴과 드레인 사이의 누설전류인 GIDL을 최소화할 수 있다.Therefore, as described above, when using the method of manufacturing a transistor having a metal gate electrode according to the present invention, after forming a nitride film spacer on the sidewall of the metal nitride film and the metal layer of the metal gate electrode, selective epitaxial growth under the spacer By reoxidizing the silicon film formed by the metal film to round the edge region of the polysilicon film, the metal layer is oxidized during the reoxidation treatment to prevent blowup phenomenon, and the edge region of the polysilicon film is rounded by the reoxidation film. The thick edge region of the GIDL layer may minimize the GIDL, which is a leakage current between the gate electrode pattern and the drain.
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