KR20010093681A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20010093681A
KR20010093681A KR1020010014980A KR20010014980A KR20010093681A KR 20010093681 A KR20010093681 A KR 20010093681A KR 1020010014980 A KR1020010014980 A KR 1020010014980A KR 20010014980 A KR20010014980 A KR 20010014980A KR 20010093681 A KR20010093681 A KR 20010093681A
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semiconductor chip
wiring board
wiring
substrate
board
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KR1020010014980A
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Korean (ko)
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KR100830787B1 (en
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시바타가즈다카
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사토 게니치로
로무 가부시키가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

PURPOSE: To prevent warping of a semiconductor device having a structure where a thin semiconductor chip is bonded on a wiring board. CONSTITUTION: A semiconductor chip 1 is bonded on a wiring board 2 through the intermediary of solder balls 4, making its active surface confront the wiring board 2. An insulating board 3, formed of the same material with the wiring board 2, is bonded on the other non-active surface of the semiconductor chip 1. Therefore, the active surface and deactivating surface of the semiconductor chip 1 become equal to each other in thermal expansion and shrinkage.

Description

반도체장치{SEMICONDUCTOR DEVICE}Semiconductor device {SEMICONDUCTOR DEVICE}

본 발명은 반도체 칩을, 예를 들면 필름상의 배선기판상에 접합한 구성의 반도체장치에 관한 것이다.The present invention relates to a semiconductor device having a structure in which a semiconductor chip is bonded to, for example, a film-like wiring board.

반도체장치의 실장면적을 감소시키기 위해, 반도체 칩 자체와 거의 동등한 크기의 IC패키지인 칩사이즈 패키지에 대한 개발이 종래로부터 행해지고 있다.In order to reduce the mounting area of a semiconductor device, the development of the chip size package which is the IC package of the size substantially equivalent to the semiconductor chip itself is performed conventionally.

칩사이즈 패키지형의 반도체장치의 하나의 형태로, 표면실장형의 패키지가 있다.One type of semiconductor device of chip size package type is a surface mount type package.

이 표면실장형의 패키지에서는, 박형(薄型)의 반도체 칩이 필름상의 배선기판상에 접합되고, 이 필름상의 배선기판이 전자기기내의 실장기판상에 실장된다.In this surface mount package, a thin semiconductor chip is bonded onto a film-like wiring board, and the film-like wiring board is mounted on a mounting board in an electronic device.

반도체 칩과 접합되는 배선기판은, 반도체 칩의 원주둘레부에 배열된 복수의 패드를 재배선하여 배선기판의 하면에 2차원 배열된 땜납볼과 접속하는 내부배선을 갖고 있다.The wiring board to be bonded to the semiconductor chip has an internal wiring for rearranging a plurality of pads arranged in the peripheral portion of the semiconductor chip and connecting the solder balls arranged two-dimensionally on the lower surface of the wiring board.

그러나, 상술한 것과 같은 구성에서는, 극히 박형의 반도체 칩을, 이와는 열팽창계수가 다른 배선기판에 접합한 구조이기 때문에, 환경온도의 변화에 수반하여 패키지에 휘어짐이 생긴다는 문제가 있다.However, in the above-described configuration, since the extremely thin semiconductor chip is bonded to a wiring board having a different thermal expansion coefficient, there is a problem that the package is warped due to a change in environmental temperature.

본 발명의 목적은, 박형의 반도체 칩을 배선기판에 접합한 구조이면서 휘어짐이 생기는 것을 방지할 수 있는 반도체장치를 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a thin semiconductor chip is bonded to a wiring board while preventing warpage from occurring.

도 1은 본 발명의 제 1 실시형태에 관한 반도체장치의 구성을 설명하기 위한 도해적인 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view for explaining the configuration of a semiconductor device according to a first embodiment of the present invention.

도 2는 본 발명의 제 2 실시형태에 관한 반도체장치의 구성을 설명하기 위한 도해적인 단면도.2 is a schematic cross-sectional view for explaining the configuration of a semiconductor device according to a second embodiment of the present invention.

(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

1. 반도체 칩 2. 배선기판1. Semiconductor chip 2. Wiring board

3. 절연판 4, 5. 땜납볼3. Insulation plate 4, 5. Solder ball

본 발명의 반도체장치는, 반도체 칩과, 이 반도체 칩의 한쪽 표면측에 접합되며 상기 반도체 칩과 전기 접속된 배선기판과, 상기 반도체 칩의 다른 쪽 표면측에 접합되며 상기 배선기판과 동일한 재료로 된 휘어짐 방지기판을 포함한다.The semiconductor device of the present invention comprises a semiconductor chip, a wiring board bonded to one surface side of the semiconductor chip and electrically connected to the semiconductor chip, and the same material as the wiring board joined to the other surface side of the semiconductor chip. And a deflection prevention substrate.

본 발명에 의하면, 반도체 칩은, 동일재료로 된 배선기판 및 휘어짐 방지기판(예를 들면, 절연재료로 된)으로 끼고 지지되기 때문에, 예를 들면 반도체 칩이, 두께 100㎛ 정도의 박형의 것이라도, 환경온도의 변화에 의해 패키지에 휘어짐이 생길 우려가 없다.According to the present invention, since the semiconductor chip is supported by a wiring board made of the same material and a warp prevention board (for example, made of an insulating material), for example, the semiconductor chip is a thin film having a thickness of about 100 μm. In addition, there is no fear of warpage in the package due to changes in environmental temperature.

즉, 환경온도가 변화한 때에는, 반도체 칩의 양면에 있어서, 열팽창 또는 열수축이 균등하게 생기기 때문에, 패키지에 휘어짐이 생기는 것을 방지할 수가 있다.That is, when the environmental temperature is changed, since thermal expansion or thermal contraction occurs uniformly on both surfaces of the semiconductor chip, it is possible to prevent warpage from occurring in the package.

상기 배선기판의 반도체 칩과는 반대측의 표면에는, 표면실장용의 외부접속부재가 배치되어 있는 것이 바람직하다.It is preferable that the external connection member for surface mounting is arrange | positioned on the surface on the opposite side to the semiconductor chip of the said wiring board.

이 구성에 의하면, 배선기판의 반도체 칩과는 반대측의 표면에, 표면실장용의 외부접속부재(땜납볼이나 랜드 등)가 설치되어 있기 때문에, 이 반도체장치를 전자기기내의 실장기판에 표면 실장시킬 수가 있다.According to this configuration, since external connection members (solder balls, lands, etc.) for surface mounting are provided on the surface on the side opposite to the semiconductor chip of the wiring board, the semiconductor device can be surface mounted on the mounting board in the electronic device. There is a number.

상기 휘어짐 방지기판은 별도의 배선기판으로서, 이 휘어짐 방지기판의 상기 반도체 칩과는 반대측에, 그 휘어짐 방지기판에 전기 접속된 별도의 반도체 칩이 접합되어 있는 것이 바람직하다.It is preferable that the said bending prevention board is another wiring board, and the other semiconductor chip electrically connected to this bending prevention board is joined to the opposite side to this semiconductor chip of this bending prevention board.

이 구성에 의하면, 휘어짐 방지기판을 끼고 또한 별도의 반도체 칩을 적층할 수가 있기 때문에, 반도체 칩의 소위 3차원 실장이 가능하게 된다.According to this structure, since a semiconductor chip can be laminated together with a warpage prevention board | substrate, what is called a three-dimensional mounting of a semiconductor chip is attained.

이에 의해, 반도체 칩의 고밀도 실장이 가능하게 되므로, 결과로서, 반도체장치의 실질적인 집적도를 향상시킬 수가 있다.As a result, high-density mounting of the semiconductor chip is made possible, and as a result, substantial integration of the semiconductor device can be improved.

상기 배선기판과 휘어짐 방지기판 사이에, 이들을 전기 접속하기 위한 배선재가 개재 실장되어 있는 것이 바람직하다.It is preferable that a wiring material for electrically connecting them is mounted between the wiring board and the warpage prevention board.

이 구성에 의하면, 배선기판과 휘어짐 방지기판 사이에 전기 접속용의 접속부재가 배치되기 때문에, 휘어짐 방지기판(배선기판으로서의 기능을 갖는)에 접합된 별도의 반도체 칩을, 배선기판에 전기 접속할 수가 있다.According to this structure, since the connection member for electrical connection is arrange | positioned between a wiring board and a bending prevention board, the other semiconductor chip joined to the bending prevention board (having a function as a wiring board) can be electrically connected to a wiring board. have.

같은 모양으로 해서, 그 별도의 반도체 칩의 상면에 배선기판과 동일한 재료로 된 휘어짐 방지기판을 배치하여 3층 이상의 3차원 적층구조를 구성할 수도 있다.In the same manner, a three-dimensional laminated structure of three or more layers may be formed by arranging a warpage prevention substrate made of the same material as the wiring substrate on the upper surface of the other semiconductor chip.

이 경우에, 배선기판과 휘어짐 방지기판 사이 및 각층의 휘어짐 방지기판 사이에 배선재를 배치하는 것이 바람직하다.In this case, it is preferable to arrange the wiring member between the wiring board and the anti-warp board and between the anti-warp boards of each layer.

이에 의해, 각층의 반도체 칩간 및/또는 각층의 반도체 칩과 배선기판 사이의 전기 접속을 달성할 수가 있다.Thereby, electrical connection between the semiconductor chips of each layer and / or between the semiconductor chip of each layer and a wiring board can be achieved.

본 발명에 있어서의 상술한, 또는, 또 다른 목적, 특징 및 효과는, 첨부 도면을 참조하여 다음에 기술하는 실시형태의 설명에 의해 보다 명백해 질 것이다.The above-mentioned or another object, a characteristic, and an effect in this invention will become clear by description of embodiment described below with reference to an accompanying drawing.

(실시예)(Example)

도 1은, 본 발명의 1 실시형태에 관한 반도체장치의 구성을 설명하기 위한 도해적인 단면도이다.1 is a schematic cross-sectional view for explaining the configuration of a semiconductor device according to one embodiment of the present invention.

이 반도체장치는, 박형의 반도체 칩(1)과, 이 반도체 칩(1)을 끼고 지지하도록 설치된 배선기판(2) 및 휘어짐 방지기판으로서의 절연판(3)을 포함하고, 평면으로 보아 반도체 칩(1) 자체의 크기와 거의 동등한 정도의 크기로 구성된 칩사이즈 패키지형의 장치이다.This semiconductor device includes a thin semiconductor chip 1, a wiring board 2 provided so as to support the semiconductor chip 1, and an insulating plate 3 as an anti-bending substrate, and the semiconductor chip 1 in plan view. ) It is a chip-size package type device which is composed of almost the same size as its own size.

반도체 칩(1)은, 그 활성표면을 배선기판(2)에 대향시켜 배치되어 있다.The semiconductor chip 1 is disposed with its active surface facing the wiring board 2.

이 반도체 칩(1)의 활성면에는, 땜납볼(4)이, 그 원주둘레에 따라 복수개 배열되어 형성되어 있다.On the active surface of the semiconductor chip 1, a plurality of solder balls 4 are arranged along the circumference thereof.

이 땜납볼(4)을 통해 반도체 칩(1)이 배선기판(2)과 접합되어 있고, 이에 의해, 반도체 칩(1)의 내부회로가 배선기판(2)에 전기 접속되어 있다.The semiconductor chip 1 is joined to the wiring board 2 through the solder ball 4, whereby the internal circuit of the semiconductor chip 1 is electrically connected to the wiring board 2.

배선기판(2)은, 예를 들면 필름상의 기판으로서, 반도체 칩(1)의 땜납볼(4)에 접속되는 내부배선(도시생략)을 구비하고 있다.The wiring board 2 is, for example, a film substrate, and has internal wiring (not shown) connected to the solder balls 4 of the semiconductor chip 1.

이 내부배선은, 배선기판(2)의 반도체 칩(1)과는 반대측의 표면에 2차원적으로 배열되어 있는 복수개의 땜납볼(5)(표면실장용 외부접속부재)에 접속되어 있다.This internal wiring is connected to a plurality of solder balls 5 (surface mounting external connection member) arranged two-dimensionally on the surface opposite to the semiconductor chip 1 of the wiring board 2.

배선기판(2)의 내부배선은, 반도체 칩(1)의 원주둘레에 따라 배열된 땜납볼(4)을 각각 배선기판(2)의 하면에 2차원적으로 배열된 땜납볼(5)에 접속하도록 형성되어 있다.The internal wiring of the wiring board 2 connects the solder balls 4 arranged along the circumference of the semiconductor chip 1 to the solder balls 5 two-dimensionally arranged on the bottom surface of the wiring board 2, respectively. It is formed to.

한편, 반도체 칩(1)의 배선기판(2)과는 반대측의 표면에는, 절연판(3)이 예를 들면, 접착제에 의해 접합되어 있다.On the other hand, the insulating plate 3 is bonded to the surface of the semiconductor chip 1 on the opposite side to the wiring board 2 by, for example, an adhesive.

이 절연판(3)은, 배선기판(2)을 구성하는 절연재료와 동일한 절연재료를 사용하여 제작되어 있다.The insulating plate 3 is made of the same insulating material as the insulating material constituting the wiring board 2.

그리고, 이 절연판(3)의 두께는, 배선기판(2)의 두께와 거의 동등하게 되어 있다.The thickness of the insulating plate 3 is approximately equal to the thickness of the wiring board 2.

이에 의해, 반도체 칩(1)의 활성면 및 비활성면에는, 각각 동등한 열팽창계수의 판상체인 배선기판(2) 및 절연판(3)이 접합되어 있게 된다.As a result, the wiring board 2 and the insulating plate 3, which are plate-like bodies having the same thermal expansion coefficient, are joined to the active surface and the inactive surface of the semiconductor chip 1, respectively.

따라서, 환경온도가 변화한 경우에, 반도체 칩(1)의 활성면 및 비활성면에 있어서, 열팽창 또는 열수축이 동등하게 생기므로, 그 반도체장치의 사용시 또는 보관시 등에 패키지에 휘어짐이 생길 염려가 없다.Therefore, when the environmental temperature changes, thermal expansion or thermal contraction occurs equally on the active surface and the inactive surface of the semiconductor chip 1, so that there is no fear of warpage in the package when the semiconductor device is used or stored. .

이 칩사이즈 패키지형의 반도체장치는, 배선기판(2)의 하면에 설치된 복수개의 땜납볼(5)을 전자기기에 설치된 보다 큰 실장기판(10)에 전기 접속시키므로서,이 전자기기에 장착된다.This chip size package type semiconductor device is mounted on this electronic device by electrically connecting a plurality of solder balls 5 provided on the lower surface of the wiring board 2 to a larger mounting substrate 10 provided on the electronic device. .

도 2는, 본 발명의 제 2 실시형태에 관한 반도체장치의 구성을 설명하기 위한 도해적인 단면도이다.2 is a schematic cross-sectional view for explaining the configuration of the semiconductor device according to the second embodiment of the present invention.

또한, 이 도 2에 있어서, 상기 도 1에 표시된 각부에 대응하는 부분에는, 도 1의 경우와 동일한 참조부호를 부여하여 표시한다.In FIG. 2, parts corresponding to the respective parts shown in FIG. 1 are denoted by the same reference numerals as in the case of FIG.

이 반도체장치도, 상술한 도 1에 나타낸 제 1 실시예의 경우와 마찬가지로, 평면으로 보아 전체의 크기가 반도체 칩 자체의 크기와 거의 동등한, 소위 칩사이즈 패키지형의 것이다.This semiconductor device is also of a so-called chip size package type, similarly to the case of the first embodiment shown in FIG. 1 described above, in which the overall size is almost the same as that of the semiconductor chip itself.

이 실시형태의 반도체장치는, 복수개의 박형반도체 칩(11, 12, 13)을 적층하여 구성되어 있다.The semiconductor device of this embodiment is configured by stacking a plurality of thin semiconductor chips 11, 12, 13.

즉, 배선기판(2)상에 제 1의 반도체 칩(11)이 실장되어 있고, 이 반도체 칩(11)상에 배선기판(21)을 거쳐 제 2의 반도체 칩(12)이 적층되어 있고, 이 제 2의 반도체 칩(12)상에 배선기판(22)을 거쳐 제 3의 반도체 칩(13)이 적층되어 있다.That is, the first semiconductor chip 11 is mounted on the wiring board 2, and the second semiconductor chip 12 is laminated on the semiconductor chip 11 via the wiring board 21. The third semiconductor chip 13 is stacked on the second semiconductor chip 12 via the wiring substrate 22.

제 1의 반도체 칩(11)은, 상술한 제 1 실시형태에 있어서의 반도체 칩(1)의 경우와 마찬가지로, 그 활성면에 형성된 땜납볼(4)을 배선기판(2)에 접합시키므로서, 이 배선기판(2)을 통해 전자기기 내의 보다 큰 실장기판에 전기 접속될 수 있도록 되어 있다.Similarly to the case of the semiconductor chip 1 in the above-described first embodiment, the first semiconductor chip 11 joins the solder ball 4 formed on the active surface to the wiring board 2. The wiring board 2 can be electrically connected to a larger mounting board in the electronic device.

제 1의 반도체 칩(11)과 제 2의 반도체 칩(12) 사이에 개재 실장되는 배선기판(21)은, 제 1의 반도체 칩(11)에 대해서는, 그 활성면 및 비활성면의 열팽창의 차이를 보상하는 휘어짐 방지기판으로서 기능한다.The wiring substrate 21 interposed between the first semiconductor chip 11 and the second semiconductor chip 12 differs in thermal expansion between the active surface and the inactive surface of the first semiconductor chip 11. It functions as a warpage prevention substrate to compensate for the problem.

그리고, 이 배선기판(21)은, 제 2의 반도체 칩(12)에 대해서는, 외부와의 전기 접속을 위한 배선기판으로서 기능하고 있다.The wiring board 21 functions as a wiring board for electrical connection with the outside of the second semiconductor chip 12.

즉, 배선기판(21)은, 제 2의 반도체 칩(12)의 활성면에 형성된 복수개의 땜납볼(41)에 전기 접속되는 복수의 내부배선(도시생략)을 갖고 있다.That is, the wiring board 21 has a plurality of internal wirings (not shown) electrically connected to the plurality of solder balls 41 formed on the active surface of the second semiconductor chip 12.

이 내부배선은, 배선기판(21)의 하면, 즉 제 1의 반도체 칩(11)측의 면에 설치된 층간접속부재(51)(배선재)에 접속되어 있다.This internal wiring is connected to the interlayer connecting member 51 (wiring material) provided on the lower surface of the wiring board 21, that is, on the surface of the first semiconductor chip 11 side.

층간접속부재(51)는, 배선기판(2) 및 배선기판(21)의 각 내부배선간을 접속하도록, 제 1의 반도체 칩(11)의 주위에 복수개 배열되어 설치되어 있다.A plurality of interlayer connecting members 51 are arranged and arranged around the first semiconductor chip 11 so as to connect between the wiring board 2 and the internal wirings of the wiring board 21.

배선기판(21)의 내부배선이 이 층간접속부재(51)에 접속되므로서, 제 2의 반도체 칩(12)은, 땜납볼(41) 및 배선기판(21)의 내부배선 및 층간접속부재(51)를 거쳐, 배선기판(2)에 전기 접속되게 된다.Since the internal wiring of the wiring board 21 is connected to the interlayer connecting member 51, the second semiconductor chip 12 is connected to the internal wiring and the interlayer connecting member of the solder ball 41 and the wiring board 21. 51 is electrically connected to the wiring board 2.

층간접속부재(51)는, 배선기판(2)의 내부배선에 접속되어 있으므로, 제 2의 반도체 칩(12)과 제 1의 반도체 칩(11) 사이의 전기 접속이 가능함과 동시에, 제 2의 반도체 칩(12)과 그 반도체장치가 실장되는 전자기기내의 실장기판 사이의 전기 접속도 가능하다.Since the interlayer connection member 51 is connected to the internal wiring of the wiring board 2, the electrical connection between the second semiconductor chip 12 and the first semiconductor chip 11 is possible, and Electrical connection between the semiconductor chip 12 and the mounting board in the electronic device in which the semiconductor device is mounted is also possible.

제 3의 반도체 칩(13)에 관해서도 같은 구조가 취해져 있다.The same structure is taken also with respect to the third semiconductor chip 13.

즉, 제 2의 반도체 칩(12)과 제 3의 반도체 칩(13) 사이에 개재 실장된 배선기판(22)은, 제 2의 반도체 칩(12)에 대해, 그 활성면 및 비활성면 사이의 열팽창계수의 차이를 보상하기 위한 휘어짐 방지기판으로서 기능한다.That is, the wiring board 22 interposed between the second semiconductor chip 12 and the third semiconductor chip 13 has a difference between the active surface and the inactive surface with respect to the second semiconductor chip 12. It functions as a warpage prevention substrate for compensating for the difference in thermal expansion coefficient.

제 3의 반도체 칩(13)의 활성면에 설치된 복수의 땜납볼(42)은, 배선기판(22)의 내부배선(도시생략)에 접속되어 있다.The plurality of solder balls 42 provided on the active surface of the third semiconductor chip 13 are connected to an internal wiring (not shown) of the wiring board 22.

이 배선기판(22)의 내부배선은, 배선기판(21, 22) 사이에 배치된 층간접속부(52)에 각각 접속되어 있다.The internal wiring of the wiring board 22 is connected to the interlayer connecting portions 52 arranged between the wiring boards 21 and 22, respectively.

층간접속부(52)는, 제 2의 반도체 칩(12)의 주위에 복수개 배열되어 설치되어 있다.The interlayer connecting portion 52 is arranged in plural around the second semiconductor chip 12.

이 층간접속부재(52)는, 배선기판(21)의 내부배선에 접속되어 있다.The interlayer connection member 52 is connected to the internal wiring of the wiring board 21.

이에 의해, 제 3의 반도체 칩(13)은, 제 1 또는 제 2의 반도체 칩(11, 12)에 전기 접속되는 외에, 그 반도체장치가 실장되는 전자기기내의 실장기판에도 전기 접속될 수 있도록 되어 있다.As a result, the third semiconductor chip 13 is electrically connected to the first or second semiconductor chips 11 and 12, and can also be electrically connected to the mounting substrate in the electronic device on which the semiconductor device is mounted. have.

제 3의 반도체 칩(13)의 상면, 즉 비활성면에는, 절연판(3)이 예를 들면 접착제에 의해 첨부되어 있다.The insulating plate 3 is attached to the upper surface of the third semiconductor chip 13, that is, the inactive surface, by an adhesive, for example.

배선기판(2, 21, 22) 및 절연판(3)은, 어느 것이나 동일한 절연재료를 사용하여 구성되어 있고, 또한 그들의 두께가 거의 동등하게 형성되어 있다.Both the wiring boards 2, 21, 22 and the insulating plate 3 are made of the same insulating material, and their thicknesses are formed almost equal.

따라서, 제 1, 제 2 및 제 3의 반도체 칩(11, 12, 13)에 대해서는, 각 활성면 및 비활성면에 있어서의 열팽창 및 열수축이 각각 동등하게 생기기 때문에, 환경온도의 변화에 의해 어느 것인가의 반도체 칩에 휘어짐이 생기는 일이 없다.Therefore, for the first, second, and third semiconductor chips 11, 12, and 13, thermal expansion and thermal contraction on each active surface and inactive surface occur equally, so which one is due to a change in environmental temperature? Warping does not occur in the semiconductor chip.

이상, 본 발명의 두 가지 실시형태에 대해 설명했으나, 본 발명은 다른 형태로도 실시할 수가 있다.As mentioned above, although two embodiment of this invention was described, this invention can also be implemented with other aspects.

즉, 상술한 두 가지 실시형태에서는, 최하층에 위치하는 배선기판(2)의 하면에 땜납볼(5)을 복수개 배열한, 소위 볼그리드 어레이 형식의 반도체장치에 대해 설명했으나, 반도체장치와 전자기기 내부의 실장기판 등과의 접속은, 다른 형식의 외부단자에 의해서도 행할 수가 있다.That is, in the above-described two embodiments, a so-called ball grid array type semiconductor device in which a plurality of solder balls 5 are arranged on the lower surface of the wiring board 2 positioned at the lowermost layer has been described. The connection to the internal mounting board or the like can also be made by other types of external terminals.

즉, 배선기판(2)의 하면에 땜납볼(5)을 설치하지 않고, 배선기판(2)의 내부배선에 접속된 평탄한 단자부(랜드)를 노출시켜 두는 랜드그리드 어레이 형식이 채용되어도 된다.That is, a land grid array type may be employed in which the flat terminal portion (land) connected to the internal wiring of the wiring board 2 is exposed without providing the solder balls 5 on the lower surface of the wiring board 2.

또, 상술한 제 2 실시형태에서는, 3개의 반도체 칩(11, 12, 13)을 적층한 예에 대해 설명했으나, 2층 구조의 반도체장치나, 4층 이상으로 반도체 칩을 적층한 구조도 같은 모양으로 실현할 수 있다.In addition, in the above-mentioned 2nd Embodiment, although the example which laminated | stacked three semiconductor chips 11, 12, and 13 was demonstrated, the semiconductor device of 2-layer structure and the structure which laminated | stacked the semiconductor chip in four or more layers are also the same. It can be realized in shape.

또한, 상술한 실시형태에서는, 반도체 칩의 배선기판으로의 접합을 땜납볼로 행하도록 하고 있으나, 반도체 칩의 표면에 금 등의 내산화성 금속으로 된 돌기를 형성하여, 이것을 배선기판의 표면에 형성한 금도금부 등에 접합하도록 하여, 반도체 칩을 배선기판에 접합해도 된다.Further, in the above-described embodiment, the bonding of the semiconductor chip to the wiring board is performed by solder balls. However, projections made of an oxidation-resistant metal such as gold are formed on the surface of the semiconductor chip and formed on the surface of the wiring board. The semiconductor chip may be bonded to the wiring board by bonding to a gold plating part or the like.

본 발명의 실시형태에 대해 상세히 설명해 왔으나, 이는 본 발명의 기술적 내용을 명백히 하기 위해 이용된 구체예에 불과하며, 본 발명은 이들 구체예에 한정해서 해석될 것이 아니라, 본 발명의 정신 및 범위는 첨부하는 청구의 범위에 의해서만 한정된다.While embodiments of the present invention have been described in detail, these are merely embodiments used to clarify the technical contents of the present invention, and the present invention is not to be construed as being limited to these embodiments, but the spirit and scope of the present invention It is limited only by the appended claims.

본 발명은 박형의 반도체 칩을 배선기판에 접합한 구조이면서 휘어짐이 생기는 것을 방지할 수 있는 반도체장치를 제공한다.SUMMARY OF THE INVENTION The present invention provides a semiconductor device in which a thin semiconductor chip is bonded to a wiring board while being capable of preventing warpage.

Claims (5)

반도체 칩과,Semiconductor chip, 상기 반도체 칩의 한쪽 표면측에 접합되며, 상기 반도체 칩과 전기 접속된 배선기판과,A wiring board bonded to one surface side of the semiconductor chip and electrically connected to the semiconductor chip; 상기 반도체 칩의 다른 쪽의 표면측에 접합되며, 상기 배선기판과 동일한 재료로 된 휘어짐 방지기판을 포함하는 것을 특징으로 하는 반도체장치.And a bending preventing substrate bonded to the surface side of the other side of the semiconductor chip and made of the same material as the wiring substrate. 제 1항에 있어서,The method of claim 1, 상기 배선기판의 상기 반도체 칩과는 반대측의 표면에, 표면실장용의 외부접속부재가 배치되어 있는 것을 특징으로 하는 반도체장치.A semiconductor device according to claim 1, wherein an external connection member for surface mounting is arranged on a surface of the wiring board opposite to the semiconductor chip. 제 1항에 있어서,The method of claim 1, 상기 휘어짐 방지기판은 별도의 배선기판으로서, 이 휘어짐 방지기판의 상기 반도체 칩과는 반대측에, 그 휘어짐 방지기판에 전기 접속된 별도의 반도체 칩이 접합되어 있는 것을 특징으로 하는 반도체장치.And wherein the warpage preventing substrate is a separate wiring board, and on the side opposite to the semiconductor chip of the warpage prevention substrate, a separate semiconductor chip electrically connected to the warpage prevention substrate is joined. 제 2항에 있어서,The method of claim 2, 상기 휘어짐 방지기판은 별도의 배선기판으로서, 이 휘어짐 방지기판의 상기 반도체 칩과는 반대측에, 그 휘어짐 방지기판에 전기 접속된 별도의 반도체 칩이접합되어 있는 것을 특징으로 하는 반도체장치.And wherein the warpage preventing substrate is a separate wiring board, and on the side opposite to the semiconductor chip of the warpage prevention substrate, a separate semiconductor chip electrically connected to the warpage prevention substrate is joined. 제 1항 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 배선기판과 휘어짐 방지기판 사이에, 이들을 전기 접속하기 위한 배선재가 개재 실장되어 있는 것을 특징으로 하는 반도체장치.A semiconductor device comprising a wiring material interposed between the wiring board and the warpage prevention board for electrically connecting them.
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