KR20010065176A - Method of manufacturing a capacitor in a semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a capacitor of a semiconductor device, in order to solve the problem that the process stability is degraded due to a plurality of CMP process to alleviate the step between the cell region and the surrounding region during capacitor manufacturing, the lower portion formed in the cell region The trench pattern formed by the same process as the lower electrode on the boundary between the cell region and the peripheral region among the electrodes is used as a guard ring, and by using this, the capacitor formation oxide film is partially removed only in the cell region, thereby allowing subsequent interlayer insulation films. A method for manufacturing a capacitor of a semiconductor device, which can alleviate the step difference between a cell region and a peripheral region even by omitting a CMP process for planarization of the surface.

Description

Method of manufacturing a capacitor in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device for minimizing a step at a boundary portion between a cell block and a surrounding area.

In a DRAM manufacturing method of 0.2 µm or less technology, when a crown or cylinder structure is applied as a capacitor structure, two chemical mechanical poliding (CMP) processes are generally performed. Then, a conventional capacitor manufacturing method will be described with reference to FIG. 1.

1A and 1B are cross-sectional views of a device for explaining a capacitor manufacturing method of a conventional semiconductor device.

As shown in FIG. 1A, the first interlayer insulating film 12 and the etching barrier layer 13 are formed on the substrate 11 on which the substructure for forming the capacitor is formed, and the charge storage node in the cell region is formed. The etch barrier layer 13 and the first interlayer insulating film 12 are patterned. Thereafter, a conductive material is interposed between the etch barrier layer 13 and the first interlayer insulating layer 12 pattern to form a charge storage node 14, and an oxide film 15 for forming a capacitor is formed on the entire structure. Next, after the capacitor forming oxide film 15 is patterned, a conductive layer 16 to be used as a lower electrode is formed over the entire structure, and a metastable polysilicon (MPS) layer is formed on the conductive layer 16. (17) is formed. Subsequently, a first CMP process is performed to polish a part of the metastable polysilicon layer 17, the conductive layer 16, and the capacitor forming oxide film 15 formed on the upper surface of the capacitor forming oxide film 15 to AA ′. .

As shown in FIG. 1B, the capacitor forming oxide film 15 is removed, the dielectric film 18 is formed on the surface of the conductive layer 16 for the lower electrode, and then the upper electrode 19 is formed. After that, the second interlayer insulating film 20 is formed on the entire structure in order to alleviate the step difference between the cell region in which the capacitor is formed and the surrounding area. Then, the second interlayer insulating film 20 is polished to BB 'by the second CMP process. To flatten.

As described above, in the conventional capacitor manufacturing process, two CMP processes are performed. The CMP process increases process steps, makes equipment difficult to maintain, and consumes a lot of consumable materials, which greatly increases the process cost. In addition, the scratch problem due to the slurry used in the CMP process, etc., is difficult to completely solve in reality, and thus the reliability of the device cannot be guaranteed.

Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device capable of minimizing a step difference between a cell region and a surrounding region without using a CMP process.

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: providing a substrate on which a substructure including a plurality of charge storage nodes is formed; Forming a capacitor formation oxide pattern in which the plurality of charge storage nodes are individually exposed, wherein the oxide pattern is formed in a plurality of hole patterns in a cell region and a trench pattern in the form of a closed line along the outermost portion of the cell region. step; Forming a conductive layer on the entire top surface including the oxide film pattern, and then filling a gap between the hole pattern and the trench pattern portion with a first photosensitive film; Forming a second photoresist film on the entire structure after leaving the conductive layer and the first photoresist film in the hole pattern and the trench pattern by a polishing process; Exposing the first and first photoresist films of a cell region based on the trench patterns, and then removing the exposed photoresist to form a second photoresist pattern; And forming a plurality of lower electrodes in the hole pattern by forming the plurality of lower electrodes in the hole pattern, forming a guard ring in the trench pattern, and then forming a dielectric film and an upper electrode in the cell region.

1A and 1B are cross-sectional views of a device for explaining a method of manufacturing a capacitor of a conventional semiconductor device.

2A to 2D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.

3 is a schematic plan view of a semiconductor device to which the present invention is applied;

<Description of the symbols for the main parts of the drawings>

20: guard ring 21: substrate

22: first interlayer insulating film 23: etching barrier layer

24: charge storage node 25: oxide film for capacitor formation

26 conductive layer 27 metastable polysilicon layer

28: photosensitive film 29: photosensitive film pattern

30 dielectric film 31 upper electrode

32: second interlayer insulating film CB: cell block

100: lower electrode 200: guard ring

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2A to 2D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.

As shown in FIG. 2A, the first interlayer insulating layer 22 and the etching barrier layer 23 are formed on the substrate 21 on which the substructure for forming the capacitor is formed, and the charge storage node in the cell region is formed. The etch barrier layer 23 and the first interlayer insulating film 22 are patterned. Thereafter, a conductive material is interposed between the etching barrier layer 23 and the first interlayer insulating layer 22 pattern to form a charge storage node 24, and an oxide film 25 for forming a capacitor is formed on the entire structure. Next, the capacitor formation oxide film 25 is patterned so that the plurality of charge storage nodes 24 are individually exposed. In this case, the capacitor forming oxide layer 25 is patterned to have a plurality of hole patterns in the cell region and a trench pattern having a closed curve along the outermost portion of the cell region. After forming a conductive layer 26 to be used as a lower electrode on the entire structure, a metastable polysilicon (MPS) layer 27 is formed. Thereafter, the photosensitive film 28 is formed on the entire structure such that the gap between the conductive layer 26, that is, the hole pattern and the trench pattern portion is filled. Here, the lower electrode forming oxide film 25 is formed using, for example, BPSG, and the dopant concentration of boron (B) is 20 volume or more and the dopant of phosphorus (P) so that the BPSG film is easily removed by a wet method. The concentration is made 8 volume% or more. In addition, the etching barrier layer 23 is formed to a thickness of 300 kPa or less using an oxide film or a nitride film.

As shown in FIG. 2B, a part of the photosensitive film 28, the metastable polysilicon layer 27, the conductive layer 26 and the capacitor forming oxide film 25 is polished to AA 'in FIG. 2A. At this time, the capacitor formed at the boundary between the cell region and the surrounding region is formed in an extra pattern, and all are connected in a constant width so that a guard ring 200 is formed.

As shown in FIG. 2C, the photoresist pattern 29 is formed on the entire structure without removing the photoresist layer 28 inside the conductive layer 26, and the exposure process is performed to open the photoresist pattern 29. Form. Thereafter, the capacitor forming oxide film 25 and the photosensitive film 28 in the cell region are removed to form a plurality of lower electrodes 100 in the hole pattern, and the guard ring 200 is formed in the trench pattern. Here, the boundary between the portion where the photoresist film is exposed and the portion that is not exposed is to be inside the guard ring 200. The capacitor forming oxide layer 25 is removed by a wet etching method, and since the boundary between the cell region and the surrounding region is blocked by the guard ring 200, etching in the lateral direction does not occur. Even after the capacitor formation oxide film 25 in the cell region is removed, the capacitor formation oxide film in the peripheral region still remains, so that no step is generated between the cell region in which the capacitor is formed and the peripheral region, and the flattening is performed as in the CMP process. It becomes the state that it is.

As shown in FIG. 2D, after removing the photoresist pattern 29 and the photoresist 28 remaining in the guard ring, the dielectric film 30 is formed on the surface of the lower electrode 100 and the upper electrode 31 is formed. The capacitor is completed. Thereafter, a second interlayer insulating film 32 is formed on the entire structure. The step D generated in the guard ring 200 after forming the second interlayer insulating layer 32 is about the thickness of the upper electrode 31.

3 is a schematic plan view of a semiconductor device to which the present invention is applied.

As shown, it can be seen that each of the plurality of cell blocks CB0, CB1, CB2, CB3,... Is separated by a guard ring 200 connected at a constant width to an extra capacitor formed at an outermost portion.

In general, in the device of 256M DRAM class or higher, the height of the capacitor is increased to 1 μm or more. According to the present invention, the step between the cell region and the surrounding region can be reduced to less than 1/5. In addition, the thickness of the interlayer insulating film deposited after the capacitor can be reduced, so that the thickness of the interlayer insulating film can be reduced to 1/5 or less.

As described above, the present invention forms a guard ring at the boundary between the cell region and the surrounding region, thereby minimizing the step difference between the cell region and the surrounding region without omitting the CMP process. In this way, if the CMP process is omitted, various problems caused by the slurry may be solved, thereby securing the stability of the process.

Claims (2)

Providing a substrate having a substructure comprising a plurality of charge storage nodes; Forming a capacitor formation oxide pattern in which the plurality of charge storage nodes are individually exposed, wherein the oxide pattern is formed in a plurality of hole patterns in a cell region and a trench pattern in a closed curve along the outermost portion of the cell region; ; Forming a conductive layer on the entire top surface including the oxide film pattern, and then filling a gap between the hole pattern and the trench pattern portion with a first photosensitive film; Forming a second photoresist film on the entire structure after leaving the conductive layer and the first photoresist film in the hole pattern and the trench pattern by a polishing process; Exposing the first and second photoresist layers of a cell region based on the trench patterns, and then removing the exposed photoresist to form a second photoresist pattern; And And forming a dielectric film and an upper electrode after removing the oxide pattern of the cell region, forming a plurality of lower electrodes in the hole pattern, and forming a guard ring in the trench pattern. Manufacturing method. 2. The method of claim 1, wherein the capacitor forming oxide film is formed using a BPSG film having a boron dopant concentration of 20 volume or more and a phosphorus dopant concentration of 8 volume or more.