KR20010063866A - Method for leveling semiconductor device - Google Patents

Method for leveling semiconductor device Download PDF

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Publication number
KR20010063866A
KR20010063866A KR1019990061970A KR19990061970A KR20010063866A KR 20010063866 A KR20010063866 A KR 20010063866A KR 1019990061970 A KR1019990061970 A KR 1019990061970A KR 19990061970 A KR19990061970 A KR 19990061970A KR 20010063866 A KR20010063866 A KR 20010063866A
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South Korea
Prior art keywords
planarization
insulating film
semiconductor
cmp
planarized
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KR1019990061970A
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Korean (ko)
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백계현
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990061970A priority Critical patent/KR20010063866A/en
Publication of KR20010063866A publication Critical patent/KR20010063866A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric

Abstract

PURPOSE: A method for planarizing a semiconductor device is provided to reduce process variation and manufacturing cost and to easily control a degree of planarization, by using two planarization methods such as partial planarization by a sputtering method and planarization by a chemical mechanical polishing(CMP) method. CONSTITUTION: A substrate(31) having a plurality of interconnections(32) is prepared. The first insulation layer(33) is formed on the entire surface. The first insulation layer is partially planarized by a sputtering method. The second insulation layer(34) is formed on the partially-planarized first insulation layer. The second insulation layer is planarized by a chemical mechanical polishing(CMP) method.

Description

반도체 소자의 평탄화 방법{METHOD FOR LEVELING SEMICONDUCTOR DEVICE}Method of planarization of semiconductor device {METHOD FOR LEVELING SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 평탄화 방법에 관한 것으로, 특히 평탄화 공정을 이원화하여 소자의 경제성을 향상시키는 반도체 소자의 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device, and more particularly to a planarization method of a semiconductor device for dualizing the planarization process to improve the economics of the device.

현재 반도체 공정에서 사용하는 시엠피(Chemical Mechanical Polishing:CMP) 공정은 화학적, 기계적인 메커니즘(Mechanism)이 복합적으로 작용하고 이후클리닝(Cleaning) 공정을 거쳐야 하는 등 고려할 변수가 많고 어려운 공정이다.The chemical mechanical polishing (CMP) process used in the current semiconductor process is a difficult and difficult process with many variables to consider, such as a combination of chemical and mechanical mechanisms and a subsequent cleaning process.

또한, 상기 CMP 공정 자체가 물질의 연마를 통하여 평탄화를 이루기 때문에 여분의 물질을 증착 즉 샌드위치(Sandwich) 구조로 증착하게 된다.In addition, since the CMP process itself is planarized through polishing of the material, an extra material is deposited, that is, a sandwich structure.

이때, CMP 공정의 균일도가 10%내외로 나쁘기 때문에 CMP 공정 이전에 일부 평탄화를 이루기 위하여 또한 토폴로지가 증가하게 되면 CMP 타겟(Target)이 증가하기 때문에 상기 샌드위치 구조의 평탄화 대상층의 두께가 두꺼워짐에 따른 스텝 커버리지(Step Coverage) 문제를 해결하기 위하여 상기 샌드위치 구조의 중간 물질은 유동 특성 및 스텝 커버리지가 좋은 것을 증착한다.In this case, since the uniformity of the CMP process is about 10%, the thickness of the planarization target layer of the sandwich structure increases due to the increase in the CMP target (Target) in order to achieve some planarization before the CMP process and also to increase the topology. In order to solve the step coverage problem, the intermediate material of the sandwich structure deposits a good flow characteristic and step coverage.

종래 기술에 따른 반도체 소자의 평탄화 방법은 도 1a에서와 같이, 반도체 기판(11)상에 다수 개의 배선(12)들을 형성한다.In the planarization method of the semiconductor device according to the related art, as shown in FIG. 1A, a plurality of wirings 12 are formed on the semiconductor substrate 11.

그리고, 상기 배선(12)들을 포함한 반도체 기판(11)상에 제 1 절연막(13)과 유동 특성 및 스텝 커버리지가 좋은 제 2 절연막(14) 그리고 제 3 절연막(15)의 샌드위치 구조의 절연막을 형성한다.An insulating film having a sandwich structure of the first insulating film 13, the second insulating film 14 having good flow characteristics and step coverage, and the third insulating film 15 is formed on the semiconductor substrate 11 including the wirings 12. do.

여기서, 상기 제 2 절연막(14)을 비피에스지(Boron Phosphrus Silicate Glass:BPSG) 또는 O3-티이오에스(Tetra Ethyl Ortho Silicate:TEOS)의 다공성 절연막으로 형성한다.The second insulating layer 14 may be formed of a porous insulating layer of boron phosphrus silicate glass (BPSG) or O 3 -Tiotra (Tetra Ethyl Ortho Silicate (TEOS).

도 1b에서와 같이, 상기 제 3 절연막(15)을 CMP 방법에 의해 평탄화 한다.As shown in FIG. 1B, the third insulating film 15 is planarized by the CMP method.

여기서, 상기 제 3 절연막(15)의 평탄화 공정 시 CMP 타겟이 증가 할 경우 도 2에서와 같이, 상기 제 2 절연막(14)이 부분적으로 노출된다.Here, when the CMP target increases during the planarization of the third insulating layer 15, as shown in FIG. 2, the second insulating layer 14 is partially exposed.

그러나 종래의 반도체 소자의 평탄화 방법은 CMP 방법에 의한 평탄화 공정 시 다음과 같은 문제점이 있었다.However, the conventional planarization method of the semiconductor device has the following problems in the planarization process by the CMP method.

첫째, 샌드위치 구조의 절연막의 중간 물질은 유동 특성 및 스텝 커버리지가 좋지만 구조가 다공성이기 때문에 대기 중의 수분을 흡착하고 상기 절연층 내에 함유된 이온성 불순물들이 절연 특성을 방해하며 절연층간의 접촉 불량이 발생되고 또한 층간의 열팽창계수의 차이로 균열이 발생한다.First, the intermediate material of the insulating film of the sandwich structure has good flow characteristics and step coverage, but since the structure is porous, it adsorbs moisture in the air, and ionic impurities contained in the insulating layer interfere with the insulating property and poor contact between the insulating layers occurs. In addition, cracking occurs due to a difference in coefficient of thermal expansion between layers.

둘째, CMP 타겟이 증가하는 경우 중간층의 절연막이 부분적으로 노출되기 때문에 후속 공정에서 치명적인 결함의 원인이 된다.Second, when the CMP target is increased, the insulating film of the intermediate layer is partially exposed, which causes fatal defects in subsequent processes.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 CMP 공정 이전의 부분적인 평탄화 공정으로 스퍼터링(Sputtering) 방법을 사용하므로 다공성 절연막을 형성하지 않고 평탄화 하는 반도체 소자의 평탄화 방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and therefore, the sputtering method is used as a partial planarization process before the CMP process. .

도 1a와 도 1b는 종래 기술에 따른 반도체 소자의 평탄화 방법을 나타낸 공정 단면도1A and 1B are cross-sectional views illustrating a planarization method of a semiconductor device according to the related art.

도 2는 종래 기술에서 제 2 절연막이 부분적으로 노출됨을 나타낸 단면도2 is a cross-sectional view showing partially exposed second insulating film in the prior art

도 3a 내지 도 3d는 본 발명의 실시 예에 따른 반도체 소자의 평탄화 방법을 나타낸 공정 단면도3A to 3D are cross-sectional views illustrating a planarization method of a semiconductor device in accordance with an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

31: 반도체 기판 32: 배선층31: semiconductor substrate 32: wiring layer

33: 제 1 절연막 34: 제 2 절연막33: first insulating film 34: second insulating film

본 발명의 반도체 소자의 평탄화 방법은 다수 개의 배선들이 형성된 기판을 마련하는 단계, 전면에 제 1 절연막을 형성하는 단계, 상기 제 1 절연막을 스퍼터링 방법에 의해 부분적으로 평탄화하는 단계, 상기 부분적으로 평탄화된 제 1 절연막(33)상에 제 2 절연막을 형성하는 단계 및 상기 제 2 절연막을 CMP 방법에 의해 평탄화하는 단계를 포함하여 이루어짐을 특징으로 한다.According to an aspect of the present invention, there is provided a method of planarizing a semiconductor device, the method including: preparing a substrate having a plurality of wirings; And forming a second insulating film on the first insulating film 33 and planarizing the second insulating film by the CMP method.

상기와 같은 본 발명에 따른 반도체 소자의 평탄화 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the planarization method of the semiconductor device according to the present invention as described above will be described in detail with reference to the accompanying drawings.

본 발명의 실시 예에 따른 반도체 소자의 평탄화 방법은 도 3a에서와 같이, 반도체 기판(31)상에 다수 개의 배선(32)들을 형성한다.In the planarization method of the semiconductor device according to the embodiment of the present invention, as shown in FIG. 3A, a plurality of wires 32 are formed on the semiconductor substrate 31.

그리고, 상기 배선(32)들을 포함한 반도체 기판(31)상에 제 1 절연막(33)을 형성한다.In addition, a first insulating layer 33 is formed on the semiconductor substrate 31 including the wirings 32.

그리고, 상기 제 1 절연막(33)상에 스퍼터링 공정으로 아르곤(Ar) 이온을 활성화 시킨다.In addition, argon (Ar) ions are activated on the first insulating layer 33 by a sputtering process.

도 1b에서와 같이, 상기 아르곤 이온의 활성화로 상기 제 1 절연막(33)을 부분적으로 평탄화한다.As shown in FIG. 1B, the first insulating layer 33 is partially planarized by activation of the argon ions.

여기서, 상기 제 1 절연막(33)이 부분적으로 평탄화된 이유는 토폴로지가 존재하는 물질을 스퍼터링하면 높낮이가 존재하는 모서리 부분이 먼저 부분적으로 제거(P)되는 현상인 패시트(Facet) 현상이 발생하기 때문이다.The first insulating layer 33 is partially planarized because, when sputtering a material having a topology, a facet phenomenon occurs, in which a corner portion having a height is partially removed (P) first. Because.

상기 패시트 현상은 가속된 이온이 부딪히는 각도에 따라 전해지는 에너지의 차이 때문에 발생하는 것으로 일반적으로 45°전후로 충돌할 때의 에너지 전달이 가장 크다.The facet phenomenon is caused by the difference in energy transmitted according to the angle at which the accelerated ions collide with each other. In general, the greatest energy transfer is achieved when the collision occurs around 45 °.

그 결과 모서리 부분이 가장 취약하기 때문에 다른 부분보다 먼저 스퍼터링된다.As a result, the edges are the most fragile and are sputtered before other parts.

결국 각이 존재하는 모서리 부분이 잘려지면서 높이가 낮은 부분으로 쌓이게 되는 현상이 발생한다.Eventually, the corners where the angles are present are cut off and accumulate in the lower part.

도 1c에서와 같이, 상기 패시트 현상에 의해 부분적으로 평탄화된 제 1 절연막(33)상에 제 2 절연막(34)을 형성한다.As shown in FIG. 1C, a second insulating film 34 is formed on the first insulating film 33 partially planarized by the facet phenomenon.

여기서, 상기 스퍼터링 공정에 의해 물리적인 어택(Attack)을 받은 제 1 절연막(33)의 표면에는 불완전한 실리콘(Si) 이온의 결합들이 존재하기 때문에 이후 공정에서의 절연막의 형성시 접착성이 우수해지고 스텝 커버리지도 좋아지므로 상기 제 2 절연막(34)을 형성하면서 2차적인 평탄화를 이루게 된다.Here, since incomplete bonds of silicon (Si) ions exist on the surface of the first insulating film 33 subjected to the physical attack by the sputtering process, the adhesion is excellent and the step is formed in the formation of the insulating film in the subsequent process. Since coverage is also good, secondary planarization is achieved while forming the second insulating film 34.

도 1d에서와 같이, 상기 부분적으로 평탄화된 제 2 절연막(34)을 CMP 방법에 의해 평탄화 한다.As shown in Fig. 1D, the partially planarized second insulating film 34 is planarized by the CMP method.

본 발명의 반도체 소자의 평탄화 방법은 스퍼터링에 의한 부분적인 평탄화와 CMP 방법에 의한 평탄화의 평탄화 공정을 이원화함으로 다음과 같은 이유에 의해 공정변수 및 비용의 감소 그리고 평탄화 정도의 조절 용이 및 공정 자체의 안정화로 소자의 신뢰성 및 경제성을 향상시키는 효과가 있다.The planarization method of the semiconductor device of the present invention dualizes the planarization of the partial planarization by sputtering and the planarization by the CMP method, thereby reducing process variables and costs, and controlling the degree of planarization and stabilizing the process itself for the following reasons. This has the effect of improving the reliability and economy of the device.

첫째, 평탄화 대상층인 절연층이 3층의 샌드위치 구조가 아닌 2층 구조이기 때문에 평탄화 공정을 위한 추가 물질인 다공성 절연막의 형성이 필요치 않아 절연층 사이의 접착력 및 열팽창계수 차이에 의한 균열 발생을 방지한다.First, since the insulating layer, which is the planarization target layer, is a two-layer structure rather than a three-layer sandwich structure, it is not necessary to form a porous insulating film, which is an additional material for the planarization process, and thus prevents cracking due to a difference in adhesive strength and thermal expansion coefficient between the insulating layers. .

둘째, 상기 스퍼터링 공정은 평탄화될 물질의 반응성을 좋게 하기 때문에 그 후속 공정에서의 절연층의 스텝 커버리지가 향상되어 절연층의 증착에 따른 2차적인 평탄화가 가능하다.Second, since the sputtering process improves the reactivity of the material to be planarized, the step coverage of the insulating layer in the subsequent process is improved to enable secondary planarization according to the deposition of the insulating layer.

셋째, CMP 공정에 따른 부산물이 적어지기 때문에 잔여물 생성이나 평탄화 물질의 물성 변화와 같은 부작용이 일어날 가능성이 적어진다.Third, the less by-products from the CMP process, the less chance of side effects such as residue formation or changes in physical properties of the planarization material.

Claims (1)

  1. 다수 개의 배선들이 형성된 기판을 마련하는 단계;Providing a substrate on which a plurality of wirings are formed;
    전면에 제 1 절연막을 형성하는 단계;Forming a first insulating film on the entire surface;
    상기 제 1 절연막을 스퍼터링 방법에 의해 부분적으로 평탄화하는 단계;Partially planarizing the first insulating film by a sputtering method;
    상기 부분적으로 평탄화된 제 1 절연막상에 제 2 절연막을 형성하는 단계;Forming a second insulating film on the partially planarized first insulating film;
    상기 제 2 절연막을 CMP 방법에 의해 평탄화하는 단계를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 평탄화 방법.And planarizing the second insulating film by a CMP method.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100910508B1 (en) * 2007-12-12 2009-07-31 주식회사 동부하이텍 Method for flatting surface of wafer
US9257456B2 (en) 2014-06-26 2016-02-09 Samsung Display Co., Ltd. Method of forming a metal pattern and method of manufacturing a display substrate
US9490275B2 (en) 2015-01-22 2016-11-08 Samsung Display Co., Ltd. Method for manufacturing thin film transistor array panel

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100910508B1 (en) * 2007-12-12 2009-07-31 주식회사 동부하이텍 Method for flatting surface of wafer
US9257456B2 (en) 2014-06-26 2016-02-09 Samsung Display Co., Ltd. Method of forming a metal pattern and method of manufacturing a display substrate
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