KR20010046340A - A control signal generator for data strobe buffer in ddr sdram - Google Patents

A control signal generator for data strobe buffer in ddr sdram Download PDF

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Publication number
KR20010046340A
KR20010046340A KR1019990050063A KR19990050063A KR20010046340A KR 20010046340 A KR20010046340 A KR 20010046340A KR 1019990050063 A KR1019990050063 A KR 1019990050063A KR 19990050063 A KR19990050063 A KR 19990050063A KR 20010046340 A KR20010046340 A KR 20010046340A
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KR
South Korea
Prior art keywords
signal
data strobe
output
pull
count unit
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KR1019990050063A
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Korean (ko)
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KR100318434B1 (en
Inventor
추신호
유기형
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박종섭
주식회사 하이닉스반도체
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4093Input/output [I/O] data interface arrangements, e.g. data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory technology, and more particularly to a data strobe buffer control signal generation circuit of DDR SDRAM (double data rate synchronous dynamic random access memory), and stable writing even if an unstable data strobe signal occurs after the last data is input. It is an object of the present invention to provide a data strobe buffer control signal generation circuit of a dial SDRAM to perform an operation. According to the present invention, a data strobe buffer itself can be disabled immediately after a continuous data input, thereby preventing a wrong signal from being loaded on the global I / O bus even if instability of the data strobe such as overshoot is caused. Since the data strobe signal always starts at the rising edge and ends at the falling edge, a DS falling edge detection signal is used, which is a high pulse at each falling edge of the data strobe signal.

Description

D SDRAM's Data Strobe Buffer Control Signal Generation Circuit {A CONTROL SIGNAL GENERATOR FOR DATA STROBE BUFFER IN DDR SDRAM}

The present invention relates to semiconductor memory technology, and more particularly to a data strobe buffer control signal generation circuit of DDR double data rate synchronous dynamic random access memory (SDRAM).

In recent years, the most prominent issue in DRAM development is high-speed synchronous DRAM such as DDR SDRAM (double data rate SDRAM) and RAMBUS DRAM. Among them, DDR SDRAM is expected to lead the future memory market because it can operate twice as fast as conventional synchronous DRAM (SDRAM) and can be applied without changing the central processing unit (CPU).

DDR SDRAM, with data input and output on the rising and falling edges of the clock, eliminates the use of data strobes with pipeline operation, prefetch operations, and delay locked loops. It is a big feature.

1 is a diagram illustrating a timing during a write operation of a conventional DDR SDRAM. The data strobe signal includes a lower data strobe signal (LDS) and an upper data strobe (UDS). In FIG. 1, only the lower data strobe signal LDS will be described.

As shown, the lower data strobe signal LDS goes to the high impedance (Hi-Z) state after the continuous data input (DQ) operation is completed according to the write command. The last falling edge of the lower data strobe signal LDS is shown. Later, when an unstable signal such as overshoot occurs, bad data can be written to the global I / O bus. In other words, DDR SDRAM receives data at the rising and falling edges of the data strobe signal and aligns the data at the falling edge, causing polling of unnecessary data strobe signals due to overshoot. Incorrect data can be aligned.

In the figure, the 'LDSP2' signal is an internal pulse generated by receiving a lower data strobe (LDS), which is an external signal, and shows the signal ldsrp2 receiving the rising edge of the LDS and the signal ldsfp2 receiving the falling edge.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data strobe buffer control signal generation circuit of a dial SDRAM capable of performing a stable write operation even if an unstable data strobe signal occurs after the last data is input.

1 is a timing diagram during a write operation of a conventional DDR SDRAM.

2 is a circuit diagram of a data strobe buffer control signal of a DDR SDRAM according to an embodiment of the present invention;

3A is a detailed circuit diagram of the clock edge delay generator 20 of FIG.

3B is a detailed circuit diagram of the DSP2 disable signal generator 21 of FIG.

FIG. 3C is a detailed circuit diagram of the DS buffer off signal generator 22 of FIG.

4 is an operational waveform diagram of a DDR SDRAM according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: clock edge delay generator

21: DSP2 disable signal generator

22: DS buffer off signal generator

23: DS Polling Edge Detector

24: DS (lds, uds) buffer

In accordance with another aspect of the present invention, there is provided a data strobe buffer control signal generation circuit of a dial SDRAM of the present invention, including: shift counting means for shift counting a write command acknowledgment signal in synchronization with a clock; Disable signal generating means for generating a signal for disabling the pulsed signal at each edge of the data strobe signal by combining the shift counting signal output from the shift counting means and the continuous operation flag signal indicating the burst length; And generating a data strobe buffer off signal for generating a data strobe buffer off signal for turning off the data strobe buffer after the last falling edge of the data strobe signal by inputting the falling edge detection signal and the disable signal of the data strobe signal. Means.

In other words, the present invention enables the data strobe buffer itself to be disabled immediately after continuous data input, thereby preventing a wrong signal from being loaded on the global I / O bus even if instability of the data strobe such as overshoot is caused. . Since the data strobe signal always starts at the rising edge and ends at the falling edge, a DS falling edge detection signal is used, which is a high pulse at each falling edge of the data strobe signal.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2 is a diagram illustrating a data strobe buffer control signal generation circuit of a DDR SDRAM according to an embodiment of the present invention, in which a write command acknowledgment signal casp6_qfc that recognizes an external write command is increased to a level signal in synchronization with a clock clkp4_dly. DSP2 which makes the signal DIS_DSP2 which disables DSP2 by combining the clock edge delay generator 20 which consists of a shift counter circuit, the shift counter output signals wt1r, wt2r, wt4r, and the continuous operation flags bl2, bl4, bl8. The disable signal generator 21, the DS falling edge detector 23 for detecting the falling edges of the data strobe signals LDS and UDS, the DSP2 disable signal DIS_DSP2 and the falling edge detection signals ldsfp2 and udsfp2 are inputted. And a DS buffer off signal generator 22 for generating signals dis_ldsp2z and dis_udsp2z for turning off the data strobe buffer 24.

FIG. 3A shows a detailed circuit of the clock edge delay generator 20 of FIG. 2, wherein a shift counter inputs a write command acknowledgment signal casp6_qfc, a delay signal clkp4_dly of the clock signal clkp4, and a power and reset signal rstz as inputs. The circuit is shown.

The configuration and operation of the illustrated circuit are as follows.

First, the block 30 for obtaining the first rising count signal wt0r receives the pull-down NMOS N2 and start-up PMOS P5 having the write command acknowledgment signal casp6_qfc as the gate input and the clkp4_dly signal inverted through the inverter I192. A driver comprising a PMOS P1 serving as a gate input, a PMOS P95 serving as a gate input of the system power-up signal pwrup, and a latch composed of two inverters I7 and I8 for latching its output.

Further, the block 31 for obtaining the first polling count signal wt0f includes a transfer gate T194 which uses the clkp4_dly signal as the PMOS gate input and the inverted clkp4_dly signal as the NMOS gate input through the inverter I19, and A latch composed of two inverters I283 and I21 for latching the output, and an inverter I17 for inverting the output of the latch and outputting the first polling count signal wt0f.

On the other hand, the block 32 for obtaining the second rising count signal wt1r includes a transfer gate T268 having the clkp4_dly signal as the NMOS side gate input and the inverted clkp4_dly signal as the PMOS side gate input through the inverter I271, and Inverter I272 constituting a latch by engaging the outputs of the NAND gate I266 and NAND gate I266 with the output and the reset signal rstz, and for inverting the output of the latch and outputting the second rising count signal wt1r. It consists of an inverter I272.

The remaining circuit is configured in the same way as the second rising count block 32 in the case of the rising count block, and in the same manner as the first falling count block 31 in the case of the falling count block.

Block 33 is a block for generating the reset signal rstz. The inverter I308 receives the data input (din) buffer enable signal en_dindsz (low active), the output of the inverter I308 and the system power-up signal pwrup. A NAND gate I307 serving as an input and a NOR gate I306 serving as an input of an output of the NAND gate I307 and a clkp4_dly signal are configured.

Block 34 is a block for generating the delayed clock signal clkp4_dly, which is a series of inverters I305, I295 and I296 for inverting the data input (din) buffer enable signal en_dindsz (low active), and its output and clock signals clkp4. And a NAND gate I277 having an input as an input, and an inverter I281 for inverting its output and outputting it to clkp4_dly.

In the above circuit, when an external write command comes in, the write command acknowledgment signal casp6_qfc floats with a high pulse, the output wt0r of the first rising count block 30 goes high, and every edge of the delayed clock clkp4_dly (rising or polling). ), Wt0f, wt1r, wt1f, ..., wt4r become high states sequentially.

The system power up signal pwrup is used as a signal for holding the initial value of the latch of the first rising count block 30, and the reset signal rstz is used as a signal for resetting each rising count block.

FIG. 3B shows a detailed circuit of the DSP2 disable signal generator 21 of FIG. 2, in which a NAND gate having a continuous operation flag bl2 indicating a burst length '2' and a second rising count signal wt1r as an input. (I259), the NAND gate I261 inputting the continuous operation flag bl4 indicating the burst length '4' and the third rising count signal wt2r, and the last of the continuous operation flag bl8 indicating the burst length '8' and the shift counter. A NAND gate I260 that takes an output signal wt4r as an input, a three-input NAND gate I163 that takes an output of each of the NAND gates I259, I260, and I261, an inverter I258 that inverts its output, and And an inverter I262 which inverts its output again.

The circuit shown is denominated with the outputs wt1r, wt2r, wt4r and the continuous operation flags bl2, bl4, bl8 of the clock edge delay generator 20 of FIG. 3A to make dis_dsp2 high for disabling the DSP2 signal. If the burst length is '2', wt1r and bl2 meet and make dis_dsp2 high.

FIG. 3C shows a detailed circuit configuration of the DS buffer off signal generator 22 of FIG. 2, and the configuration and operation thereof will be described with reference to the accompanying drawings.

The illustrated blocks 34 and 35 respectively show a typical clock generator, which is a clock generator 34 having the falling edge detection signal ldsfp2 of the lower data strobe signal LDS output from the DS falling edge detector 23 of FIG. 2 as an input. ) Is an inverter I48 for inverting ldsfp2, a plurality of inverters I49 to I51 for delaying its output, and a NAND gate for outputting the ldsfp2d signal by inputting the output of the inverter I48 and the delayed output. I53). The ldsfp2d signal is a signal in which the duty of the ldsfp2 signal is increased.

The clock generator 35 which receives the falling edge detection signal udsfp2 of the upper data strobe signal UDS output from the DS falling edge detector 23 has an inverter I60 for inverting the udsfp2 signal and delays its output. And a plurality of inverters I56 to I57, and a NAND gate I54 for outputting the udsfp2d signal by inputting the output of the inverter I60 and the delayed output. The udsfp2d signal is a signal in which the duty of the udsfp2 signal is increased.

The block 36 related to the lower data strobe signal is composed of a driver 38, a latch 39, and an inverter I10. The block 37 related to the data strobe signal is also a driver 40 and a latch 41. ) And inverter I16. Since blocks 36 and 37 are identical in configuration except that the input signals are different, the configuration and operation will be described only for block 36 related to the lower data strobe signal.

First, on the pull-down side of the driver 38, the NMOS N44 using the write command acknowledgment signal casp6_qfc as the gate input from the ground power supply to the output terminal, the NMOS N1 using the ldsfp2d as the gate input, and the NMOS N111 using the DSP2 disable signal dis_dsp2 as the gate input. The P38 P31 having the data input buffer enable signal en_dinds as the gate input and the PMOS P32 having the DSP2 disable signal dis_dsp2 as the gate input are connected in series to the pull-up side of the driver 38 from the power supply to the output terminal. It is. In addition, a pull-up PMOS P43 having a write command acknowledgment signal casp6_qfc as a gate input is connected to the output terminal to initialize the latch. On the other hand, the latch is composed of two inverters (I110, I39) and outputs dis_ldsp2, this signal is inverted through the inverter (I10) is output as a low active signal dis_ldsp2z.

If the DSP2 disable signal dis_dsp2 is high and the signal ldsfp2d, which is a high pulse for each falling edge of the lower data strobe signal LDS, is activated high, the lower data strobe buffer off signal dis_ldsp2z is activated low to lower data strobe buffer. Will be turned off.

As described above, the operation of block 37 is the same as the operation of block 36 with respect to the upper data strobe buffer. In this embodiment, dividing the DS buffer off signal by dis_ldsp2z and dis_udsp2z indicates that the lower data strobe signal LDS and the upper data strobe signal UDS This is because they can be input at different timings (half-clock difference if most misaligned). In addition, the use of the DS falling edge detection signals ldsfp2 and udsfp2 that floats with high pulses on each falling edge of the data strobe signal is because the data strobe signal always starts from the rising edge and ends at the falling edge.

4 is a diagram illustrating an operation waveform of the DDR SDRAM according to the above-described embodiment. Even if an overshoot occurs after the last falling edge of the lower data strobe signal LDS, the interval is applied to the DS buffer off signal DIS_LDSP2z. As a result, the DS buffer does not perform an operation, thereby preventing a malfunction.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention described above has an effect of preventing wrong data from being written during an unstable operation after the last falling edge, thereby ensuring stable write operation characteristics of the DDR SDRAM.

Claims (7)

  1. Shift counting means for shift counting the write command acknowledgment signal in synchronization with a clock;
    Disable signal generating means for generating a signal for disabling the pulsed signal at each edge of the data strobe signal by combining the shift counting signal output from the shift counting means and the continuous operation flag signal indicating the burst length; And
    Data strobe buffer off signal generating means for generating a data strobe buffer off signal for turning off the data strobe buffer after the last falling edge of the data strobe signal by inputting the falling edge detection signal and the disable signal of the data strobe signal;
    And a data strobe buffer control signal generation circuit of a dial SDRAM.
  2. The method of claim 1,
    The shift counting means,
    The first rising count unit, the first falling count unit, the second rising count unit, the second falling count unit, the third rising count unit, the third falling count unit, the fourth rising count unit, and the fourth falling count unit connected in turn And a fifth rising count unit. The data strobe buffer control signal generation circuit of a dial SDRAM.
  3. The method of claim 2,
    The first rising count unit,
    A first pull-up transistor connected to a supply power source and controlled by the clock, a second pull-up transistor connected to the first pull-up transistor and an output terminal thereof, and connected to a ground power supply and a write command acknowledgment signal; A driver having a first pull-down transistor having a signal as a gate input, a third pull-up transistor connected to the supply power source and the output terminal and controlled by a system power-up signal;
    And a latch connected to an output terminal of the driver and initialized by the system power-up signal.
  4. The method of claim 3,
    The first to fourth polling count unit, respectively
    A transfer gate for switching the count value of the front end under the control of the clock;
    A latch for latching the count value;
    And a inverter for inverting the output of the latch.
  5. The method of claim 3,
    The second to fifth rising count units,
    A transfer gate for switching the count value of the front end under the control of the clock;
    A latch latching the count value and having a reset signal input;
    And a inverter for inverting the output of the latch.
  6. The method according to any one of claims 2 to 5,
    The disable signal generating means,
    A first NAND gate having a continuous operation flag signal indicating that the burst length is '2' and an output of the second rising count unit;
    A second NAND gate having a continuous operation flag signal indicating that the burst length is '4' and an output of the third rising count unit;
    A third NAND gate having a continuous operation flag signal indicating that the burst length is '8' and an output of the fifth rising count unit;
    And a fourth NAND gate having an output of the first to third NAND gates as an input.
  7. The method of claim 6,
    The data strobe buffer off signal generator,
    A second pull-down transistor connected to a ground power source and controlled by the write command acknowledgment signal, a third pull-down transistor connected to the second pull-down transistor and controlled by a signal in which the duty of the falling edge detection signal is increased, and the third pull-down transistor And a fourth pull-down transistor connected to an output terminal thereof and controlled by an output of the disable signal generating means, a fourth pull-up transistor connected to a supply power supply and controlled by an input buffer enable signal, and connected to the fourth pull-up transistor and the output terminal. A driver having a fifth pull-up transistor controlled by an output of the disable signal generating means, a power supply and a sixth pull-up transistor connected to the output terminal and controlled by the write command recognition signal;
    A latch for latching an output of the driver;
    And a inverter for inverting the output of the latch.
KR1019990050063A 1999-11-12 1999-11-12 A control signal generator for data strobe buffer in ddr sdram KR100318434B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100902126B1 (en) * 2008-04-30 2009-06-09 주식회사 하이닉스반도체 Semiconductor memory device and operation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100902126B1 (en) * 2008-04-30 2009-06-09 주식회사 하이닉스반도체 Semiconductor memory device and operation method thereof
US7843744B2 (en) 2008-04-30 2010-11-30 Hynix Semiconductor Inc. Semiconductor memory device and operation method thereof

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