KR20010004893A - Method of manufacture semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to improve uniformity of a chemical and mechanical polishing process by modifying a capping layer and thereby to stabilize the polishing process and other following processes. CONSTITUTION: First, a polysilicon layer(2) and a tungsten silicide layer(4) are deposited on a wafer to form a gate. Then, a plasma nitride layer(6) and an anti diffused reflection layer are formed as a capping layer on the tungsten silicide layer(4). The anti diffused reflection layer may be a silicon-rich oxynitride layer. Next, the first inter poly oxide layer is deposited and then a chemical and mechanical polishing process is performed thereto. Thereafter, a landing plug contact is formed and then a polysilicon layer is deposited for a landing plug(20). Next, a chemical and mechanical polishing process is performed to form the landing plug(20) until the nitride layer(6) is exposed.

Description

Method of manufacture semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to changing a capping layer used for a sacrificial oxide (SAC) process and a mask operation in a conventional device. ): Chemical & Mechnical Polishing) The present invention relates to a method for manufacturing a semiconductor device in which a step and a subsequent step are stabilized.

In general, as the integration of semiconductor devices increases, the size of the contact hole and line width required by the device is gradually decreasing. As the design decreases, the precision of the mask is also required.

In order to improve the precision of masking, it is essential to improve the global topology of wafers, and the chemical mechanical polishing (CMP) process is introduced for this planarization, and in devices with 256M DRAM or higher Four to five step chemical mechanical polishing (CMP) processes are applied.

However, in the conventional semiconductor device manufacturing method, the chemical mechanical polishing (CMP) process is essentially a cell edge and a peri due to the density of the pattern and the movement ratio of the wafer edge compared to the center. There was a problem with the movement costs in the region. Due to these problems, when multiple chemical mechanical polishing (CMP) processes are applied to the device fabrication, the lamination layers of the center and edges of the wafer, the cell and the ferry region have a considerable thickness difference, which is a result of contact hole formation. In the subsequent etching process, it is difficult to set a target, which causes various problems in the subsequent process.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to change the capping layer to be applied to the upper conductive layer such as poly 1, poly 2, and the like. The present invention provides a method of manufacturing a semiconductor device that stabilizes a chemical mechanical polishing (CMP) process and a subsequent process by improving uniformity.

1A to 1E are cross-sectional views of a manufacturing process of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

2: poly 4: tungsten silicide

6: plasma nitride film 8; Anti-reflective coating

12, 16: poly 14: oxide film

20: landing plug pulley

In order to achieve the above object, the semiconductor device manufacturing method of the present invention,

At least a first step of device isolation and deposition of poly and tungsten silicides on the entire surface of the wafer,

A second step of forming a nitride film and a silicon rich oxynitride film on the tungsten silicide;

A third step of forming a spacer after the process and depositing a first interpoly oxide to planarize by chemical mechanical polishing;

A fourth step of performing a landing plug contact mask and an etching process for forming a plug in the poly 2 and poly 3 contact positions of the active region after the process;

And depositing a poly to a predetermined thickness on the entire surface of the wafer to form a landing plug poly.

In addition to the above configuration, it is preferable to perform poly etch back when the nitride film is exposed to form the landing plug poly.

The polyetch back process preferably uses a chemical mechanical polishing process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

1A to 1E show cross-sectional views of a manufacturing process of a semiconductor device according to the present invention. With reference to the drawings, it will be described the process of manufacturing the semiconductor device of the present invention.

Device isolation is performed in a conventional manner, and then poly (2) and tungsten silicide (Wsix) 4 are deposited on the wafer for gate formation. After deposition, a capping layer is deposited for a hard mask in a gate process and a barrier in a subsequent contact forming process, and a gate line is manufactured by dry etching after the masking operation. Conventionally, an oxide film layer was mainly used to facilitate masking of barrier materials such as an insulation film and a photo, and in the present invention, in the present invention, the thickness of the insulation film is reduced and an anti-reflective film (Si-Rich Oxynitride) is formed on the top. (Hereinafter referred to as 'SRON') (8) was applied, and the overall thickness was adjusted to be similar to the existing. In this case, there is no problem in the dry etching for forming the gate (see FIG. 1A).

After the gate is formed, a plug is generally formed at a position where a poly 2 contact and a poly 3 contact are to be formed, and an interpoly oxide (IPO) 1 insulating layer 10 is deposited to form the landing plug poly.

After depositing the IPO1 layer 10, the cell 100 and the ferry 200 region of the wafer have a step created by the lower poly 1 (gate) line, and this step causes a good landing plug contact (LPC). Masking becomes impossible. To compensate for this, IPO1 chemical mechanical polishing (CMP) is performed (see FIG. 1B).

After the IPO1 chemical mechanical polishing (CMP), a landing plug contact (LPC) is formed using a landing plug contact (LPC) mask. When the landing plug contact (LPC) is etched, the anti-reflective film (SRON) 8 on the upper poly 1 line has a selectivity with respect to the oxide film 14, so that it can be maintained almost unremoved. After forming the landing plug contact (LPC), the poly is deposited on the front surface of the wafer to be used as the landing plug. Thereafter, an etching back may be performed to form Landing Plug Poly (LPP), but chemical mechanical polishing (CMP) may be more effective for subsequent processes.

As described above, during the chemical mechanical polishing (CMP) process, the edge of the wafer is moved faster than the center, and when the anti-reflective coating on the poly 1 is opened at the center of the wafer, the edge of the wafer is already opened. When the oxide slurry is used, the nitride film and the anti-reflective film have a selective movement ratio, so that the nitride film is formed at the edge area until the landing anti-reflective film (SRON) in the central area is completely removed and each landing plug poly (LPP) is separated. It will act as a barrier. After completion of the chemical mechanical polishing (CMP) process, the formation of landing plug poly as well as the side effect of planarization can be achieved, which is the same result not only in the center of the wafer but also in the cell and ferry regions (FIGS. 1C-1E).

As described above, according to the method of manufacturing a semiconductor device of the present invention, the uniformity of the conventional chemical mechanical polishing (CMP) process can be improved only by changing the capping layer applied to the upper conductive layer such as poly 1 or poly 2. This can stabilize the chemical mechanical polishing (CMP) process and subsequent processes. In addition, since the dry etching is not a problem in the line implementation technology of the conductive layer, it is possible to more stable wafer planarization only by applying the current retention technology, thereby enabling early development of the device and increased yield.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (3)

In the semiconductor device manufacturing method, At least a first step of device isolation and deposition of poly and tungsten silicides on the entire surface of the wafer, A second step of forming a nitride film and a silicon rich oxynitride film on the tungsten silicide; A third step of forming a spacer after the process and depositing a first interpoly oxide to planarize by chemical mechanical polishing; A fourth step of performing a landing plug contact mask and an etching process for forming a plug in the poly 2 and poly 3 contact positions of the active region after the process; And depositing poly to a predetermined thickness on the entire surface of the wafer to form a landing plug poly. The method of claim 1, wherein a poly etch back is performed when the nitride film is exposed to form the landing plug poly. The method of claim 2, wherein the polyetch back process uses a chemical mechanical polishing process.