KR20000057644A - Transverse electric field system liquid crystal display device suitable for improving aperture ratio - Google Patents

Abstract

PURPOSE: A transverse field system active matrix type liquid crystal display device is provided to improve maximum transmissivity with a wide visual field angle characteristics, excellent contrast ratio and aperture ratio. CONSTITUTION: An active matrix type liquid crystal display device capable of accomplishing an angle of visual field equal to that of a CRT and controlling the display by an electric field substantially parallel to a substrate surface provides bright display and requires lower power consumption. Pixel electrodes and opposed electrode capable of applying an electric field substantially parallel to a substrate surface is constituted, the pixel electrodes or the opposed electrodes are constituted by transparent electrodes, and the orientation state of a liquid crystal and the axis of polarization of a polarizer are constituted so that dark display is effected at the time when no field is applied.

Description

Transverse electric field type liquid crystal display device suitable for opening ratio improvement {TRANSVERSE ELECTRIC FIELD SYSTEM LIQUID CRYSTAL DISPLAY DEVICE SUITABLE FOR IMPROVING APERTURE RATIO}

BACKGROUND ART [0002] An active matrix liquid crystal display using active elements typified by thin film transistors (TFTs) is widely used as display terminals for OA devices in view of their thinness, light weight, and high quality comparable to CRTs. There are two types of display methods of this liquid crystal display device as follows.

One is a method of sandwiching a liquid crystal between two substrates composed of transparent electrodes, operating at a voltage applied to the transparent electrode, and modulating and displaying the light incident on the liquid crystal through the transparent electrode. All of these systems employ this method.

The other is a method in which a liquid crystal is operated by an electric field almost parallel to a substrate surface between two electrodes configured on the same substrate, and modulates and displays light incident on the liquid crystal from a gap between the two electrodes. This remarkably wide feature is called a transverse electric field method or an in-plane switching method as a promising technique for an active matrix liquid crystal display device.

The characteristics of the latter method are described in Japanese Patent Application Laid-open No. Hei 5-505247, Japanese Patent Application Laid-Open No. 63-21907, and Japanese Patent Laid-Open No. Hei 6-160878.

However, in the latter conventional method, since the opaque metal electrode is configured in the shape of a comb, the ratio (opening ratio) of the opening area through which light is transmitted is significantly low, and the latter active matrix type liquid crystal display device is displayed. There is a problem that the power consumption of the device increases because the screen is dark or a bright backlight having a large power consumption must be used to brighten the display screen.

In addition, as another problem, in the latter conventional method, since a metal electrode is used, there is also a problem that the reflectance at the electrode is high, and the face or the like is hard to see on the screen due to the reflection at the electrode.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal display device, and more particularly to a transverse electric field type liquid crystal display device having a wide visual characteristic suitable for improving aperture ratio.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of an essential part showing one pixel and its periphery of a liquid crystal display of the active matrix type color liquid crystal display of Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view of the pixel taken along the cutting line 3-3 of FIG. 1. FIG.

3 is a cross-sectional view of the thin film transistor element TFT taken along the cut line 4-4 of FIG.

4 is a cross-sectional view of the storage capacitor Cstg taken along the line 5-5 of FIG. 1.

5 is a plan view for explaining a configuration of a matrix peripheral portion of a display panel.

6 is a cross-sectional view showing a panel edge portion without a scan signal terminal on the left side and an external connection terminal on the right side.

FIG. 7A is a plan view showing the vicinity of a connection portion between the gate terminal GTM and the gate wiring GL, and FIG. 7B is a cross-sectional view thereof.

Fig. 8A is a plan view showing the vicinity of a connection portion between the drain terminal DTM and the video signal line DL, and Fig. 8B is a sectional view thereof.

Fig. 9A is a plan view showing the vicinity of a connection portion of a common electrode terminal CTM, a common bus line CB, and a common voltage signal line CL, and Fig. 9B is a sectional view thereof.

Fig. 10 is a circuit diagram including a matrix portion and its periphery of an active matrix type color liquid crystal display device of the present invention.

Fig. 11 shows driving waveforms of an active matrix type color liquid crystal display device of the present invention.

Fig. 12 is a flowchart of a cross sectional view of a pixel portion and a gate terminal portion showing manufacturing steps of steps A to C on the substrate SUB1 side;

Fig. 13 is a flowchart of a cross sectional view of a pixel portion and a gate terminal portion showing manufacturing steps of steps D to F on the substrate SUB1 side;

Fig. 14 is a flowchart of a cross sectional view of a pixel portion and a gate terminal portion showing the manufacturing steps of steps G to H on the substrate SUB1 side;

Fig. 15 is a top view showing a state in which peripheral driving circuits are mounted on a liquid crystal display panel.

Fig. 16 shows a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.

17 is an essential part cross sectional view showing a state in which a tape carrier package TCP is connected to a terminal GTM for a scan signal circuit of a liquid crystal display panel PNL.

18 is an exploded perspective view of a liquid crystal display module.

Fig. 19 shows the relationship between the applied electric field direction, the rubbing direction, and the polarizing plate transmission axis.

Fig. 20 is a plan view of an essential part showing one pixel and its periphery of a liquid crystal display of the active matrix type color liquid crystal display according to the second embodiment of the present invention.

Fig. 21 is a plan view of an essential part showing one pixel and its periphery of the liquid crystal display of the active matrix type color liquid crystal display of Example 3 of the present invention.

Fig. 22 is a plan view of an essential part showing one pixel and its periphery of a liquid crystal display of the active matrix type color liquid crystal display of Example 4 of the present invention.

Fig. 23 is a plan view of an essential part showing one pixel and its periphery of a liquid crystal display of the active matrix type color liquid crystal display of Example 5 of the present invention;

24A to 24C are principal part plan views and cross sectional views showing one pixel of the liquid crystal display unit and its periphery of the active matrix type color liquid crystal display device of the sixth embodiment of the present invention;

Fig. 25 is a plan view of an essential part showing one pixel of the liquid crystal display of the active matrix type color liquid crystal display of the seventh embodiment of the present invention and its periphery;

FIG. 26 is a cross sectional view taken along line 6-6 of FIG. 25; FIG.

FIG. 27 is a sectional view of the thin film transistor element TFT taken along the cut line 7-7 in FIG. 25;

FIG. 28 is a sectional view of the storage capacitor Cstg taken along a cut line 8-8 of FIG. 25; FIG.

(A) is a top view which shows the vicinity of the connection part of gate terminal GTM and gate wiring GL, and FIG. 29 (b) is sectional drawing.

FIG. 30A is a plan view showing the vicinity of a connection portion between the drain terminal DTM and the video signal line DL, and FIG. 30B is a sectional view thereof.

(A) is a top view which shows the vicinity of the connection part of common electrode terminal CTM1, common bus line CB1, and common voltage signal line CL, and FIG. 31 (b) is sectional drawing.

(A) is a top view which shows the vicinity of the connection part of common electrode terminal CTM2, common bus line CB2, and common voltage signal line CL, and FIG. 32 (b) is sectional drawing.

Fig. 33 is a circuit diagram including a matrix portion and its periphery of an active matrix type color liquid crystal display device of the present invention.

Fig. 34 shows driving waveforms of an active matrix type color liquid crystal display device of the present invention.

Fig. 35 is a flowchart of a cross sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps A to C on the substrate SUB1 side;

Fig. 36 is a flowchart of a cross sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps D to E on the substrate SUB1 side;

Fig. 37 is a flowchart of a cross sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of step F on the substrate SUB1 side;

Fig. 38 is a plan view of an essential part showing one pixel of the liquid crystal display of the active matrix type color liquid crystal display according to the eighth embodiment of the present invention and the periphery thereof.

Fig. 39 is a plan view of an essential part showing one pixel of the liquid crystal display of the active matrix type color liquid crystal display of the ninth embodiment of the present invention and its periphery;

Fig. 40 is a plan view of an essential part showing one pixel and its periphery of a liquid crystal display of the active matrix type color liquid crystal display of the tenth embodiment of the present invention.

41 (a) to 41 (d) show the principle of the present invention, and FIG. 41 (a) is a characteristic diagram showing the potential distribution in the liquid crystal layer when a voltage is applied to the electrode. ) Is a plan view showing the reorientation state of the liquid crystal molecules near the center of the liquid crystal layer, (c) of FIG. 41 is a characteristic diagram showing the rotation angle α of the liquid crystal molecules shown in (b) of FIG. 41, (d) ) Is an example of a characteristic diagram showing a transmittance distribution of light passing through a liquid crystal layer between the upper and lower polarizers, the upper and lower substrates, and the electrodes.

42A to 42C are diagrams illustrating the principles of the present invention, and FIG. 42A is a characteristic diagram showing the state of an equipotential line when a voltage is applied to a transparent electrode, and FIGS. 42B and 42C are liquid crystal molecules in a liquid crystal layer when an electric field is applied. An example of the figure which shows the rotation angle (alpha) and the tilt (elevation) angle of the lens.

43A to 43D illustrate the principle of improvement of the aperture ratio of the active matrix type color liquid crystal display device according to the eleventh embodiment of the present invention, and FIG. 43A illustrates the application of a voltage to an electrode. 43 (b) is a plan view showing a rearrangement state of liquid crystal molecules near the center of the liquid crystal layer, and FIG. 43 (c) is shown in FIG. 43 (b). 43 (d) is an example of the characteristic diagram which showed the distribution of the light transmittance which permeate | transmits the liquid crystal layer between an up-and-down polarizing plate, an up-and-down board | substrate, an electrode top, and an electrode.

44 is an example of the characteristic diagram of the simulation result which shows the viewing angle range which contrast ratio becomes 10 or more in the tilt angle and full orientation of the liquid crystal molecule in a liquid crystal layer in a transverse electric field system.

SUMMARY OF THE INVENTION The present invention solves the above problems, and an object of the present invention is to provide an active matrix liquid crystal display device using the latter display method capable of realizing a viewing angle such as a CRT. It is to provide an active matrix liquid crystal display device which is easy to see with low reflection.

In order to achieve the above object, in the present invention, at least one of the pixel electrode or the counter electrode is a transparent electrode, and is normally black mode in which dark display is performed when no electric field is applied. The initial alignment state of the twistable liquid crystal layer is a homogeneous orientation state, and liquid crystal molecules on and between the electrodes when the electric field is applied are dominantly rotated substantially parallel to the substrate surface, and the light transmittance of the liquid crystal display panel The maximum value is 4.0% or more, and the viewing angle range of the contrast ratio of 10: 1 or more is within the range of an omnidirectional inclination of 40 ° or more from the vertical direction with respect to the display surface.

As a 2nd structure, at least one of a pixel electrode or a counter electrode is a transparent electrode, it is set as the normally black mode which shows a dark display when an electric field is not applied, and the initial orientation state of the twistable liquid crystal layer when an electric field is not applied is a homogeneous orientation state. And a twist elastic modulus is 10 × 10 ⁻² N (Newtons) or less.

As a third configuration, at least one of the pixel electrode or the counter electrode is a transparent electrode, the normal black mode for dark display when no electric field is applied, and the initial alignment state of the twistable liquid crystal layer when no electric field is applied is the homogeneous alignment state. The initial pretilt angle of the liquid crystal molecules at the upper and lower interfaces of the liquid crystal layer is 10 ° or less, and the initial tilt state of the liquid crystal molecules in the liquid crystal layer is a splay state.

As a fourth configuration, at least one of the pixel electrode or the counter electrode is a transparent electrode, the normal black mode in which dark display is performed when no electric field is applied, and the initial alignment state of the twistable liquid crystal layer when no electric field is applied is the homogeneous alignment state. The average tilt angle of the liquid crystal molecules of the liquid crystal layer on the transparent electrode is less than 45 ° even when an electric field is applied.

As the fifth configuration, in any of the first to fourth configurations, at least, a double structure of a transparent electrode and an opaque metal electrode is used for the pixel electrode or the counter electrode.

As a sixth configuration, in any of the first to fourth configurations, a structure in which adjacent opposing voltage signal lines are connected through a through hole by an opposing electrode in a pixel is used.

As a seventh structure, in any one of 1st-4th structure, it has a protective film which coat | covers an active matrix element further, and at least one of the said pixel electrode or the said counter electrode is formed on the said protective film, and is formed in the said protective film It is characterized in that it is electrically connected with an active matrix element or a counter voltage signal line through a through hole.

As an eighth structure, in any one of the first to fourth embodiments, a structure in which the counter electrode is made of a transparent electrode and has a light shielding pattern between the counter electrode and the image signal line is used.

As a 9th structure, in any one of 1st-5th structure, the counter voltage signal line which electrically connects between counter electrodes is a metal.

As a tenth configuration, in any one of the first to fourth configurations, three or more opposing electrodes are formed, two of the opposing electrodes are formed adjacent to the video signal line, and the opposing electrodes formed adjacent to the video signal line are Opaque

As an 11th structure, in any one of 1st-4th structure, the transparent conductive film used for a transparent electrode is indium tin oxide (ITO).

As a twelfth configuration, in the ninth configuration, the counter voltage signal line is Cr, Ta, Ti, Mo, W, Al or an alloy thereof, or a clad structure in which these are stacked.

As a thirteenth aspect, in a ninth aspect, the counter voltage signal line is a clad structure in which a transparent conductive film such as indium tin oxide (ITO) is laminated on Cr, Ta, Ti, Mo, W, Al, or an alloy thereof. .

As a fourteenth configuration, in any one of the first to fourth configurations, the initial twist angle of the liquid crystal layer is almost zero, and the initial orientation angle is 45 ° or more and less than 90 ° if the dielectric anisotropy Δε of the liquid crystal material is positive. When the dielectric anisotropy Δε is minus, it is characterized by being over 45 ° and below 45 °.

As the first manufacturing method, at least one of the conductive layer on the uppermost layer of the scan signal line terminal portion, the video signal line terminal portion, or the counter electrode terminal portion, and at least one of the pixel electrode or the counter electrode is formed of a transparent conductive layer and is formed in the same process. Characterized in that.

The operation of the present invention is shown below.

First, when the electrode is opaque because at least one of the pixel electrode or the counter electrode is made transparent as a function of the first configuration, the maximum transmittance at the time of displaying light (white) is improved by the transmitted light of the portion. Furthermore, brighter display can be performed, and the maximum transmittance value can be achieved 4.0% or more in the present invention from 3.0 to 3.8% in the case of adopting the opaque electrode of the latter conventional method. That is, when the luminance of the backlight incident light is 3000 cd / m 2, the maximum luminance value of the bright display luminance can achieve 120 cd / m 2 or more.

In addition, when no voltage is applied, the liquid crystal molecules maintain the initial homogeneous alignment state. Therefore, when the polarizing plate is configured so as to display dark (black) display in that state (normally black mode), the electrode is made transparent. In addition, since the light of the portion does not transmit, high-quality dark display can be performed and contrast is improved.

On the other hand, in the normally white mode, dark display must be performed when voltage is applied, and when the voltage is applied, the light on the electrode cannot completely block light, so the transmitted light of the portion increases the transmittance of the dark display, thereby improving the quality of the dark display. Can not be displayed. Therefore, sufficient contrast ratio cannot be achieved.

Further, since the liquid crystal molecules on the electrodes and on the electrodes rotate dominantly in parallel with the substrate surface at the time of electric field application, a wide viewing angle characteristic is obtained.

Therefore, a wide viewing angle characteristic can be obtained within the range of the omnidirectional range in which the contrast ratio of 10: 1 or more is inclined by 40 ° or more in the vertical direction with respect to the display surface.

In addition, as a function of the second configuration, when a voltage is applied between the pixel electrode and the counter electrode, since the twist elastic modulus of the twistable liquid crystal layer is 10 × 10 ^-12 N (Newtons) or less, on the electrode of the transparent conductive film, The angle α that rotates from the initial orientation direction increases, and the transmittance on the electrode works complementarily with the transmittance between the electrodes, thereby substantially improving the aperture ratio. It is preferable that this twist elastic modulus K2 is smaller.

In addition, since the initial pretilt angle of the liquid crystal molecules at the upper and lower interfaces of the liquid crystal layer is 10 ° or less, and the initial tilt state of the liquid crystal molecules in the liquid crystal layer is a splay state as a function of the third configuration, the liquid crystal molecules at the center portion of the liquid crystal layer Since the tilt angle of becomes almost 0 ° and the average tilt angle of the liquid crystal layer contributing to the display can be lowered, the tilt angle of the liquid crystal molecules between the electrodes and on the transparent electrode can be set low even when voltage is applied. Improving the aperture ratio and wide viewing angle can be realized.

In addition, as an operation of the fourth configuration, the average tilt angle of the liquid crystal molecules of the liquid crystal layer on the transparent electrode is less than 45 ° even when the electric field is applied, so that the aperture ratio improvement and the wide viewing angle can be realized.

In addition, as a function of the fifth configuration, by using a double structure of a transparent electrode and an opaque metal electrode as the pixel electrode or the counter electrode, disconnection failure of this electrode can be largely prevented, which is advantageous for large screens.

In addition, as a function of the sixth configuration, the resistance of the opposing voltage signal line is reduced because each opposing voltage signal line is electrically connected in a mesh shape by using a structure in which adjacent opposing voltage signal lines are connected through the through holes by opposing electrodes in the pixel. Can be reduced, and even if a disconnection defect occurs, it does not become a major defect.

In addition, as an operation of the seventh configuration, it is suppressed that the electric field acting on the liquid crystal molecules is reduced by the protective film, and the driving voltage can be reduced.

In addition, as an operation of the eighth configuration, the aperture ratio is improved by using a structure in which the counter electrode is made of a transparent electrode and has a light shielding pattern between the counter electrode and the video signal line.

In addition, as a function of the ninth configuration, the crosstalk in the horizontal direction can be suppressed by reducing the resistance of the counter voltage signal line to facilitate voltage transfer between the counter electrodes and reducing the distortion of the voltage.

Further, as a function of the tenth configuration, by making the opposing electrode adjacent to the video signal line opaque, crosstalk in accordance with the video signal is suppressed. The reason is as follows.

By forming the transparent counter electrode adjacent to the video signal line, the electric field (electric force line) from the video signal line is absorbed by the counter electrode, and since the electric field from the video signal line does not affect the electric field between the pixel electrode and the counter electrode, The occurrence of crosstalk, in particular crosstalk in the vertical direction of the substrate, is significantly suppressed. However, the behavior of liquid crystal molecules on the opposite electrode adjacent to the video signal line is unstable due to the variation of the video signal, and when the opposite electrode adjacent to the video signal line is made transparent, crosstalk is observed by the transmitted light of the electrode portion. Therefore, by making the opposing electrode adjacent to the video signal line opaque, crosstalk due to the video signal can be suppressed.

In addition, as a function of the eleventh constitution, the transparent conductive film is indium-tin-oxide (ITO), and is suitable for improving transmittance.

In addition, as a function of the twelfth and thirteenth constitutions, since the counter voltage signal lines have a laminated clad structure, the resistance value can be reduced, and disconnection failure can be reduced.

In addition, as an operation of the fourteenth constitution, the initial twist angle of the liquid crystal layer is almost 0, and the initial orientation angle is 0 ° if the dielectric anisotropy Δε of the liquid crystal material is positive, but 45 ° or more and less than 90 °, and the dielectric anisotropy Δε is negative. Since it is 45 degrees or less beyond this, contrast can be improved by suppressing a domain and optimizing the range of the maximum applied voltage, and also the response speed can be optimized.

In addition, as a function of the first manufacturing method, by simultaneously forming the transparent conductive layer of the uppermost layer of the scan signal line terminal portion, the video signal line terminal portion, or the counter electrode terminal portion and the transparent electrode or the conductive electrode of the pixel electrode or the counter electrode, the pixel electrode is not increased. And the counter electrode can be formed of a transparent conductive film.

In the liquid crystal display of the present invention, at least one of the pixel electrode and the counter electrode is composed of a transparent conductive film. For example, Richard A. Soref, Proceedings of the IEEE, December 1974, 1710-1711. The configuration of the liquid crystal display element described on the page (hereinafter referred to as Document 1) differs in the following points.

In Document 1, the comb-tooth shaped electrodes corresponding to a pixel electrode and a counter electrode are comprised with the transparent conductive film.

However, when forming the initial alignment state of the liquid crystal molecules, SiO (silicon monooxide) is deposited on all sides at about 85 degrees, and at the interface between each electrode and the liquid crystal layer, a very high pretilt angle is deliberately formed on the liquid crystal molecules. have. For this reason, as shown in FIG. 1 (b) of Document 1, a voltage is applied between the comb-shaped electrodes from a homogeneous orientation twisted by 90 ° in the initial alignment state, so that the electrodes are placed on the substrate surface as a reoriented state. An approximately parallel homogeneous orientation state and a homeotropic orientation state above the electrode are perpendicular to the substrate plane.

In this configuration, however, as the electric field is increased, the reorientation state of the two kinds of liquid crystal molecules works complementarily to enable brighter display, but the tilt angle of the liquid crystal molecules needs to be increased on average. There was a drawback that the viewing angle characteristics were narrowed.

On the other hand, in the liquid crystal display device of the transverse electric field system of the present invention, since a wide viewing angle characteristic and a good aperture ratio are obtained, even when a voltage is applied between the pixel electrode and the counter electrode, the liquid crystal molecules contribute to the display image. The reorientation portion maintains the homogeneous alignment state as parallel to the substrate surface as possible, and on the electrode of the transparent conductive film, the transmittance on the electrode corresponds to the transmittance between the electrodes corresponding to the angle α rotated from the initial alignment direction, It is set as the structure which improves an aperture ratio substantially.

In addition, in this specification, the homogeneous orientation state is a state where the liquid crystal molecules in a liquid crystal layer have the tilt (elevation) angle parallel to the interface of a board | substrate surface or a liquid crystal layer as much as possible, More specifically, The tilt angle from the interface is in an orientation state of less than 45 °. Therefore, a homeotropic alignment state shall be a case where the tilt angle from the interface of a board | substrate surface or a liquid crystal layer exceeds 45 degrees.

41A shows an example of dislocation distribution in the liquid crystal layer in the electrode configuration for generating an electric field in a direction substantially parallel to the substrate surface.

Solid lines in the figure are equipotential lines, and electric field vectors are provided in a direction perpendicular to the equipotential lines. The electric field vector E generates only the component Ey in the direction perpendicular to the substrate surface on the center of the electrode, but also generates the component Ex in the horizontal direction on the substrate surface other than the center portion. In this horizontal component, that is, the region in which the transverse electric field component Ex occurs, as shown in FIGS. 41B and 41C, the liquid crystal molecules between the electrodes rotate in the transverse electric field Ex direction from the initial alignment direction RDR. rotate by α.

On the other hand, the liquid crystal molecules on the electrode rotate under the influence of the rotation of the liquid crystal molecules between the electrodes due to the elastic field in the liquid crystal. Therefore, the transverse electric field is not applied to the liquid crystal molecules at the center on the electrode, but rotates in the same direction as the surrounding liquid crystal molecules by the elastic field. That is, the rotation angle α is large between the electrodes, decreases on the electrode, and becomes minimum on the electrode center portion.

The result of simulating this state is shown to FIG. 42A-42C. In addition, the simulation of this example is the initial homogeneous alignment state of the liquid crystal molecules, and the initial twist angle of the liquid crystal layer is almost 0, and the initial alignment angle φLC = 75 ° formed by the initial alignment direction RDR and the applied electric field Ex is set up and down of the liquid crystal layer. In the birefringence mode, the initial pretilt angle of the liquid crystal molecules in the vicinity of the interface is set to 0 °, and the transmissive axis of one polarizing plate is aligned with the initial orientation direction RDR, and the cross nicol is orthogonal to the other polarizing plate. It carried out by the structural example which displays.

The light transmittance T / T ₀ at this time is represented by the following expression (1).

Here, αeff is an angle formed between the effective optical axis and the polarization transmission axis of the liquid crystal layer. In the present example, αeff is an effective value in the liquid crystal layer thickness direction of the rotation angle α of the liquid crystal molecules, and can be treated as an average value when assuming the same rotation. Apparent value.

Deff represents the thickness of the effective liquid crystal layer having birefringence, Δn represents the refractive anisotropy, and λ represents the wavelength of light.

In the equation (1), at the time of the applied electric field Ex, the value of α eff increases with the intensity, and becomes maximum when the angle is 45 °.

In the simulation of the present example, the retardation Δn · deff of the liquid crystal layer is selected to be 1/2 of the wavelength λ of light to realize the birefringence zero-order mode, and the dielectric anisotropy Δε is set to positive.

Fig. 42A is a characteristic diagram showing the state of an equipotential line when a voltage having a bright display near the maximum is applied to a transparent ITO electrode, the thickness of the liquid crystal layer (4.0 mu m) on the vertical axis, and the relative position of the electrode on the horizontal axis. Represents a relationship. In addition, the numerical value in a figure shows normalized dislocation intensity | strength.

42B and 42C show the rotation angle α and the tilt (rising) angle of the liquid crystal molecules in the liquid crystal layer when the transverse electric field component Ex formed from the state of the equipotential lines is applied.

As shown in Fig. 42C, even when a voltage is applied, the liquid crystal molecules on the electrode hardly rise, and in this example, the tilt angle is 8 degrees or less in all the thickness directions of the liquid crystal layer, and as shown in Fig. 42B. Similarly, the liquid crystal molecules on the electrode also rotate about 15 to 35 degrees near the center of the liquid crystal layer.

In addition, the code | symbol of the tilt angle shown in FIG. 42C has made the right rise positive and the left rise negative for convenience. Therefore, in the method of this invention, the rotation angle (alpha) of a liquid crystal molecule also changes on an electrode, and can change a transmittance | permeability.

The twist elastic modulus K2 of the liquid crystal is most relevant to this operation, and the smaller the twist elastic modulus K2 is, the smaller the smaller the liquid crystal molecules on the electrodes are affected by the liquid crystal molecules between the electrodes. Rotate to approach the angle of rotation α of the molecule.

In FIG. 41 (d), the distribution of the transmittance | permeability between electrodes and an electrode in the case where twist elasticity coefficient K2 is set to about 10x10 <^-2> N (Newton) is shown typically.

When the electrode is transparent, 5 to 30% of the average transmittance of the transmittance of the A portion between the electrodes becomes the average transmittance of the transmittance of the B portion on the electrode by the reorientation operation of the liquid crystal molecules on the electrode described above.

In addition, as will be described later, when the twist modulus of elasticity K2 is set to 2.0 × 10 ⁻¹² N (Newton) or less, 50% or more of the average transmittance of the transmittance of the A portion between the electrodes is the average value of the transmittance of the B portion on the electrode. It turned out that it becomes a transmittance | permeability. Therefore, the average transmittance of all the parts becomes the average value transmittance of the transmittance of the A + B part and increases.

That is, the aperture ratio per pixel can be substantially improved as compared with the conventional metal layer that does not completely transmit light.

In the simulation of this example, the initial pretilt angle is calculated by setting it to 0 °, but in practice, the initial pretilt angle near the interface with the alignment film of the liquid crystal layer is about 10 ° or less, preferably 6 ° or less in the rubbing treatment. It is necessary to set. In addition, in the Example mentioned later, it sets to about 5 degrees.

By setting the initial pretilt angle in this range, the liquid crystal molecules at the interface of the liquid crystal layer can be regulated in the in-plane direction, and the average tilt angle of the liquid crystal layer on the electrode can be kept less than 45 ° even when an electric field is applied. That is, even when an electric field is applied, the liquid crystal on the electrode can be prevented from becoming a so-called homeotropic alignment.

44 is an example of the characteristic diagram of the simulation result which showed the tilt angle of the liquid crystal molecule in a liquid crystal layer, and the viewing angle range whose contrast ratio becomes 10 or more in full orientation in a transverse electric field system liquid crystal display device.

That is, when the tilt angle is about 30 °, the contrast ratio becomes 10 or more in all directions within the viewing angle range inclined about 40 ° from the vertical direction with respect to the display surface, thereby obtaining characteristics almost equivalent to those of the conventional conventional liquid crystal display device. Lose. In addition, as the tilt angle is reduced, the viewing angle range is enlarged, and when the angle is about 10 °, the viewing angle range is expanded to within about 80 ° inclined viewing angle range.

In this embodiment, since the average tilt angle of the liquid crystal molecules in the liquid crystal layer on the transparent electrode and between the electrodes when no electric field is applied and when the electric field is applied is always reduced, the rubbing directions of the alignment films ORI1 and ORI2 described later are two substrates SUB1 and SUB2. The initial alignment state is set so that the initial pretilt angle of the liquid crystal molecules at the interface of the liquid crystal layer on the side becomes the splay state, so that the liquid crystal molecules near the center of the liquid crystal layer are as parallel with the interface as possible.

The invention, another object of the invention and still further features of the invention will become apparent from the following description with reference to the drawings.

(Example 1)

<< active matrix liquid crystal display >>

Hereinafter, the Example which applied this invention to the color matrix liquid crystal display device of an active matrix system is demonstrated. In addition, in the drawing demonstrated below, the thing with the same function attaches | subjects the same code | symbol, and the repeated description is abbreviate | omitted.

<< flat structure of matrix part (pixel part) >>

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing one pixel and its periphery of an active matrix system color liquid crystal display device of the present invention. (The diagonal portion in the drawing represents the transparent conductive film g2.)

As shown in Fig. 1, each pixel includes a scan signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode wiring) CL, and two adjacent video signal lines (drain signal line or vertical signal line) DL. It is arrange | positioned in the intersection area | region (in the area | region enclosed by four signal lines). Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode CT. In the figure, the scanning signal lines GL and the counter voltage signal lines CL extend in the left and right directions and are arranged in plural in the vertical direction. The video signal lines DL extend in the vertical direction and are arranged in plural in the left and right directions. The pixel electrode PX is connected to the thin film transistor TFT via the source electrode SD1, and the counter electrode CT is integrated with the counter voltage signal line CL.

In two pixels that are adjacent to each other vertically along the video signal line DL, the planar configuration is overlapped when bent by the A line in FIG. This is to reduce the resistance of the counter voltage signal line CL by making the counter voltage signal line CL common to two pixels vertically adjacent to each other along the video signal line DL, and expanding the electrode width of the counter voltage signal line CL. Thereby, it becomes easy to supply a sufficient counter voltage from the external circuit to the counter electrode CT of each pixel in the left-right direction.

The pixel electrode PX and the counter electrode CT face each other, and the optical state of the liquid crystal LC is controlled by the electric field between each pixel electrode PX and the counter electrode CT, and the display is controlled. The pixel electrode PX and the counter electrode CT are comprised in the comb-tooth shape, respectively, and are long and thin electrodes in the up-down direction of a figure.

The number O (comb teeth) of the counter electrode CT in one pixel is configured such that the number (comb teeth) P of the pixel electrode PX has a relationship of O = P + 1 (O = in this embodiment). 3, P = 2). This is because the counter electrode CT and the pixel electrode PX are alternately arranged, and the counter electrode CT is necessarily adjacent to the video signal line DL. Accordingly, the electric field lines from the video signal line DL can be shielded at the counter electrode CT so that the electric field between the counter electrode CT and the pixel electrode PX is not affected by the electric field generated from the video signal line DL. Since the counter electrode CT is always supplied with the potential from the outside by the counter voltage signal line CL described later, the potential is stable. Therefore, even when adjacent to the video signal line DL, there is little variation in potential. In addition, since the geometric position from the video signal line DL of the pixel electrode PX becomes far, the parasitic capacitance between the pixel electrode PX and the video signal line DL is greatly reduced, and the fluctuation caused by the video signal voltage of the pixel electrode potential Vs is also suppressed. can do. As a result, crosstalk (poor image quality called vertical smear) generated in the vertical direction can be suppressed.

The electrode width of the pixel electrode PX and the counter electrode CT is 6 micrometers, respectively. In order to apply a sufficient electric field to the whole liquid crystal layer with respect to the thickness direction of a liquid crystal layer, this is set as much larger than 3.9 micrometers in thickness of the liquid crystal layer mentioned later, and as thin as possible in order to enlarge an aperture ratio. In addition, in order to prevent disconnection, the electrode width of the video signal line DL is set to 8 m slightly wider than the pixel electrode PX and the counter electrode CT. Here, the electrode width of the video signal line DL is set to be equal to or less than twice the electrode width of the adjacent counter electrode CT. Alternatively, when the electrode width of the video signal line DL is determined from the productivity of the yield, the electrode width of the counter electrode CT adjacent to the video signal line DL is set to 1/2 or more of the electrode width of the video signal line DL. This is for absorbing the electric force lines generated from the video signal lines DL at opposite electrode CTs on both sides, and in order to absorb the electric force lines generated from a certain electrode width, an electrode having an electrode width equal to or larger than that is required. Accordingly, since the opposite electrode CTs on both sides need to absorb the electric force lines generated from half of the electrodes of the video signal line DL (by 4 m each), the electrode width of the opposite electrode CT adjacent to the video signal line DL is made 1/2 or more. . This prevents crosstalk, especially in the vertical direction (vertical direction), in which crosstalk occurs due to the influence of the video signal.

The scan signal line GL sets the electrode width so as to satisfy the resistance value as long as the scan voltage is sufficiently applied to the gate electrode GT of the pixel on the end side (the opposite side of the scan electrode terminal GTM described later). In addition, the electrode width is set so that the opposite voltage signal line CL also satisfies the resistance enough to apply the opposite voltage to the opposite electrode CT of the pixel on the end side (the opposite side of the common bus line CB described later).

On the other hand, the electrode gap between the pixel electrode PX and the counter electrode CT changes depending on the liquid crystal material used. Since the electric field strength which achieves the maximum transmittance | permeability differs by a liquid crystal material, this is set in the range of the maximum amplitude of the signal voltage set to the breakdown voltage of the video signal drive circuit (signal driver) used by setting an electrode space | interval according to a liquid crystal material. This is because the maximum transmittance is obtained. When the liquid crystal material described later is used, the electrode interval is 16 µm.

<< cross-sectional structure of the matrix part (pixel part) >>

2 is a cross-sectional view taken along line 3-3 of FIG. 1, FIG. 3 is a cross-sectional view of a thin film transistor TFT taken along line 4-4 of FIG. 1, and FIG. 4 is taken along line 5-5 of FIG. 1. It is a figure which shows the cross section of accumulation capacitance Cstg. 2 to 4, a thin film transistor TFT, a storage capacitor Cstg, and an electrode group are formed on the lower transparent glass substrate SUB1 side based on the liquid crystal layer LC, and the color filter FIL and light shielding are formed on the upper transparent glass substrate SUB2 side. The black matrix pattern BM is formed.

Moreover, the orientation films ORI1 and ORI2 which control the initial orientation of a liquid crystal are provided in the inner surface (liquid crystal LC side) surface of each of the transparent glass substrates SUB1, SUB2, and a polarization axis is orthogonal to the outer surface of each of the transparent glass substrates SUB1, SUB2. (Cross nicol arrangement) polarizing plate is provided.

<< TFT board >>

First, the configuration of the lower transparent glass substrate SUB1 side (TFT substrate) will be described in detail.

<< thin film transistor TFT >>

The thin film transistor TFT operates so that the channel resistance between the source and the drain becomes small when a positive bias is applied to the gate electrode GT, and the channel resistance becomes large when the bias is zero.

As shown in Fig. 3, the thin film transistor TFT is formed of a gate electrode GT, a gate insulating film GI, an i-type semiconductor layer AS made of i-type (intrinsic, intrinsic, non-doped crystalline impurity) amorphous silicon (Si), It has a pair of source electrode SD1 and the drain electrode SD2. In addition, the source and the drain are originally determined by the bias polarity therebetween. In the circuit of the liquid crystal display, since the polarity is inverted during operation, it is to be understood that the source and the drain are replaced during operation. However, in the following description, one side is represented as a source and the other side is fixed as a convenience.

<< gate electrode GT >>

The gate electrode GT is formed in succession with the scan signal line GL, and is configured such that a part of the scan signal line GL becomes the gate electrode GT. The gate electrode GT is a portion exceeding the active region of the thin film transistor TFT, and is formed larger than that so as to completely cover the i-type semiconductor layer AS. Accordingly, in addition to the role of the gate electrode GT, studies have been made so that external light and backlight light do not come into contact with the i-type semiconductor layer AS. In this example, the gate electrode GT is formed of a single layer conductive film g1. In the conductive film g1, for example, an aluminum (Al) film formed of sputtering is used, and Al anodized film AOF is provided thereon.

<Scanning signal line GL >>

The scanning signal line GL is composed of a conductive film g1. The conductive film g1 of the scan signal line GL is formed in the same manufacturing process as the conductive film g1 of the gate electrode GT, and is integrally formed. The scan signal line GL supplies the gate voltage Vg to the gate electrode GT from an external circuit. Al anodized film AOF is also provided on the scan signal line GL. In addition, the portion which intersects the video signal line DL is made thin in order to reduce the short circuit probability with the video signal line DL, and can be separated by laser trimming even if it is shorted.

Counter electrode CT

The counter electrode CT is comprised from the gate electrode GT, the scan signal line GL, and the conductive film g1 of the same layer. Further, Al anodized film AOF is provided on the counter electrode CT. The counter electrode CT is configured to apply the counter voltage Vcom. In this embodiment, the counter voltage Vcom is a feed-through voltage ΔVs generated when the thin film transistor element TFT is turned off from the intermediate DC potential of the minimum level driving voltage Vdmin and the maximum level driving voltage Vdmax applied to the video signal line DL. It is set to a potential as low as minutes, but when it is desired to reduce the power supply voltage of the integrated circuit used in the video signal driving circuit to about half, an AC voltage may be applied.

Counter voltage signal line CL

The counter voltage signal line CL is composed of a conductive film g1. The conductive film g1 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g1 of the gate electrode GT, the scan signal line GL, and the counter electrode CT, and is integrally formed with the counter electrode CT. The counter voltage signal line CL supplies the counter voltage Vcom to the counter electrode CT from an external circuit. Further, Al anodization film AOF is provided on the counter voltage signal line CL. In addition, the portion crossing the video signal line DL is made thin so as to reduce the probability of a short circuit with the video signal line DL, similarly to the scan signal line GL, and can be separated by laser trimming even if the short circuit occurs.

<< insulating film GI >>

The insulating film GI is used as a gate insulating film for providing an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI is formed over the gate electrode GT and the scan signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected, and is formed to a thickness of 1200 to 2700 GPa (about 2400 GPa in this embodiment). The gate insulating film GI is formed so as to surround the whole of the matrix portion AR, and the peripheral portion is removed to expose the external connection terminals DTM and GTM. The insulating film GI also contributes to the electrical isolation of the scan signal line GL, the counter voltage signal line CL, and the video signal line DL.

I-type semiconductor layer AS

The i-type semiconductor layer AS is amorphous silicon and is formed to a thickness of 200 to 2200 GPa (film thickness of about 2000 GPa in this embodiment). The layer d0 is an N (+) type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, and is left only in a portion where the i type semiconductor layer AS is present on the lower side and the conductive layer d1 (d2) is present on the upper side. have.

The i-type semiconductor layer AS is also provided between both the scan signal line GL and the intersection portion (crossover portion) between the counter voltage signal line CL and the video signal line DL. The i-type semiconductor layer AS at this intersection reduces the short circuit between the scan signal line GL and the counter voltage signal line CL and the video signal line DL at the intersection.

<< source electrode SD1, drain electrode SD2 >>

Each of the source electrode SD1 and the drain electrode SD2 is composed of a conductive film d1 in contact with the N (+) type semiconductor layer d0 and a conductive film d2 formed thereon.

The conductive film d1 is formed to have a thickness of 500 to 1000 GPa (about 600 GPa in this embodiment) using a chromium (Cr) film formed of sputtering. If the Cr film is formed thick, the stress increases, so that the Cr film is formed in a range not exceeding the film thickness of about 2000 GPa. The Cr film is used for the purpose of improving adhesion to the N (+) type semiconductor layer d0 and preventing Al of the conductive film d2 from diffusing into the N (+) type semiconductor layer d0 (of the so-called barrier layer). In addition to the Cr film, a high melting point metal (Mo, Ti, Ta, W) film and a high melting point metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used as the conductive film d1.

The conductive film d2 is formed to have a thickness of 3000 to 5000 GPa (about 4000 GPa in this embodiment) by sputtering of Al. The Al film is less stressed than the Cr film, and can be formed at a thick film thickness, and the resistance value of the source electrode SD1, the drain electrode SD2, and the video signal line DL is reduced, or the gate electrode GT or the i-type semiconductor layer AS is caused. There is a function to ensure the overcoming of the (step coverage).

After patterning the conductive film d1 and the conductive film d2 with the same mask pattern, the N (+) type semiconductor layer d0 is removed using the same mask or using the conductive film d1 and the conductive film d2 as a mask. That is, in the N (+) type semiconductor layer d0 remaining on the i-type semiconductor layer AS, portions other than the conductive film d1 and the conductive film d2 are self-aligned. At this time, since the N (+) type semiconductor layer d0 is etched so as to be removed as much as the thickness thereof, the surface portion of the i type semiconductor layer AS is also etched slightly, but the extent may be controlled by the etching time.

<< video signal line DL >>

The video signal line DL is composed of the source electrode SD1, the drain electrode SD2, and the second conductive film d2 and the third conductive film d3 in the same layer. The video signal line DL is formed integrally with the drain electrode SD2.

<< pixel electrode PX >>

The pixel electrode PX is formed of the transparent conductive layer g2. This transparent conductive film g2 is made of a transparent conductive film (Indium-Tin-Oxide ITO: nesa film) formed by sputtering, and is formed to a thickness of 100 to 2000 GPa (film thickness of about 1400 GPa in this embodiment).

Since the pixel electrode becomes transparent as in the present embodiment, the maximum transmittance at the time of performing the white display is improved by the transmitted light of the portion, so that brighter display can be performed than when the pixel electrode is opaque. At this time, as will be described later, when no voltage is applied, the liquid crystal molecules maintain the initial alignment state, and the arrangement of the polarizing plates is configured (to be normally black mode) so as to display black in that state. Even if it is transparent, black of high quality can be displayed, without permeating the light of the part. As a result, the maximum transmittance is improved, and a more sufficient contrast ratio can be achieved.

`` Accumulation capacity Cstg ''

The pixel electrode PX is formed so as to overlap the counter voltage signal line CL at the end opposite to the end connected to the thin film transistor TFT. As can be seen from FIG. 4, this superposition constitutes a storage capacitor (capacitive element) Cstg in which the pixel electrode PX is one electrode PL2 and the opposing voltage signal CL is the other electrode PL1. The dielectric film of the storage capacitor Cstg is composed of an insulating film GI and an anodic oxide film AOF used as the gate insulating film of the thin film transistor TFT.

As shown in Fig. 1, the storage capacitor Cstg is formed in a portion where the width of the conductive film g1 of the counter voltage signal line CL is widened.

Shield PSV1

The protective film PSV1 is provided on the thin film transistor TFT. The protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like, and uses a high transparency and a good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and is formed with a film thickness of about 1 μm.

The protective film PSV1 is formed to surround the whole of the matrix portion AR, and the peripheral portion is removed to expose the external connection terminals DTM and GTM. For the thickness relationship between the protective film PSV1 and the gate insulating film GI, the former is made thick in consideration of the protective effect, and the latter is made thin in consideration of the mutual conductance gm of the transistor. Therefore, the protective film PSV1 having a high protective effect is formed larger than the gate insulating film GI so as to protect over a wide range as much as possible in the peripheral portion.

<< color filter board >>

1 and 2, the configuration of the upper transparent glass substrate SUB2 side (color filter substrate) will be described in detail.

<< shading film BM >>

On the upper transparent glass substrate SUB2 side, transmitted light from an unnecessary gap portion (gap other than the pixel electrode PX and the counter electrode CT) is emitted to the display surface side to form a light shielding film BM (so-called black matrix) so as not to lower the contrast ratio. Doing. The light shielding film BM also serves to prevent external light or back light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched by the light shielding film BM and the large gate electrode GT which are above and below, and external natural light or backlight light does not reach.

The outline of the polygon in which the light shielding film BM shown in FIG. 1 is closed has shown the opening inside which the light shielding film BM is not formed. This outline pattern is an example, and when opening part is enlarged more, it can also be set as the light-shielding film BM1 of the dotted line of FIG. Although the enlarged region in Fig. 1 is disturbed in the electric field direction, the display of the portion corresponds one-to-one to the video information in the pixel, and in the case of black, it becomes white in the case of black and white, so that it can be used as part of the display. Do. In addition, when the boundary line of the up-down direction of a figure is determined by the alignment precision of an up-and-down board | substrate, and the alignment precision is better than the electrode width of the counter electrode CT adjacent to the video signal line DL, when it sets between the widths of a counter electrode, The opening can be enlarged.

The light shielding film BM has a shielding property against light and is formed of a highly insulating film so as not to affect the electric field between the pixel electrode PX and the counter electrode CT. In this embodiment, black pigment is incorporated into the resist material, and 1.2 It is formed to a thickness of about 탆.

The light shielding film BM is formed in a lattice shape around each pixel, and one pixel effective display area is partitioned. Therefore, the outline of each pixel is made clear by the light shielding film BM. That is, the light shielding film BM has two functions of light shielding for the black matrix and the i-type semiconductor layer AS.

The light shielding film BM is formed in the peripheral part also in a frame shape, and the pattern is formed continuously with the pattern of the matrix part shown in FIG. 1 which provided the some opening in dot shape. The light shielding film BM in the peripheral portion extends outside the sealing portion SL and prevents leakage light such as reflected light resulting from a mounting machine such as a personal computer from entering the matrix portion. On the other hand, this light shielding film BM is about 0.3-1.0 mm inside from the edge of the board | substrate SUB2, and is formed avoiding the cutting | disconnection area | region of the board | substrate SUB2.

<< color filter FIL >>

The color filter FIL is formed in a stripe shape by repetition of red, green, and blue at positions facing the pixels. The color filter FIL is formed so that it may overlap with the edge part of the light shielding film BM.

The color filter FIL can be formed as follows. First, dyeing base materials, such as an acrylic resin, are formed on the surface of upper transparent glass substrate SUB2, and dyeing base materials other than a red filter formation area are removed by photolithography technique. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Subsequently, green filter G and blue filter B are formed one by one by performing the same process.

<< overcoat film OC >>

The overcoat film OC is provided for the prevention of the leakage of the dye of the color filter FIL to the liquid crystal LC, and the planarization of the step by the color filter FIL and the light shielding film BM. The overcoat film OC is formed of transparent resin materials, such as an acrylic resin and an epoxy resin, for example.

`` Liquid crystal layer and deflection plate ''

Next, a liquid crystal layer, an alignment film, a polarizing plate, etc. are demonstrated.

<< liquid crystal layer >>

As liquid crystal material LC, the nematic liquid crystal whose dielectric anisotropy (DELTA) epsilon is positive, whose value is 13.2 and refractive index anisotropy (DELTA) n is 0.081 (589 nm, 20 degreeC) is used. The thickness (gap) of the liquid crystal layer is 3.9 µm, and the retardation Δn · d is 0.316. Depending on the value of this retardation Δn · d, the maximum transmittance can be obtained when the liquid crystal molecules rotate 45 ° from the rubbing direction to the electric field direction in combination with the alignment film and polarizing plate described later, and the wavelength dependence is almost within the range of visible light. No transmitted light can be obtained. The thickness (gap) of the liquid crystal layer is controlled by polymer beads.

The liquid crystal material LC is not particularly limited, and the dielectric anisotropy Δε may be negative. In addition, the larger the value of the dielectric anisotropy Δε can reduce the driving voltage. Further, the smaller the refractive anisotropy Δn can make the thickness (gap) of the liquid crystal layer thicker, the liquid crystal sealing time can be shorter, and the gap variation can be reduced.

In addition, when the relationship between the material material of the liquid crystal material and the transmitted light intensity at the counter electrode portion or the pixel electrode portion of the transparent conductive film was examined, it was found that it largely depends on the twist elastic modulus K2 of the liquid crystal material. This is because attenuation at the upper part of the electrode of the transparent conductive film of the in-plane twist deformation caused by the transverse electric field causing light transmission in the openings between the electrodes is caused by an inherent curvature according to the twist elastic modulus K2 of the liquid crystal material. Therefore, in order to make the light transmission at the electrode part of a transparent conductive film larger, and to improve the brightness | luminance of the whole opening part containing the electrode of this transparent conductive film, the said damping curvature is made small using the liquid crystal material with a small twist elasticity modulus K2. Just do it. The effect of the twist elastic modulus K2 is further described in Example 11.

In Example 1, 5.1x10 <^-12> N (Newton) is used at room temperature as twist elastic modulus K2.

In addition, the measuring method of the twist elastic modulus K2 is described, for example in the literature by Oka Ogashi, Co., Ltd. of liquid crystal and a base piece, p216-220 (培 風 館, 1985), and measures the threshold voltage of a twisted liquid crystal cell. It can be obtained from

<< alignment film >>

As the alignment film ORI, polyimide is used. The rubbing direction is parallel to each other in the upper and lower substrates, and the initial orientation angle φ LC formed by the initial orientation direction RDR and the applied electric field direction EDR (Ex) is set to 75 °. The relationship is shown in FIG.

The initial orientation angle φ LC formed between the initial orientation direction RDR and the applied electric field direction EDR is not less than 45 ° and less than 90 ° when the dielectric anisotropy Δε of the liquid crystal material is positive, and exceeds 0 ° and not less than 45 ° when the dielectric anisotropy Δε is negative. Can not be done.

In addition, in this embodiment, by making the rubbing directions parallel to each other in the alignment films ORI1 and ORI2, the initial pretilt angle of the liquid crystal molecules at the upper and lower interfaces of the liquid crystal layer contributing to the display between the electrodes and on the electrodes becomes a splay state, and the liquid crystal molecules Has the effect of compensating for mutual optical characteristics, thereby obtaining a wide viewing angle characteristic.

Further, by making the rubbing direction antiparallel with the alignment films ORI1 and ORI2, the pretilt angle of the liquid crystal molecules at the upper and lower interfaces of the liquid crystal layer is in a parallel state, and the tilt angle in the average liquid crystal layer is further increased. By setting the pretilt angle, the same effects of the present invention are obtained.

<< polarizing plate >>

As polarizing plate POL, polarizing transmission axis MAX1 of lower polarizing plate POL1 is matched with rubbing direction RDR, and polarizing transmission axis MAX2 of upper deflection plate POL2 is orthogonal to it using G1220DU by Mitsui Denki Co., Ltd. product. The relationship is shown in FIG. Accordingly, by increasing the voltage (voltage between the pixel electrode PX and the counter electrode CT) applied to the pixel of the present invention, a normally closed characteristic of increasing transmittance can be obtained, and high-quality black display when no voltage is applied. You can do

Moreover, in order to reduce the specific resistance value, the transparent conductive film is formed in one surface in polarizing plate POL2 itself in order to prevent the influence of static electricity from the exterior. This transparent conductive film may be formed between the upper substrate SUB2 and the upper polarizing plate POL2.

<< composition around the matrix >>

FIG. 5 is a diagram illustrating a main part plane around the matrix AR of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2. 6 is a cross-sectional view in the vicinity of the external connection terminal GTM to which the scanning circuit is to be connected to the left side, and a cross-sectional view in the vicinity of the sealing portion of the part without the external connection terminal on the right side.

In the manufacture of this panel, small sized glass substrates can be processed and divided into one glass substrate at the same time to improve throughput, and large sized glass substrates of any size can be used for common use of manufacturing facilities. After processing, the size is reduced to the size suitable for each variety, and in either case, the glass is cut after rough processing. 5 and 6 show the latter example, in which both of Figs. 5 and 6 show the cut-outs of the upper and lower substrates SUB1 and SUB2, and LN represents the edges before the cut-off of both substrates. In either case, in the completed state, the portion where the external connection terminal group Tg, Td and the terminal COT (subscript omitted) are present (upper side and left side in the drawing) so that the size of the upper substrate SUB2 is larger than that of the lower substrate SUB1 so as to expose them. It is restricted to the inside. The terminal groups Tg and Td are the terminals of the scanning circuit connection terminal GTM and the video signal circuit connection terminal DTM which will be described later, respectively, and their lead-out wiring units in units of the tape carrier package TCP (FIG. 16, 17) in which the integrated circuit chip CHI is mounted. It is named after combining several. The lead-out wiring from the matrix part of each group to the external connection terminal part inclines as it approaches both ends. This is to align the terminal DTM and GTM of the display panel PNL with the arrangement pitch of the package TCP and the connection terminal pitch in each package TCP. In addition, the counter electrode terminal CTM is a terminal for providing a counter voltage to the counter electrode CT from an external circuit. The counter voltage signal line CL of the matrix portion is drawn out to the opposite side of the scanning circuit terminal GTM (right side in the drawing), and the counter voltage signal lines are collectively connected to the counter electrode terminal CTM on the common bus line CB.

A sealing pattern SL is formed between the transparent glass substrates SUB1 and SUB2 so as to seal the liquid crystal LC, except for the liquid crystal sealing mouth INJ, along the edge thereof. The sealing material consists of epoxy resins, for example.

The layers of the alignment films ORI1 and ORI2 are formed inside the sealing pattern SL. Polarizing plates POL1 and POL2 are comprised in the outer surface of lower transparent glass substrate SUB1, and upper transparent glass substrate SUB2, respectively. Liquid crystal LC is sealed in the area | region partitioned by sealing pattern SL between lower alignment film ORI1 which sets the direction of a liquid crystal molecule, and upper alignment film ORI2. The lower alignment film ORI1 is formed on the upper portion of the protective film PSV1 on the lower transparent glass substrate SUB1 side.

This liquid crystal display device overlaps various layers separately on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and forms the sealing pattern SL on the substrate SUB2 side to form the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2. It superimposes, and inject | pours liquid crystal LC from the opening part INJ of sealing material SL, it is assembled by sealing an injection port INJ with an epoxy resin etc., and cut | disconnecting an upper and lower substrate.

<< gate terminal part >>

FIG. 7A is a plan view showing a connection structure from the scan signal line GL to the external connection terminal GTM of the display matrix, and FIG. 7B shows a cross section taken along the BB cutting line of FIG. have. In addition, the said figure corresponds to the vicinity of the right center of FIG. 5, and the part of inclination wiring was shown by the straight line for convenience.

AO is a boundary of photoresist direct drawing, that is, a photoresist pattern of selective anodic oxidation. Therefore, this photoresist is removed after anodizing, and the pattern AO shown in the figure does not remain as a finished product, but since the oxide film AOF is selectively formed on the gate wiring GL as shown in the cross-sectional view, the trace remains. In the plan view, on the basis of the boundary line AO of the photoresist, the left side is a region covered with resist and not anodized, and the right side is a region exposed from the resist and anodized. The oxide Al ₂ O ₃ film AOF is formed on the surface of the anodized Al layer g1 so that the volume of the lower conductive portion decreases. Of course, anodization is performed by setting an appropriate time, voltage, and the like so that the conductive portion remains.

Although the Al layer g1 is hatching in order to make it easy to understand, the area | region which is not polarized is patterned by the comb-tooth shape. This is because, when the Al layer is wide, whiskers are generated on the surface, so that the width of each sheet is narrowed and the plurality of sheets are arranged in parallel to prevent the occurrence of whiskers, while minimizing the probability of disconnection and the sacrifice of electrical conductivity. The goal is to restrain.

The gate terminal GTM is composed of an Al layer g1 and a transparent conductive layer g2 for protecting the surface and improving the reliability of the connection with a tape carrier packege (TCP). The transparent conductive film g2 is formed of a pixel electrode PX. Transparent conductive film ITO formed in the same process is used. Further, the conductive layers d1 and d2 formed on the Al layer g1 and the side portions thereof have a Cr layer having good connectivity to both the Al layer and the transparent conductive layer g2 in order to compensate for poor connection between the Al layer and the transparent conductive layer g2. It is for connecting d1 and reducing connection resistance, and since the conductive layer d2 is formed in the same mask as the conductive layer d1, it remains.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line, and the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion GTM located on the left end is exposed from these to allow electrical contact with an external circuit. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in practice, a plurality of such pairs are arranged up and down as shown in Figs. 7A and 7B, and the terminal group Tg (Fig. 5) The left end of the gate terminal extends beyond the cutting region of the substrate in the manufacturing process and is shorted by a wiring SHg (not shown). Such short-circuit SHg in the manufacturing process helps to prevent electrostatic breakdown such as power supply during anodization and rubbing of the alignment film ORI1.

`` Drain Terminal DTM ''

FIG. 8A shows a plan view showing the connection from the video signal line DL to its external connection terminal DTM, and FIG. 8B shows a cross section taken along the line B-B in FIG. 8A. In addition, the said figure corresponds to the vicinity of the upper right of FIG. 5, The direction of a figure is changed for convenience, but the right end direction corresponds to the upper end part of the board | substrate SUB1.

The TSTd is a test terminal, but no external circuit is connected thereto, but is wider than the wiring so as to be able to contact the probe needle or the like. Similarly, the drain terminal DTM is wider than the wiring portion so as to be connected to an external circuit. The external connection drain terminal DTM is arranged in the vertical direction, and the drain terminal DTM constitutes the terminal group Td (subscript omitted) as shown in FIG. 5 and further extends beyond the cutting line of the substrate SUB1, and prevents electrostatic destruction during the manufacturing process. All of them are shorted by interconnect SHd (not shown). The inspection terminal TSTd is formed in each video signal line DL as shown in Fig. 8A.

The drain connection terminal DTM is formed of a transparent conductive layer g2 single layer, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. This transparent conductive film g2 uses the transparent conductive film ITO formed in the same process as the pixel electrode PX similarly to the gate terminal GTM. The semiconductor layer AS formed on the end of the gate insulating film GI is for etching the edges of the gate insulating film GI into a tapered shape. On the drain terminal DTM, the protective film PSV1 is removed, of course, because it is connected to an external circuit.

In the lead-out wiring from the matrix portion to the drain terminal portion DTM, the layers d1 and d2 at the same level as the video signal line DL are configured up to the middle of the protective film PSV1, and are connected to the transparent conductive film g2 in the protective film PSV1. This aims to protect Al layer d2 which is easy to be electrolyzed with the protective film PSV1 and sealing pattern SL as much as possible.

Counter electrode terminal CTM

FIG. 9A is a plan view showing a connection from the opposite voltage signal line CL to its external connection terminal CTM, and FIG. 9B shows a cross section taken along the line B-B in FIG. 9A. In addition, the figure corresponds to the vicinity of the upper left side of FIG.

Each counter voltage signal line CL is collectively drawn out to the counter electrode terminal CTM in a common bus line CB. The common bus line CB has a structure in which the conductive layer d1 and the conductive layer d2 are laminated on the conductive layer g1. This is to reduce the resistance of the common bus line CB and to allow the opposing voltage to be sufficiently supplied from the external circuit to the opposing voltage signal lines CL. This structure is characterized in that the resistance of the common bus line is lowered without newly loading a conductive layer. The conductive layer g1 of the common bus line CB is not anodized so as to be electrically connected to the conductive layers d1 and d2. It is also exposed from the gate insulating film GI.

The counter electrode terminal CTM has a structure in which a transparent conductive layer g2 is laminated on the conductive layer g1. This transparent conductive film g2 uses the transparent conductive film ITO formed by the same process as the pixel electrode PX like the other terminal. In order to protect the surface by the transparent conductive layer g2, and to prevent electrical corrosion etc., the whole layer g1 is covered with the durable transparent conductive layer g2.

<< display device whole equivalent circuit >>

10 shows a wiring diagram of an equivalent circuit of the display matrix portion and its peripheral circuits. Although the figure is a circuit diagram, it is shown corresponding to the actual geometric arrangement. AR is a matrix array in which a plurality of pixels are arranged in a two-dimensional shape.

In the figure, X means the image signal line DL, and the subscripts G, B, and R are added corresponding to the green, blue, and red pixels, respectively. Y means scanning signal line GL, and subscripts 1, 2, 3,... , end is added in the order of the scanning timing.

The scan signal line Y (subscript omitted) is connected to the vertical scan circuit V, and the video signal line X (subscript omitted) is connected to the video signal drive circuit H.

SUP includes a power supply circuit for obtaining a plurality of divided voltage stabilized voltage sources from one voltage source, or a circuit for exchanging information for a CRT (cathode ray tube) from a host (higher processing unit) with information for a TFT liquid crystal display device. It is a circuit.

<< driving method >>

11 shows driving waveforms of the liquid crystal display of the present invention.

In Example 1, since the counter voltage signal line CL is formed from the electrically conductive film g1 of the low resistance metal of aluminum, the load impedance is small and the waveform distortion of the counter voltage is small. For this reason, the counter voltage can be altered and there is an advantage that the signal line voltage can be reduced.

That is, the opposing voltage is a binary AC square wave of Vch and Vcl, and the non-selection voltages of the scan signals Vg (i-1) and Vg (i) are changed to binary values of Vg1h and Vg11 every one scanning period in synchronization with it. . The amplitude value of the opposing voltage and the amplitude value of the unselected voltage are made equal. The video signal voltage is a voltage obtained by subtracting 1/2 of the amplitude of the opposite voltage from the voltage to be applied to the liquid crystal layer.

Although the counter voltage may be a direct current, the maximum amplitude of the video signal voltage can be reduced by alternating current, so that a low breakdown voltage can be used for the video signal drive circuit (signal driver). In Examples 2 and 3 described later, since the counter voltage signal line CL is formed of the transparent conductive film g2, the resistance is relatively high, and the counter voltage is preferably a direct current method.

<< function of accumulation capacity Cstg >>

The storage capacitor Cstg is provided to accumulate the video information recorded in the pixel (after the thin film transistor TFT is turned off) for a long time. In the method of applying the electric field used in the present invention in parallel with the substrate surface, unlike the method of applying the electric field perpendicular to the substrate surface, there is almost no capacitance (so-called liquid crystal capacitance) composed of the pixel electrode and the counter electrode, The storage capacitor Cstg cannot accumulate image information in the pixel. Therefore, in the method of applying an electric field in parallel with the substrate surface, the storage capacitor Cstg is an essential component.

In addition, the storage capacitor Cstg operates to reduce the influence of the gate potential change ΔVg on the pixel electrode potential Vs when the thin film transistor TFT switches. When this form is represented by an equation, it becomes as follows.

ΔVs = {Cgs / (Cgs + Cstg + Cpix)} × ΔVg

Here, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT, Cpix is a capacitance formed between the pixel electrode PX and the counter electrode CT, and ΔVs is the change of the pixel electrode potential due to ΔVg. It represents the feedthrough voltage. This change ΔVs causes the direct current component applied to the liquid crystal LC, but the value can be reduced by increasing the holding capacitor Cstg. Reduction of the DC component applied to liquid crystal LC can improve the lifetime of liquid crystal LC, and can reduce the so-called afterimage which a previous image remains at the time of switching of a liquid crystal display screen.

As described above, the gate electrode GT is large enough to completely cover the i-type semiconductor layer AS, so that the overlap area with the source electrode SD1 and the drain electrode SD2 increases, so that the parasitic capacitance Cgs becomes large and the pixel electrode potential Vs becomes the gate. An adverse effect is that the (scan) signal Vg can be easily affected. However, this disadvantage can also be eliminated by providing the storage capacitor Cstg.

<< production method >>

Next, the manufacturing method of the board | substrate SUB1 side of the liquid crystal display device mentioned above is demonstrated with reference to FIGS. In addition, in the said figure, the character of the center is abbreviation of a process name, the left side shows the flow of this process in the cross-sectional shape of the thin film transistor TFT part shown in FIG. 3, and the right side is near the gate terminal shown in FIG. Except for Step B and Step D, Steps A to I are classified corresponding to each photo process, and any cross-sectional view of each step shows the step of removing the photoresist after finishing the photo process. In addition, in this description, a photo process shows a series of operation | work from the application of photoresist to the selective exposure using a mask, and to develop it, and repeated description is avoided. Hereinafter, it demonstrates according to the process to which it classified.

Process A, FIG. 12

On the lower transparent glass substrate SUB1 made of AN635 glass (brand name), a conductive film g1 made of Al-Pd, Al-Si, Al-Ta, Al-Ti-Ta, etc. having a film thickness of 3000 kPa is provided by sputtering. After the photographic treatment, the conductive film g1 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid. Thus, the gate electrode GT, the scan signal line GL, the counter electrode CT, the counter voltage signal line CL, the electrode PL1, the gate terminal GTM, the first conductive layer of the common bus line CB, the first conductive layer of the counter electrode terminal CTM, and the gate terminal GTM An anodic oxidation bus line SHg (not shown) for connecting N and an anodization pad (not shown) connected to the anodization bus line SHg is formed.

Process B, FIG. 12

After formation of the anodization mask AO by direct drawing, the substrate SUB1 was immersed in an anodizing solution consisting of a solution obtained by diluting a solution of 3% tartaric acid to pH 6.25 ± 0.05 with ammonia 1: 1 diluted with ethylene glycol solution. Then, it adjusts so that chemical current density may be set to 0.5 mA / cm <2> (constant current chemical conversion). Next, anodization is performed until the chemical conversion voltage 125V required to obtain a predetermined Al ₂ O ₃ film thickness is reached. Then, it is preferable to hold | maintain for several tens of minutes in this state (constant voltage chemical conversion). This is important for obtaining a uniform Al ₂ O ₃ film. Thus, the conductive film g1 is anodized to form an anodized film AOF having a film thickness of 1800 kPa on the gate electrode GT, the scan signal line GL, the counter electrode CT, the counter voltage signal line CL, and the electrode PL1.

Process C, FIG. 12

Ammonia gas, silane gas, and nitrogen gas were introduced into the plasma CVD apparatus to provide a Si nitride film having a film thickness of 2200 kPa, and silane gas and hydrogen gas were introduced into the plasma CVD apparatus to form an i-type amorphous Si film having a film thickness of 2000 kPa. After the installation, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N (+) type amorphous Si film having a film thickness of 300 kPa.

Process D, FIG. 13

After the photographic processing, the islands of the i-type semiconductor layer AS are formed by selectively etching the N (+)-type amorphous Si film and the i-type amorphous Si film using SF ₆ and CCl ₄ as dry etching gases.

Process E, FIG. 13

After the photographic treatment, the Si nitride film is selectively etched using SF ₆ as a dry etching gas.

Process F, FIG. 13

The transparent conductive film g2 which consists of an ITO film whose film thickness is 1400 kPa is provided by sputtering. After the photographic treatment, the transparent conductive film g2 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as the etching solution, thereby forming the second conductive layer of the uppermost layer of the gate terminal GTM, the drain terminal DTM and the counter electrode terminal CTM.

Process G, FIG. 14

A conductive film d1 made of Cr having a film thickness of 600 kPa is provided by sputtering, and a conductive film d2 made of Al-Pd, Al-Si, Al-Ta, Al-Ti-Ta, or the like having a film thickness of 4000 kPa is used for sputtering. Install by After the photographic processing, the conductive film d2 is etched with the same liquid as in step B, and the conductive film d1 is etched with the same liquid as in step A, and the video signal line DL, the source electrode SD1, the drain electrode SD2, the pixel electrode PX, and the electrode PL2 are common. The bus line SHd (not shown) which shorts the second conductive layer, the third conductive layer and the drain terminal DTM of the bus line CB is formed. Subsequently, CCl ₄ and SF ₆ are introduced into the dry etching apparatus to etch the N (+) type amorphous Si film to selectively remove the N (+) type semiconductor layer d0 between the source and the drain.

Process H, FIG. 14

Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a Si nitride film having a film thickness of 1 m. After the photo process, the protective film PSV1 is formed by selectively etching the Si nitride film by a photolithography technique using SF ₆ as a dry etching gas.

《Display panel PNL and driving circuit board PCB1》

FIG. 15 is a top view illustrating a state in which the video signal driving circuit H and the vertical scanning circuit V are connected to the display panel PNL shown in FIG. 5 and the like.

Reference numeral CHI denotes a driving IC chip for driving the display panel PNL (the lower five are driving IC chips on the vertical scanning circuit side and the ten left ones are driving IC chips on the video signal driving circuit side). As shown in FIGS. 16 and 17, TCP is a tape carrier package in which the driving IC chip CHI is mounted by a tape automaid bonding method (TAB), and PCB1 is a driving circuit board on which the TCP or capacitor is mounted. It is divided into two, a video signal drive circuit and a scan signal drive circuit. The FGP is a frame gland pad, and spring-shaped debris cut and inserted into the shield case SHD is soldered. FC is a flat cable which electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1. As the flat cable FC, as shown in the figure, a sandwich of a plurality of lead wires (sn-plated in bronze material) with a stripe-like polyethylene layer and a polyvinyl alcohol layer is used.

<< connection structure of TCP >>

Fig. 16 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI is mounted on a flexible wiring board, which constitutes a scan signal driving circuit V or a video signal driving circuit H, and Fig. 17 shows that of a liquid crystal display panel; In this example, the main portion is a cross-sectional view showing the state connected to the terminal GTM for scanning signal circuit.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, TTM is an output terminal / wiring portion of the integrated circuit CHI, and is made of, for example, Cu, and is integrated at each inner leading end (commonly referred to as an internal lead). The bonding pad PAD of the circuit CHI is connected by the so-called facedown bonding method. The outer ends of the terminals TTB and TTM (commonly referred to as external leads) respectively correspond to the inputs and outputs of the semiconductor integrated circuit chip CHI, and the liquid crystal display is performed by the anisotropic conductive film ACF on the CRT / TFT conversion circuit and power supply circuit SUP by soldering or the like. It is connected to panel PNL. The package TCP is connected to the panel so that its front end covers the protective film PSV1 exposing the connection terminal GTM on the panel PNL side. Therefore, the external connection terminal GTM (DTM) is covered with at least one of the protective film PSV1 or the package TCP. Become strong against contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking the solder at the time of soldering so that it does not stick to an unnecessary part. The clearance gap between the upper and lower glass substrates outside the sealing pattern SL is protected by an epoxy resin EPX or the like after washing, and the silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 to multiplex the protection.

Drive Circuit Board PCB2

The driving circuit board PCB2 includes electronic components such as an IC, a capacitor, and a resistor. The driving circuit board PCB2 includes a power supply circuit for obtaining a plurality of divided voltage stabilized voltage sources from one voltage source, and information for a CRT (cathode ray tube) from a host (higher processing unit). The circuit SUP including the circuit for converting into a circuit is mounted. CJ is a connector connection part to which a connector (not shown) to be connected to the outside is connected.

The drive circuit board PCB1 and the drive circuit board PCB2 are electrically connected by the flat cable FC.

<< whole structure of liquid crystal display module >>

18 is an exploded perspective view illustrating each component of the liquid crystal display module MDL.

SHD is a metal shielded frame case (metal frame), LCW is a display window, PNL is a liquid crystal display panel, SPB is a light diffuser plate, LCB is a light guide, RM is a reflector, BL is a backlight fluorescent tube, and LCA is a backlight case Each member overlaps with each other in the up-and-down arrangement relationship as shown in the figure, and the module MDL is assembled.

The module MDL is fixed to the whole by hooks and hooks installed in the shield case SHD.

The backlight case LCA is shaped to accommodate the backlight fluorescent tube BL, the light diffuser plate SPB, the light guide LCB, and the reflector RM, and the light of the backlight fluorescent tube BL disposed on the side of the light guide LCB is used as the light guide LCB and the reflector RM. The light diffusion plate SPB sets the same backlight on the display surface and exits to the liquid crystal display panel PNL side.

An inverter circuit board PCB3 is connected to the back light fluorescent tube BL, and serves as a power source for the backlight fluorescent tube BL.

As described above, by making the pixel electrode transparent, the maximum transmittance at the time of white display can be improved by about 30% (31.8% in the present embodiment).

Specifically, in this embodiment, the transmittance was improved from about 3.8% when the opaque pixel electrode was employed to about 5.0% when the transparent pixel electrode was employed.

In addition, an ITO film for improving the reliability of the terminal can also be formed at the same time, thereby making it possible to achieve both reliability and productivity.

(Example 2)

This example is the same as Example 1 except for the following requirements. 20 is a plan view of the pixel. The diagonal portion in the figure represents the transparent conductive film g2.

<< pixel electrode PX >>

In the present embodiment, the pixel electrode PX is composed of the source electrode SD1, the drain electrode SD2, and the second conductive film d2 and the third conductive film d3 of the same layer. In addition, the pixel electrode PX is formed integrally with the source electrode SD1.

Counter electrode CT

In this embodiment, the counter electrode CT is composed of a transparent conductive film g2. This transparent conductive film g2 is made of a transparent conductive film (Indium-Tin-0xide ITO: nesa film) formed by sputtering similarly to Example 1, and has a thickness of 100 to 2000 GPa (film thickness of about 1400 GPa in this embodiment). Is formed.

Counter voltage signal line CL

The counter voltage signal line CL is comprised by the transparent conductive film g2, and is comprised integrally with the counter electrode CT.

<< gate terminal part >>

In this embodiment, a transparent conductive layer g2 is formed in the same process as that of the counter electrode CT for protecting the surface of the Al layer g1 of the gate terminal GTM and improving the reliability of the connection with a tape carrier pack (TCP). The configuration is not the same as in Example 1, and is as shown in Figs. 7A and 7B.

`` Drain Terminal DTM ''

In this embodiment, the transparent conductive film ITO formed in the same process as the counter electrode CT is used for the transparent conductive layer g2 of the drain connection terminal DTM as in the case of the gate terminal GTM. The configuration is slightly different from that in Example 1 in the vertical relationship of the layers, but the drawings are omitted since they are not essentially different.

Counter electrode terminal CTM

The transparent conductive layer g2 on the conductive layer g1 of the counter electrode terminal CTM uses transparent conductive film ITO formed in the same process as the counter electrode CT in the same manner as the other terminals. The configuration is not changed at all from Example 1 and is as shown in Figs. 9A and 9B.

<< production method >>

In this embodiment, the process F enters between the process B and the process C of Example 1. FIG. As a sequence of a process, the process sequence of FIG. 12 to FIG. 15 becomes an order of A-> B-> F-> C-> D-> E-> G-> H. In the mask pattern, the scan signal line GL, the scan electrode GT, and the counter voltage signal line CL are separated, and the patterns of the transparent conductive layer g2 and the counter voltage signal line CL of each terminal are formed in the same mask.

By the above, by making the counter electrode transparent, the maximum transmittance can be improved by about 16% (15.9% in the present embodiment), and the transmittance of the liquid crystal display panel PNL is about 4.4%.

(Example 3)

This Example is the same as Example 1 and Example 2 except for the following requirement. 21 is a plan view of the pixel. The diagonal portion in the figure represents the transparent conductive film g2.

Counter electrode CT

In this embodiment, the counter electrode CT is composed of a transparent conductive film g2. This transparent conductive film g2 is made of a transparent conductive film (Indium-Tin-Oxide ITO: nesa film) formed by sputtering as in Example 1, and has a thickness of 100 to 2000 GPa (film thickness of about 1400 GPa in this embodiment). Is formed.

Counter voltage signal line CL

The counter voltage signal line CL is comprised by the transparent conductive film g2, and is comprised integrally with the counter electrode CT.

<< production method >>

In this embodiment, the process F is added between the process B and the process C of Example 1. FIG. As a sequence of processes, the process sequence of FIG. 12 to FIG. 15 becomes in order of A-> B-> F-> C-> D-> E-> G-> H. The mask pattern is formed in a mask in which the patterns of the scan signal line GL, the scan electrode GT and the counter voltage signal line CL are independent.

In this embodiment, by making both the pixel electrode and the counter electrode transparent, the maximum transmittance at the time of white display can be improved by about 50% (47.7% in this embodiment) in Example 1 or Example 2 or more. And the transmittance | permeability of liquid crystal display panel PNL becomes about 5.6%.

(Example 4)

This Example is the same as Example 1 and Example 3 except for the following requirement. 22 is a plan view of the pixel. The diagonal portion in the figure represents the transparent conductive film g2.

Counter voltage signal line CL

The counter voltage signal line CL is composed of a conductive film g1. In this embodiment, Cr is used for the conductive film g1. In addition, in order to connect the counter voltage signal line CL and the counter electrode CT, anodization is not performed. In addition, a through hole PH is formed in the gate insulating film GI. In addition to Cr, the conductive film g1 may be formed of Ta, Ti, Mo, W, Al or an alloy thereof, or a clad structure in which these are laminated.

<< production method >>

In this example, step B of Example 1 is deleted. In addition, the through-hole PH is formed at the process E, and the pixel electrode PX and the counter electrode CT are simultaneously formed at the process F with the same mask.

In the present embodiment, in addition to the effects of the first and third embodiments, the resistance of the counter voltage signal line CL is reduced, thereby smoothing the transfer of voltage between the counter electrodes and reducing the distortion of the voltage. Crosstalk (lateral smear) can be reduced.

In addition, by simultaneously forming the pixel electrode PX and the counter electrode CT with the same mask, the process F performed twice in Example 4 becomes one, and productivity is also improved.

(Example 5)

This Example is the same as Example 1 and Example 4 except for the following requirements. 23 is a plan view of the pixel. The diagonal portion in the figure represents the transparent conductive film g2.

Counter electrode CT

In this embodiment, only the center counter electrode CT is constituted by the transparent conductive film g2. The opposite electrode adjacent to the image signal line is formed of a metal film integrally with the opposite voltage signal line.

In the present embodiment, in addition to the effects of the first to fourth embodiments, by making the opposing electrode adjacent to the video signal line opaque, crosstalk due to the video signal can be suppressed. The reason is as shown in the action section.

(Example 6)

In any of the above-described Examples 2 and 3, the counter electrode signal line CL is constituted of the transparent conductive layer g2 together with the counter electrode CT.

In this case, the present embodiment is designed to greatly reduce the resistance of the counter electrode signal line CL by the configuration shown in Figs. 24A to 24C.

24A is a plan view showing a portion of the counter electrode signal line CL of FIG. 20, and FIG. 24B is a cross-sectional view taken along the line b-b of FIG. 24A.

20, the opposite electrode signal line CL has a two-layer structure, and an Al layer 10 having a small resistance value is formed as a lower layer, and the Al is formed on the upper surface of the Al layer 10. The ITO film 11 is formed by completely covering the layer 10. The counter electrode CT is constituted by an extension portion in which a part of the ITO film 11 is extended.

In this case, the resistance of the counter electrode signal line CL can be reduced, and at the same time, another conductive layer (for example, an interlayer insulating film formed by a so-called whisker-like protrusion generated in the Al layer 10) (for example, Electrical short circuit with the video signal line DL can be prevented.

That is, although the Al layer 10 is known to cause whiskers when the interlayer insulating film for the image signal line DL is formed on the upper layer, it causes the above-mentioned problem, but the ITO film is formed by completely covering the Al layer 10. It is confirmed that the said whisker does not generate | occur | produce by this.

In addition, in FIG. 24C, the counter electrode CT is comprised by double wiring, In this example, the wiring of the ITO film 11 is formed so that the wiring of the Al layer 10 may be coat | covered. Since the vicinity of the center line of the wiring is low transmittance even when a voltage is applied between the electrodes, there is almost no decrease in the aperture ratio even when the opaque metal wiring is arranged as in the present example.

By employing double wiring for the counter electrode or the pixel electrode, it is possible to greatly reduce the disconnection failure of the electrode, which is a problem in the large screen.

(Example 7)

≪ Active matrix liquid crystal display device≫

Hereinafter, the Example which applied this invention to the color matrix liquid crystal display device of an active matrix system is demonstrated. In addition, in the drawing demonstrated below, the thing with the same function attaches | subjects the same code | symbol, and the repeated description is abbreviate | omitted.

≪Flat construction of the matrix part (pixel part) ≫

Fig. 25 is a plan view showing one pixel and its periphery of the active matrix system color liquid crystal display device of the present invention. (An oblique part in the figure shows a transparent conductive film i1.)

As shown in Fig. 25, each pixel includes a scan signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode wiring) CL, and two adjacent video signal lines (drain signal line or vertical signal line) DL. It is arrange | positioned in the intersection area | region (in the area | region enclosed by four signal lines). Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode CT. In the figure, the scanning signal lines GL and the counter voltage signal lines CL extend in the left and right directions and are arranged in plural in the vertical direction. The video signal lines DL extend in the vertical direction and are arranged in plural in the left and right directions. The pixel electrode PX is formed of the transparent conductive film i1, is electrically connected to the thin film transistor TFT through the source electrode SD1, and the counter electrode CT is also formed of the transparent conductive film i1, and is electrically connected to the counter voltage signal line CL.

The pixel electrode PX and the counter electrode CT face each other, and the optical state of the liquid crystal LC is controlled by the electric field between each pixel electrode PX and the counter electrode CT, and the display is controlled. The pixel electrode PX and the counter electrode CT are comprised in the comb-tooth shape, respectively, and are long and thin electrodes in the up-down direction of a figure.

The number O (comb teeth) of the counter electrode CT in one pixel is configured such that the number (comb teeth) P of the pixel electrode PX has a relationship of O = P + 1 (O = in this embodiment). 3, P = 2). This is because the counter electrode CT and the pixel electrode PX are alternately arranged, and the counter electrode CT is necessarily adjacent to the video signal line DL. Accordingly, the electric field lines from the video signal line DL can be shielded by the counter electrode CT so that the electric field between the counter electrode CT and the pixel electrode PX is not affected by the electric field generated from the video signal line DL. Since the counter electrode CT is always supplied with the potential from the outside by the counter voltage signal line CL described later, the potential is stable. Therefore, even if it is adjacent to the video signal line DL, there is little change of electric potential. In addition, since the geometric position from the video signal line DL of the pixel electrode PX becomes far, the parasitic capacitance between the pixel electrode PX and the video signal line DL is greatly reduced, and the fluctuation caused by the video signal voltage of the pixel electrode potential Vs is also suppressed. can do. As a result, crosstalk (poor image quality called vertical smear) generated in the vertical direction can be suppressed.

The electrode width of the pixel electrode PX and the counter electrode CT is 6 micrometers, respectively. In order to apply an electric field sufficient to the whole liquid crystal layer with respect to the thickness direction of a liquid crystal layer, this is set as much larger than 3.9 micrometers in thickness of the liquid crystal layer mentioned later, and makes it as thin as possible in order to enlarge an aperture ratio. In addition, in order to prevent disconnection, the electrode width of the video signal line DL is set to 8 m slightly wider than the pixel electrode PX and the counter electrode CT. Here, the electrode width of the video signal line DL is set to be equal to or less than twice the electrode width of the adjacent counter electrode CT. Alternatively, when the electrode width of the video signal line DL is determined from the productivity of the yield, the electrode width of the counter electrode CT adjacent to the video signal line DL is set to 1/2 or more of the electrode width of the video signal line DL. This is for absorbing the electric force lines generated from the video signal lines DL at opposite electrode CTs on both sides, and in order to absorb the electric force lines generated from a certain electrode width, an electrode having an electrode width equal to or larger than that is required. Accordingly, since the opposite electrode CTs on both sides need to absorb the electric force lines generated from half of the electrodes of the video signal line DL (by 4 µm each), the electrode width of the opposite electrode CT adjacent to the video signal line DL becomes 1/2 or more. . This prevents crosstalk, especially in the vertical direction (vertical direction), in which crosstalk occurs due to the influence of the video signal.

The scan signal line GL sets the electrode width so as to satisfy the resistance value as long as the scan voltage is sufficiently applied to the gate electrode GT of the pixel on the end side (the opposite side of the scan electrode terminal GTM described later). In addition, the resistance value as long as the opposite voltage signal line CL can be sufficiently applied to the opposite electrode CT of the pixel on the terminal side (the pixel farthest from the common bus lines CB1 and CB2, that is, the pixel in the middle of CB1 and CB2). Set the electrode width to satisfy.

On the other hand, the electrode interval between the pixel electrode PX and the counter electrode CT changes with the liquid crystal material used. Since the electric field strength which achieves the maximum transmittance | permeability differs by a liquid crystal material, this is set in the range of the maximum amplitude of the signal voltage set to the breakdown voltage of the video signal drive circuit (signal driver) used by setting an electrode space | interval according to a liquid crystal material. This is to obtain the maximum transmittance. When the liquid crystal material described later is used, the electrode interval is 16 µm.

<< cross-sectional structure of the matrix part (pixel part) >>

FIG. 26 is a cross-sectional view taken along the line 6-6 of FIG. 25, FIG. 27 is a cross-sectional view of the thin film transistor TFT taken along the line 7-7 of FIG. 25, and FIG. 28 is a storage capacitor Cstg taken along the line 8-8 of FIG. It is a cross section of.

26 to 28, a thin film transistor TFT, a storage capacitor Cstg, and an electrode group are formed on the lower transparent glass substrate SUB1 side based on the liquid crystal layer LC, and the color filter FIL and light shielding are formed on the upper transparent glass substrate SUB2 side. The black matrix pattern BM is formed.

Moreover, on the surface of each inside (liquid crystal LC side) of transparent glass substrate SUB1, SUB2, the alignment film ORI1, ORI2 which controls the initial orientation of a liquid crystal is provided, and on the surface of each outside of transparent glass substrate SUB1, SUB2, The polarizing plate arrange | positioned orthogonally (cross nicol arrangement) is provided.

<< TFT board >>

First, the configuration of the lower transparent glass substrate SUB1 side (TFT substrate) will be described in detail.

<< thin film transistor TFT >>

The thin film transistor TFT operates so that the channel resistance between the source and the drain becomes small when a positive bias is applied to the gate electrode GT, and the channel resistance becomes large when the bias is zero.

As shown in Fig. 27, the thin film transistor TFT is formed of a gate electrode GT, an insulating film GI, an i-type semiconductor layer AS made of i-type (non-doped intrinsic, intrinsic, conductive type crystal impurities) amorphous silicon (Si); It has a pair of source electrode SD1 and the drain electrode SD2. In addition, since the source and the drain are originally determined by the bias polarity between them, the polarity of the circuit of the liquid crystal display device is inverted during operation. However, in the following description, one side is represented as a source and the other side is fixed as a convenience.

`` Gate Electrode GT ''

The gate electrode GT is formed in succession with the scan signal line GL, and is configured such that a part of the scan signal line GL becomes the gate electrode GT. The gate electrode GT is a portion beyond the active region of the thin film transistor TFT. In this example, the gate electrode GT is formed of a single layer conductive film g3. As the conductive film g3, for example, a chromium-molybdenum alloy (Cr-Mo) film formed of sputtering is used, but not limited thereto.

≪Scan signal line GL≫

The scanning signal line GL is composed of a conductive film g3. The conductive film g3 of the scan signal line GL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, and is integrally formed. The scan signal line GL supplies the gate voltage Vg to the gate electrode GT from an external circuit. In this example, a chromium-molybdenum alloy (Cr-Mo) film formed of, for example, sputtering is used as the conductive film g3. The scan signal line GL and the gate electrode GT are not limited to the chromium-molybdenum alloy but may have a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum, for example, to reduce the resistance. The portion that intersects the video signal line DL may be thinned so as to reduce the probability of a short circuit with the video signal line DL and separated by laser trimming even if shorted.

`` Counter voltage signal line CL ''

The counter voltage signal line CL is composed of a conductive film g3. The conductive film g3 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, the scan signal line GL, and the counter electrode CT, and is configured to be electrically connected to the counter electrode CT. The counter voltage signal line CL supplies the counter voltage Vcom to the counter electrode CT from an external circuit.

The counter voltage signal line CL is not limited to the chromium-molybdenum alloy but may have a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum, for example, to reduce resistance.

The portion that intersects the video signal line DL may be thinned so as to reduce the probability of a short circuit with the video signal line DL and separated by laser trimming even if shorted.

<< insulating film GI >>

The insulating film GI is used as a gate insulating film for providing an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI is formed over the gate electrode GT and the scan signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected, and is formed to have a thickness of 2500 to 4500 Pa (about 3500 Pa in this embodiment). The insulating film GI also serves as an interlayer insulating film of the scan signal line GL, the counter voltage signal line CL, and the video signal line DL, and contributes to their electrical insulation. In addition, the insulating film GI is patterned by the same hot mask as the protective film PSV1 mentioned later, and is processed collectively.

I-type semiconductor layer AS

The i-type semiconductor layer AS is amorphous silicon and is formed to a thickness of 200 to 2500 kPa (in this embodiment, a film thickness of about 1200 kPa).

The layer d0 is an N (+) type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, and is left only in a portion where the i-type semiconductor layer AS exists on the lower side and the conductive layer d3 exists on the upper side.

The i-type semiconductor layer AS and the layer d0 are provided between both the scan signal line GL and the intersection portion (crossover portion) of the counter voltage signal line CL and the video signal line DL. The i-type semiconductor layer AS of this intersection portion reduces the short circuit between the scan signal line GL and the counter voltage signal line CL and the video signal line DL at the intersection portion.

`` Source electrode SD1, drain electrode SD2 ''

Each of the source electrode SD1 and the drain electrode SD2 is composed of a conductive film d3 in contact with the N (+) type semiconductor layer d0.

The conductive film d3 is formed to a thickness of 500 to 3000 GPa (about 2500 GPa in this embodiment) using a chromium-molybdenum alloy (Cr-Mo) film formed of sputtering. Since the Cr-Mo film has a low stress, the film thickness can be made relatively thick, contributing to the reduction in resistance of the wiring. In addition, the Cr-Mo film also has good adhesion with the N (+) type semiconductor layer d0. As the conductive film d3, a high melting point metal (Mo, Ti, Ta, W) film, a high melting point metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used in addition to the Cr-Mo film, It is good also as a laminated structure.

After the conductive film d3 is patterned with a mask pattern, the N (+) type semiconductor layer d0 is removed using the conductive film d3 as a mask. That is, in the N (+) type semiconductor layer d0 remaining on the i-type semiconductor layer AS, portions other than the conductive film d1 and the conductive film d2 are self-aligned. At this time, since the N (+) type semiconductor layer d0 is etched so as to be removed as much as the thickness thereof, the surface portion of the i type semiconductor layer AS is also etched slightly, but the extent may be controlled by the etching time.

≪Video signal line DL≫

The video signal line DL is composed of the source film SD1 and the drain electrode SD2 and the conductive film d3 in the same layer. The video signal line DL is formed integrally with the drain electrode SD2. In this example, the conductive film d3 is formed to a thickness of 500 to 3000 kPa (about 2500 kPa in this embodiment) using a chromium-molybdenum alloy (Cr-Mo) film formed of sputtering. Since the Cr-Mo film has a low stress, the film thickness can be made relatively thick, contributing to the reduction in resistance of the wiring. In addition, the Cr-Mo film also has good adhesion with the N (+) type semiconductor layer d0. As the conductive film d3, a high melting point metal (Mo, Ti, Ta, W) film, a high melting point metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used in addition to the Cr-Mo film, It is good also as a laminated structure.

≪Accumulation Capacity Cstg≫

The conductive film d3 is formed to overlap the counter voltage signal line CL in the source electrode SD2 portion of the thin film transistor TFT. As can be seen from FIG. 28, this superposition constitutes a storage capacitor (capacitive element) Cstg having the source electrode SD2 (d3) as one electrode and the counter voltage signal CL as the other electrode. The dielectric film of the storage capacitor Cstg is composed of the insulating film GI used as the gate insulating film of the thin film transistor TFT.

As shown in Fig. 25, the storage capacitor Cstg is formed in a part of the counter voltage signal line CL in plan view.

≪Protective Film PSV1≫

The protective film PSV1 is provided on the thin film transistor TFT. The protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like, and uses a high transparency and a good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and is formed to a film thickness of about 0.3 to 1 m.

The protective film PSV1 is removed to expose the external connection terminals DTM and GTM. As for the thickness relationship between the protective film PSV1 and the insulating film GI, the former becomes thick in consideration of the protective effect, and the latter is made thin in consideration of the mutual conductance gm of the transistor. In addition, the protective film PSV1 is patterned by the same hot mask as the insulating film GI, and processed collectively. Further, in the pixel portion, through holes TH2 and TH1 are provided for the electrical connection between the counter voltage signal line CL and the counter electrode CT described later and the electrical connection between the source electrode SD2 and the pixel electrode PX. In through-hole TH2, since protective film PSV1 and insulating film GI are processed collectively, the hole to g3 layer is formed, and through-hole TH1 blocks to d3, and the hole to d3 layer is formed.

<< pixel electrode PX >>

The pixel electrode PX is formed of the transparent conductive layer i1. This transparent conductive film i1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: nesa film) formed by sputtering, and is formed to a thickness of 100 to 2000 GPa (film thickness of about 1400 GPa in this embodiment). In addition, the pixel electrode PX is connected to the source electrode SD2 through the through hole TH1.

Since the pixel electrode becomes transparent as in the present embodiment, the maximum transmittance at the time of performing the white display is improved by the transmitted light of the portion, so that brighter display can be performed than when the pixel electrode is opaque. At this time, as will be described later, when no voltage is applied, the liquid crystal molecules maintain the initial alignment state and configure the arrangement of the polarizing plates so as to display black in the state (to be normally black mode). Even if it is made transparent, high quality black display can be performed without transmitting the light of the part. Thereby, the maximum transmittance can be improved and a sufficient contrast ratio can be achieved.

Counter electrode CT

The counter electrode CT is formed of the transparent conductive layer i1. This transparent conductive film i1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: nesa film) formed by sputtering, and is formed to a thickness of 100 to 2000 GPa (film thickness of about 1400 GPa in this embodiment). The counter electrode CT is connected to the counter voltage signal line CL through the through hole TH2.

The counter electrode CT is configured to apply the counter voltage Vcom. In this embodiment, the counter voltage Vcom is a feed-through voltage ΔVs generated when the thin film transistor element TFT is turned off from an intermediate DC potential between the minimum level driving voltage Vdmin and the maximum level driving voltage Vdmax applied to the video signal line DL. It is set to a potential as low as minutes, but when it is desired to reduce the power supply voltage of the integrated circuit used in the video signal driving circuit to about half, an AC voltage may be applied.

<< color filter board >>

25 and 26, the configuration of the upper transparent glass substrate SUB2 side (color filter substrate) will be described in detail.

<< shading film BM >>

On the upper transparent glass substrate SUB2 side, transmitted light from an unnecessary gap portion (gap other than the pixel electrode PX and the counter electrode CT) is emitted to the display surface side to form a light shielding film BM (so-called black matrix) so as not to lower the contrast ratio. have. The light shielding film BM also serves to prevent external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched by the light shielding film BM and the large gate electrode GT which are above and below, and external natural light or backlight light does not reach.

The light shielding film BM shown in FIG. 25 is a structure extending linearly in the left-right direction on the TFT. This pattern is an example, and it is also possible to form a matrix in which the opening is formed in a hole shape. In the part where the electric field direction such as the comb-shaped electrode end is disturbed, the display of the part corresponds one-to-one to the video information in the pixel, and in the case of black, it becomes white in the case of black and white. It is possible. In addition, the gap portion between the counter electrode CT and the video signal line DL in the vertical direction in the figure is shielded by the light shielding layer SH formed in the same process as the gate electrode GT. Accordingly, the light shielding in the vertical direction in the left and right directions can be shielded with high accuracy by the alignment accuracy of the TFT process, so that the boundary of the light shielding layer SH can be set between the electrodes of the counter electrode CT adjacent to the image signal line DL, so that the alignment of the upper and lower substrates is possible. The opening part can be enlarged more than the light shielding by the light shielding film BM which depends on the precision.

The light shielding film BM has a shielding property against light and is formed of a highly insulating film so as not to affect the electric field between the pixel electrode PX and the counter electrode CT. In this embodiment, black pigment is incorporated into the resist material, and 1.2 It is formed in the thickness of about micrometer.

The light shielding film BM is formed linearly in the left-right direction on the pixels of each row, and the effective display area of each row is partitioned by this line. Therefore, the outline of the pixels of each row is made clear by the light shielding film BM. That is, the light shielding film BM has two functions of light shielding for the black matrix and the i-type semiconductor layer AS.

The light shielding film BM is formed in the frame part in the peripheral part, and the pattern is formed continuously with the pattern of the matrix part shown in FIG. The light shielding film BM in the periphery extends outside the sealing portion SL and prevents leakage light such as reflected light caused by the mounting device such as a personal computer from entering the matrix portion, and prevents light such as backlight from leaking out of the display area. Doing. On the other hand, this light shielding film BM is about 0.3-1.0 mm inside from the edge of the board | substrate SUB2, and is formed avoiding the cutting | disconnection area | region of the board | substrate SUB2.

<< color filter FIL >>

Same as Example 1.

<< overcoat film OC >>

Same as Example 1.

`` Liquid crystal layer, alignment film and deflection plate ''

Same as Example 1.

<< composition around the matrix >>

Same as Example 1.

<< gate terminal part >>

(A) is a top view which shows the connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, and FIG. 29 (b) shows sectional drawing along the BB cutting line of FIG. 29 (a). have. In addition, the said figure respond | corresponds to the vicinity of the right center of FIG. 5, and the part of inclination wiring was shown by the linear form for convenience.

In the figure, the Cr-Mo layer g3 is hatched for easy understanding. The gate terminal GTM is composed of a transparent conductive layer i1 which further protects the Cr-Mo layer g3 and its surface and also improves the connection reliability with a tape carrier package (TCP). This transparent conductive layer i1 uses transparent conductive film ITO formed in the same process as the pixel electrode PX.

In the plan view, the insulating film GI and the protective film PSV1 are formed on the right side of the boundary line, and the terminal portion GTM located at the left end is exposed from these to enable electrical contact with an external circuit. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in practice, a plurality of such pairs are arranged up and down as shown in Fig. 29A to constitute the terminal group Tg (Fig. 5). In the manufacturing process, the left end of is extended beyond the cutting region of the substrate and short-circuited by the wiring SHg (not shown). This helps to prevent electrostatic breakdown during rubbing of the alignment film ORI1 in the manufacturing process.

`` Drain Terminal DTM ''

FIG. 30A is a plan view showing the connection from the video signal line DL to its external connection terminal DTM, and FIG. 30B shows a cross section taken along the line B-B in FIG. 30A. In addition, the said figure corresponds to the vicinity of the upper right side of FIG. 5, The direction of a figure changes for convenience, but the right end direction corresponds to the upper end of the board | substrate SUB1.

The TSTd is a test terminal, but no external circuit is connected thereto, but is wider than the wiring so as to be able to contact the probe needle or the like. Similarly, the drain terminal DTM is wider than the wiring portion to allow connection with an external circuit. The external connection drain terminal DTM is arranged in the vertical direction, and the drain terminal DTM constitutes the terminal group Td (subscript omitted) as shown in FIG. 5 and further extends beyond the cutting line of the substrate SUB1, and prevents electrostatic destruction during the manufacturing process. All of them are shorted by interconnect SHd (not shown). The inspection terminal TSTd is formed in each video signal line DL as shown in FIG.

The drain connection terminal DTM is formed of the transparent conductive layer i1 and is connected to the video signal line DL with the protective film PSV1 removed. This transparent conductive film i1 uses transparent conductive film ITO formed in the same process as the pixel electrode PX as in the case of the gate terminal GTM.

In the lead-out wiring from the matrix portion to the drain terminal portion DTM, the layer d3 at the same level as the video signal line DL is formed.

Counter electrode terminal CTM

(A) of FIG. 31 shows the top view which shows the connection from the opposing voltage signal line CL to the external connection terminal CTM, and FIG. 31 (b) shows sectional drawing along the B-B cutting line of FIG. In addition, the figure corresponds to the vicinity of the upper left side of FIG.

Each counter voltage signal line CL is led to the counter electrode terminal CTM collectively as a common bus line CB1. The common bus line CB has a structure in which the conductive layer 3 is laminated on the conductive layer g3 and electrically connected to the transparent conductive layer i1. This is to reduce the resistance of the common bus line CB so that the counter voltage is sufficiently supplied from the external circuit to the counter voltage signal lines CL. This structure is characterized in that the resistance of the common bus line is lowered without newly loading a conductive layer.

The counter electrode terminal CTM has a structure in which the transparent conductive layer i1 is laminated on the conductive layer g3. This transparent conductive film i1 uses the transparent conductive film ITO formed by the same process as the pixel electrode PX like the other terminal. In order to protect the surface by the transparent conductive layer i1 and to prevent electrical corrosion, the conductive layer g3 is covered with the durable transparent conductive layer i1. In addition, the connection between the transparent conductive layer i1, the conductive layer g3, and the conductive layer d3 forms through holes in the protective film PSV1 and the insulating film GI, and conducts conduction.

FIG. 32A is a plan view showing the connection from the other end of the opposing voltage signal line CL to its external connection terminal CTM2, and FIG. 32B is a cut line BB of FIG. 32A. A cross-sectional view is shown. In addition, the figure corresponds to the vicinity of the upper right side of FIG. Here, in the common bus line CB2, it is collectively drawn out to the counter electrode terminal CTM2 at the other end (gate terminal GTM side) of each counter voltage signal line CL. The difference from the common bus line CB1 is that the conductive layer d3 and the transparent conductive layer i1 are formed so as to be insulated from the scan signal line GL. The insulating signal GI is insulated from the insulating film GI.

<< display device whole equivalent circuit >>

33 shows a wiring diagram of an equivalent circuit of the display matrix portion and its peripheral circuits. Although the figure is a circuit diagram, it is shown corresponding to the actual geometric arrangement. AR is a matrix array in which a plurality of pixels are arranged in two dimensions.

In the figure, X means the video signal line DL, and subscripts G, B, and R are added corresponding to the green, blue, and red pixels, respectively. Y means scanning signal line GL, and subscripts 1, 2, 3,... , end is added in the order of the scanning timing.

The scan signal line Y (subscript omitted) is connected to the vertical scan circuit V, and the video signal line X (subscript omitted) is connected to the video signal drive circuit H.

SUP includes a power supply circuit for obtaining a plurality of divided voltage stabilized voltage sources from one voltage source, or a circuit for exchanging information for a CRT (cathode ray tube) from a host (higher processing unit) with information for a TFT liquid crystal display device. It is a circuit.

<< driving method >>

34 shows driving waveforms of the liquid crystal display of this embodiment. The opposing voltage Vc is a constant voltage. The scan signal Vg takes an on level every one scanning period and otherwise takes an off level. The image signal voltage is applied to one pixel by inverting the anode and the cathode by one frame at an amplitude twice the voltage to be applied to the liquid crystal layer. Here, the video signal voltage Vd inverts polarity for every column and inverts polarity for every row. As a result, the pixels inverted in polarity are arranged to be adjacent to each other up, down, left, and right, so that flicker and crosstalk (smear) are less likely to occur. The counter voltage Vc is set to a voltage lowered by a predetermined amount from the center voltage of the polarity inversion of the video signal voltage. This corrects the feed-through voltage generated when the thin film transistor element changes from on to off, and is performed to apply an alternating voltage having a small DC component to the liquid crystal. This is because, when a direct current is applied to a liquid crystal, afterimage, deterioration, etc. become severe.

In addition, the opposite voltage can be altered to reduce the maximum amplitude of the video signal voltage, and it is also possible to use a low withstand voltage for the video signal drive circuit (signal driver).

<< function of accumulation capacity Cstg >>

Same as Example 1.

<< production method >>

Next, the manufacturing method of the board | substrate SUB1 side of the liquid crystal display device mentioned above is demonstrated with reference to FIGS. 35-37. In addition, in the said figure, the character of the center is abbreviation of a process name, the left side shows the flow of this process in the cross-sectional shape of the thin film transistor TFT part shown in FIG. 27, and the right side is near the gate terminal shown in FIG. Except for Step B and Step D, Steps A to I are classified corresponding to each photo process, and either of the cross-sectional views of each step shows a step in which the photoresist is finished and the photoresist is removed. In addition, in this description, a photo process shows a series of operation | work from the application of a photoresist to the selective exposure using a mask, and to develop it, and description of repetition is avoided. Hereinafter, it demonstrates according to the process classified.

Step A, Fig. 35

On the lower transparent glass substrate SUB1 made of AN635 glass (brand name), a conductive film g3 made of Cr-Mo or the like having a film thickness of 2000 kPa is provided by sputtering. After the photo treatment, the conductive film g3 is selectively etched with dicerium ammonium nitrate. Thereby, the bus line SHg for connecting the gate electrode GT, the scan signal line GL, the counter voltage signal line CL, the gate terminal GTM, the first conductive layer of the common bus line CB1, the first conductive layer of the counter electrode terminal CTM1, and the gate terminal GTM ( Not shown).

Process B, Fig. 35

Ammonia gas, silane gas and nitrogen gas were introduced into the plasma CVD apparatus to provide a Si nitride film having a film thickness of 3500 kPa, and silane gas and hydrogen gas were introduced into the plasma CVD apparatus to form an i-type amorphous Si film having a film thickness of 1200 kPa. After the installation, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N (+) type amorphous Si film having a film thickness of 300 kPa.

Process C, FIG. 35

After the photographic processing, the islands of the i-type semiconductor layer AS are formed by selectively etching the N (+)-type amorphous Si film and the i-type amorphous Si film using SF ₆ and CCl ₄ as dry etching gases.

Process D, Fig. 36

A conductive film d3 made of Cr having a film thickness of 300 GPa is provided by sputtering. After the photo process, the conductive film d3 is etched with the same liquid as in step A, and the bus line SHd (shorting the video signal line DL, the source electrode SD1, the drain electrode SD2, the first conductive layer of the common bus line CB2, and the drain terminal DTM ( Not shown). Subsequently, CCl ₄ and SF ₆ are introduced into the dry etching apparatus to etch the N (+) type amorphous Si film to selectively remove the N (+) type semiconductor layer d0 between the source and the drain.

Process E, FIG. 36

Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a Si nitride film having a film thickness of 0.4 m. After the photo process, the protective film PSV1 and the insulating film GI are patterned by selectively etching the Si nitride film using SF ₆ as the dry etching gas.

Process F, FIG. 37

A transparent conductive film i1 made of an ITO film having a film thickness of 1400 kPa is provided by sputtering. After the photographic treatment, the transparent conductive film i1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as the etching solution to form the uppermost layer of the gate terminal GTM, the drain terminal DTM, and the second conductive layers of the counter electrode terminals CTM1 and CTM2.

《Display panel PNL and driving circuit board PCB1》

Same as Example 1.

<< connection structure of TCP >>

Same as Example 1.

Drive Circuit Board PCB2

Same as Example 1.

<< whole structure of liquid crystal display module >>

Same as Example 1.

As described above, in the present embodiment, by making the comb-shaped electrode transparent as in Example 3, the maximum transmittance at the time of white display can be improved by about 50%, and the transmittance of the liquid crystal display panel PNL is about 5.7%.

In addition, an ITO film for improving the reliability of the terminal can also be formed at the same time, thereby making it possible to achieve both reliability and productivity.

In addition, in the present embodiment, unlike the embodiments 1 to 6, since the process of forming ITO on the upper layer of the protective film PSV is used, the counter electrode can be made the uppermost layer, and the shielding efficiency of the leakage field from the video signal line is also good. Thus, crosstalk can be reduced.

In addition, since the protective film PSV is not interposed in the path of the electric line for driving the liquid crystal between the electrodes, there is no voltage reduction in the protective film PSV, and the maximum driving voltage value for driving the liquid crystal is 5.0 in the example seen from 7.5 V of the first embodiment. It could be reduced to V.

In the method of driving the liquid crystal by applying an electric field substantially parallel to the substrate surface as in the present method, since the protective film is inserted twice in the path of the electric force line between the electrodes, the process can be simplified and the productivity is also improved.

(Example 8)

This example is the same as Example 7 except for the following requirements. 38 shows a plan view of the pixel. The diagonal line in the figure shows the transparent conductive film i1.

<< pixel electrode PX >>

In the present embodiment, the pixel electrode PX is constituted of the conductive film d3 of the same layer as the source electrode SD1 and the drain electrode SD2. In addition, the pixel electrode PX is formed integrally with the source electrode SD1.

In the present embodiment, in addition to the effects of the first embodiment, the transmittance is sacrificed, but contact failure between the pixel electrode PX and the source electrode SD1 can be avoided. In addition, since one side of the electrode is covered with the insulating film (protective film PSV1), when there is an alignment film defect, the possibility that a direct current flows through the liquid crystal is reduced, and liquid crystal deterioration and the like are eliminated, thereby improving reliability.

(Example 9)

This example is the same as Example 7 except for the following requirements. 39 is a plan view of the pixel. The diagonal line in the figure shows the transparent conductive film i1.

Counter electrode CT

In this embodiment, the counter electrode CT is formed integrally with the counter voltage signal line CL by the conductive film g3.

In the present embodiment, in addition to the effects of the first embodiment, the transmittance is sacrificed, but contact failure between the counter electrode CT and the counter voltage signal line CL can be avoided. In addition, since one side of the electrode is covered with the insulating film (protective film PSV1), when there is an alignment film defect, the possibility that a direct current flows through the liquid crystal is reduced, and liquid crystal deterioration or the like is eliminated, thereby improving reliability.

(Example 10)

This example is the same as Example 7 except for the following requirements. 40 is a plan view of the pixel. The diagonal line in the figure shows the transparent conductive film i1.

<< shading film BM >>

On the upper transparent glass substrate SUB2 side, transmitted light from an unnecessary gap portion (gap other than between the pixel electrode PX and the counter electrode CT) is emitted to the display surface side to form a light shielding film BM (so-called black matrix) so as not to lower the contrast ratio. Doing. The light shielding film BM also serves to prevent external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched by the light shielding film BM and the large gate electrode GT which are above and below, and external natural light or backlight light does not reach.

The light shielding film BM shown in FIG. 40 has the structure extended in the up-down-left-right direction on the thin film transistor element TFT, and has a matrix form which formed the hole in the opening part. In the part where the electric field direction such as the comb-shaped electrode end is disturbed, the display of the part corresponds one-to-one to the video information in the pixel, and in the case of black, it becomes white in the case of black and white. It is possible.

In addition, in the present embodiment, unlike Example 7, the light shielding film BM has a shielding property against light and has a high conductivity so that the electric field from the video signal line DL does not affect the electric field between the pixel electrode PX and the counter electrode CT. In this embodiment, a three-layer structure of chromium oxide (CrOx), chromium nitride (CrNx), and chromium (Cr) is formed to a thickness of about 0.2 µm from the opposing substrate SUB1 surface. At this time, chromium oxide (CrOx) is used to suppress reflection of the display surface. Further, chromium (Cr) is provided on the top layer of the light shielding layer BM so as to provide a voltage from the outside to the light shielding film BM.

The light shielding film BM is formed linearly in the left-right direction on the pixels of each row, and the effective display area of each row is partitioned by this line. Therefore, the outline of the pixels of each row is made clear by the light shielding film BM. That is, the light shielding film BM has two functions of light shielding for the black matrix and the i-type semiconductor layer AS.

The light shielding film BM is formed in the frame part in the peripheral part, and the pattern is formed continuously with the pattern of the matrix part shown in FIG. The light shielding film BM in the peripheral portion extends outside the sealing portion SL, and prevents leakage light such as reflected light caused by the mounting device such as a personal computer from entering the matrix portion, and also prevents light such as a backlight from leaking out of the display area. Doing. On the other hand, this light shielding film BM is about 0.3-1.0 mm inside from the edge of the board | substrate SUB2, and is formed avoiding the cutting | disconnection area | region of the board | substrate SUB2.

<< overcoat film OC >>

Same as Example 1. However, the through hole may be formed so as to provide a potential to the light shielding film BM. It is preferable to connect to the opposing voltage Vc as a potential.

In the present embodiment, in addition to the effects of the seventh embodiment, the light shielding film BM shields the influence of the electric field from the video signal line DL, thereby eliminating the influence of the electric fields of the pixel electrode PX and the counter electrode CT. Therefore, the crosstalk with the video signal line DL is eliminated, and the image quality defect (smear) which the line on a screen is eliminated can be eliminated. In addition, the area for shielding the transparent counter electrode CT disposed on both sides of the video signal line DL with the light shielding layer SH can also be made small, and higher transmittance can be achieved.

(Example 11)

43A to 43D show a principle of improving the aperture ratio of the active matrix type color liquid crystal display device according to the present embodiment, and FIG. 43A shows the inside of the liquid crystal layer when a voltage is applied to the electrode. 43 (b) is a plan view showing the reorientation state of the liquid crystal molecules near the center of the liquid crystal layer, and FIG. 43 (c) is rotation of the liquid crystal molecules shown in FIG. 43 (b). 43 (d) is an example of the characteristic diagram which showed the transmittance | permeability distribution of the light which permeate | transmits the liquid crystal layer between an up-down polarizing plate, an up-down board | substrate, an electrode top, and an electrode.

Here, it is the same as Example 7 except the following requirement.

In this embodiment, about 2x10 ¹² N (Newton) was used as the twist elastic modulus K2 of the liquid crystal layer.

Using a relatively large value of, for example, about 10 x 10 ^-12 N (Newton) as the twist elastic modulus K2, as shown in FIG. 41 (b), the liquid crystal molecules at the center on the electrode are almost rotated. (alpha) is 0, and as a result, the transmittance | permeability of the center part on an electrode becomes a value of dark display substantially.

On the other hand, in the present Example, even the liquid crystal molecule of the center part on an electrode was rotated, and it turned out that 50% or more of the average transmittances of the transmittance | permeability of the A part between electrodes become the average transmittance | permeability of the transmittance of the B part on an electrode.

Therefore, the average transmittance of the entire portion becomes the average transmittance of the transmittance of the A + B portion and is greatly increased.

This invention is applied to a liquid crystal etc. as mentioned above, and there exists practical possibility in the liquid crystal manufacturing industry.

Claims (21)

In an active matrix liquid crystal display device having a pixel electrode and an opposite electrode and controlling liquid crystal molecules of a twistable liquid crystal layer by an electric field component substantially parallel to a substrate surface between the pixel electrode and the opposite electrode, and displaying the same. , At least one of the pixel electrode or the opposite electrode is a transparent electrode, and the initial alignment state of the twistable liquid crystal and the polarization axis of the polarizing plate are configured such that the light transmittance of the display device increases as the electric field component is increased, and when no electric field is applied. The initial orientation state of the twistable liquid crystal layer of is a homogeneous orientation state, wherein liquid crystal molecules on and between the electrodes when the electric field is applied dominantly rotate approximately parallel to the substrate surface, and the maximum value of the light transmittance is An active matrix liquid crystal display device, wherein the viewing angle range of 4.0% or more and a contrast ratio of 10: 1 or more is within a range of an omnidirectional inclination of 40 ° or more from the vertical direction with respect to the display surface. In an active matrix liquid crystal display device having a pixel electrode and an opposite electrode and controlling liquid crystal molecules of a twistable liquid crystal layer by an electric field component substantially parallel to a substrate surface between the pixel electrode and the opposite electrode, and displaying the same. , At least one of the pixel electrode or the opposite electrode is a transparent electrode, and the initial alignment state of the twistable liquid crystal and the polarization axis of the polarizing plate are configured such that the light transmittance of the display device increases as the electric field component is increased, and when no electric field is applied. An initial alignment state of the twistable liquid crystal layer is a homogeneous alignment state, and a twist elastic modulus is 10 × 10 ⁻¹² N (Newtons) or less. In an active matrix liquid crystal display device having a pixel electrode and an opposite electrode and controlling liquid crystal molecules of a twistable liquid crystal layer by an electric field component substantially parallel to a substrate surface between the pixel electrode and the opposite electrode, and displaying the same. , At least one of the pixel electrode or the opposite electrode is a transparent electrode, and the initial alignment state of the twistable liquid crystal and the polarization axis of the polarizing plate are configured such that the light transmittance of the display device increases as the electric field component is increased, and when no electric field is applied. The initial orientation state of the twistable liquid crystal layer of is a homogeneous alignment state, the initial pretilt angle of the liquid crystal molecules of the upper and lower interfaces of the liquid crystal layer is 10 ° or less, the initial tilt state of the liquid crystal molecules in the liquid crystal layer is a splay state An active matrix liquid crystal display device. In an active matrix liquid crystal display device having a pixel electrode and an opposite electrode and controlling liquid crystal molecules of a twistable liquid crystal layer by an electric field component substantially parallel to a substrate surface between the pixel electrode and the opposite electrode, and displaying the same. , At least one of the pixel electrode or the opposite electrode is a transparent electrode, and the initial alignment state of the twistable liquid crystal and the polarization axis of the polarizing plate are configured such that the light transmittance of the display device increases as the electric field component is increased, and when no electric field is applied. An initial alignment state of the twistable liquid crystal layer is a homogeneous alignment state, and the average tilt angle of the liquid crystal molecules of the liquid crystal layer on the transparent electrode is less than 45 ° even when an electric field is applied. The method of claim 2, An active matrix liquid crystal display device, wherein the twist elastic modulus of the liquid crystal is 5.1 × 10 ⁻¹² N (Newtons) or less. The method of claim 2, A twisted elastic modulus of the liquid crystal is 2 × 10 ^-12 N (Newtons) or less, An active matrix liquid crystal display device. The method of claim 3, The initial tilt angle of the liquid crystal molecules of the upper and lower interfaces of the twistable liquid crystal layer is 6 ° or less, characterized in that the active matrix liquid crystal display device. The method of claim 4, wherein And an average tilt angle of the liquid crystal molecules on the transparent electrode of the twistable liquid crystal layer is 30 degrees or less even when an electric field is applied. The method of claim 4, wherein And an average tilt angle of the liquid crystal molecules on the transparent electrode of the twistable liquid crystal layer is 10 ° or less even when an electric field is applied. The method according to any one of claims 1 to 4, An active matrix liquid crystal display device, wherein the pixel electrode or the counter electrode has a double structure of a transparent electrode and an opaque metal electrode. The method according to any one of claims 1 to 4, The active matrix liquid crystal display device further has a counter voltage signal line for electrically connecting the counter electrodes, An active matrix liquid crystal display device characterized in that two adjacent voltage signal lines are connected through a through hole by opposite electrodes. The method according to any one of claims 1 to 4, The active matrix liquid crystal display device further has a protective film covering the active matrix element, At least one of the pixel electrode or the counter electrode is formed on the protective film, and is electrically connected to the active matrix element or the counter voltage signal line through a through hole formed in the protective film. The method according to any one of claims 1 to 4, An active matrix liquid crystal display device, wherein the opposite electrode is formed of a transparent electrode, and further includes a light shielding pattern between the opposite electrode and the image signal line. The method according to any one of claims 1 to 4, The active matrix liquid crystal display device further has a counter voltage signal line for electrically connecting the counter electrodes, And the counter voltage signal line is formed of a metal. The method of claim 11, And the counter voltage signal line is formed of a metal. The method according to any one of claims 1 to 4, The active matrix liquid crystal display device also has a video signal line and has three or more counter electrodes including two counter electrodes adjacent to the video signal line in one pixel, and the counter electrode adjacent to the video signal line is opaque. An active matrix liquid crystal display device. The method according to any one of claims 1 to 4, An active matrix liquid crystal display device, wherein the transparent conductive film of the transparent electrode is indium-tin-oxide (ITO). The method according to any one of claims 14 to 15, The counter voltage signal line is formed of Cr, Ta, Ti, Mo, W, Al or an alloy thereof, or a clad structure in which these are laminated. The method according to any one of claims 14 to 15, The counter voltage signal line is formed of a clad structure in which a transparent conductive film such as indium tin oxide (ITO) is laminated on Cr, Ta, Ti, Mo, W, Al, or an alloy thereof. Display device. The method according to any one of claims 1 to 4, When no electric field is applied, the initial twist angle of the liquid crystal layer is almost 0, and the initial orientation angle is 0 ° if the dielectric anisotropy Δε of the liquid crystal material is positive, but 45 ° or more and less than 90 °, and the dielectric anisotropy Δε is negative. It is 45 degrees or less, and is active matrix type liquid crystal display device characterized by the above-mentioned. In the manufacturing method of the active-matrix type liquid crystal display device which has a pixel electrode and a counter electrode, and controls display of liquid crystal molecules of a liquid crystal layer by the electric field component which is substantially parallel to the board | substrate surface between the said pixel electrode and the said counter electrode, At least one of the conductive layer of the uppermost layer of the scan signal line terminal portion, the video signal line terminal portion, or the counter electrode terminal portion, and at least one of the pixel electrode or the counter electrode are formed of a transparent conductive layer, and are formed in the same process. The manufacturing method of a matrix type liquid crystal display device.