KR20000044680A - Semiconductor memory device embedding self testing circuit - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to be able to automatically self-test with using as a control of test mode by composing an input/output with an unused pad by embedding a simple test mode inside the memory device. CONSTITUTION: A write mode is selected by feeding a simple input from high to low in an input pad(2) inputted a control signal. A write '0' is proceeded in every cell with a data input as '0' in selecting every word lines and bit lines. '0' data are written on every memory cells for a sufficient time. The write mode is switched to a read mode by a mode selector with a pre-charging time. An address is generated by an address counter and data written in the memory cell about every address are read. A fail is detected and outputted by comparing the read output of data and the data input '0' in a data comparator(2e) at writing.

Description

Semiconductor memory device with self test circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which a self test circuit is integrated on an on-chip.

The degree of integration of semiconductor memory devices has been greatly increased. Increasing the degree of integration of semiconductor memory devices requires that manufacturing equipment be expensive. This is because with the development of the process technology, bringing the advanced of the manufacturing equipment in order to realize the manufacturing technology that is becoming more miniaturized, the higher the equipment cost. On the other hand, as semiconductor memory devices become more integrated, chip manufacturers perform tests to guarantee their reliability, and test equipment for this test also requires a considerable cost. The time to perform the test also requires a considerable amount of time for a highly integrated semiconductor memory device, and the high cost of the equipment and the chip manufacturer has been a significant burden.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor memory device in which a self-test circuit is integrated on an on-chip.

Another object of the present invention is to provide a semiconductor memory device having a self-test circuit implemented with simple logic to reduce test costs.

It is another object of the present invention to provide a semiconductor memory device which enables quick and easy automatic self-testing by using a pad which is not used by embedding a simple test mode into a memory device, thereby enabling a quick and easy automatic self-test using the test mode control. Is in.

1 is a block diagram showing a schematic configuration of a semiconductor memory device incorporating a self-test circuit according to the present invention.

2 is a view showing a process in the test mode according to FIG.

3 is a test timing diagram according to FIG. 1;

4 is an implementation circuit diagram of an address counter.

5 is an implementation circuit diagram of a clock generation circuit.

6 is an implementation circuit diagram of a data comparator and an output stage.

* Explanation of symbols for main parts of the drawings

2: control signal input pad 4: address generator

6: Mode selector 8: Data comparator

10: output pad 12: internal memory

A semiconductor memory device according to the present invention for achieving the above object comprises a self-test circuit for inputting a control signal to a pad on an on-chip and supplying information about read / write of data to an output pad in response to this input level. It is characterized by the built-in semiconductor memory device.

The self-test circuit includes an input pad for inputting a control signal from an external source, an address generation circuit for inputting an output signal of the input pad and generating an internal address and outputting the internal address to the internal memory unit, and an output signal of the input pad. A mode selector for inputting a signal and determining a test mode according to the input level, a data comparator for detecting output data of the memory unit in response to the output of the mode selector, and an output pad for outputting the output of the data comparator to the outside; Characterized in having.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do. In the drawings, the same reference numerals are used for the same components as in the prior art.

1 is a block diagram showing a schematic configuration of a semiconductor memory device incorporating a self-test circuit according to the present invention.

Included in the small dotted line block in FIG. 1 is a basic block logic diagram required for the self-test circuit of the present invention. As shown in FIG. 1, the memory chip of the present invention inputs a control signal input pad 2 for inputting a control signal from an external source, and a control signal from the input pad 2, and accordingly internally. An address generator 4 for generating an address and outputting it to the chip internal memory unit 12, and a mode selector for inputting a control signal from the input pad 2 and determining a test mode according to the input level ( 6), a data comparator 8 for detecting output data from the memory unit 12 in response to the output of the mode selector 6, and an output pad for outputting the output of the data comparator 8 to the outside. It consists of 10. As shown in Fig. 1, the self-test circuit according to the present invention only needs a simple logic configuration.

This logic consists of two simple modes: write and read. 2 shows the progress of logic. FIG. 2 shows a process in the test mode according to FIG. 1. Referring to FIG. 2, a simple input of high to low is applied to an input pad 2 that receives a control signal from an external source and is selected as a write mode (2a). In the state where all word lines wl and bit lines bl are selected, the data input is '0', and the write '0' is performed to all cells (2b). After writing '0' data to all the memory cells for a sufficient time (write time secured), the mode selector switches to read mode with a precharge time for a predetermined time and generates an address by operation of the address counter (2c). While reading the written data of the memory cells for all addresses (2d). The data output read here is compared with the data input '0' at the time of writing and the data comparator 2e determines whether or not a failure is detected and outputs a failure.

3 shows the internal test timing according to FIG. Fig. 3 shows the input signal A, the write mode selection B, the write data input C, the read mode selection D, the read data input E, the data comparison and the defect output F in that order. have. That is, the write mode is first started by the first input signal (high to low), and then the data input is set to '0'. After the write is over, the unit enters lead mode with the necessary delay. The data is read out from the memory cells in order, and then compared with the input data. If a defect bit exists, the data comparator 8 detects it and outputs a defect. .

4, 5 and 6 show embodiments of the respective circuits for implementing the present invention, which can be implemented using circuits used in semiconductor memory devices. FIG. 4 is an implementation circuit diagram of an address counter in the address generator 4 of FIG. 1, FIG. 5 is an implementation circuit diagram of a clock generation circuit in the address generator 4 in FIG. 1, and FIG. The implementation circuit diagram of the comparator 8 and the output terminal is shown.

4 and 5, they constitute the address generator 4 of FIG. First, in the clock generation circuit of FIG. 5, a read pulse is generated and the necessary addresses are combined by two units in the address counter of FIG. 4. This address counter is used as an input address used for reading all memory cells by using as many addresses as necessary for the memory cells.

6, the data comparator 8 and the fault output logic can be seen. The fault pad is set to an initial low value to maintain low output. When the expected data output is a value other than '0', the path gate is opened and the latch data is changed by the value. This is observed from the defect pad to determine whether the chip is defective. (If the defect pad is 'high', the defect is normal, and if it is 'low', the present invention allows the chip to be tested with a simple internal logic. There is no burden to carry out with all test equipment.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention has an effect that a simple sorting test can be easily performed without the help of test equipment by integrating a self-test circuit on an on-chip. In addition, it is possible to implement a self-test circuit simply by using a pad not used in the chip.

Claims (2)

In a semiconductor memory device, And a self-test circuit for inputting a control signal to an on-chip pad and for supplying information about read / write of data to an output pad in response to this input level. The method of claim 1, The self test circuit, An input pad for inputting a control signal from the outside; An address generator which inputs an output signal of the input pad and generates an internal address and outputs the internal address accordingly; A mode selection unit which inputs an output signal of the input pad and determines a test mode according to the input level; A data comparator for detecting output data of the memory unit in response to an output of the mode selection unit; And An output pad that outputs the output of the data comparator to the outside A semiconductor memory device comprising a.