KR20000043446A - Annealing after ion implantation - Google Patents

Annealing after ion implantation Download PDF

Info

Publication number
KR20000043446A
KR20000043446A KR1019980059825A KR19980059825A KR20000043446A KR 20000043446 A KR20000043446 A KR 20000043446A KR 1019980059825 A KR1019980059825 A KR 1019980059825A KR 19980059825 A KR19980059825 A KR 19980059825A KR 20000043446 A KR20000043446 A KR 20000043446A
Authority
KR
South Korea
Prior art keywords
gas
ion implantation
annealing
reaction chamber
oxide film
Prior art date
Application number
KR1019980059825A
Other languages
Korean (ko)
Inventor
박영진
Original Assignee
윤종용
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1019980059825A priority Critical patent/KR20000043446A/en
Publication of KR20000043446A publication Critical patent/KR20000043446A/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: A method for performing an annealing process after implanting ions is provided to improve a process condition of an annealing process after performing an ion implantation process. CONSTITUTION: A method for performing an annealing process after implanting ions comprises the following steps. In an annealing process performed between an ion implantation process and a field oxidation process, A gas of O2 is inserted within a reaction chamber containing a gas of N2. The gas O2 and the gas N2 are mixed within the reaction chamber. The mixed gas controls SixNy formed locally on a polysilicon layer(11). A mixing rate of the gas N2 and the gas O2 is defined by a rate of 100-5.

Description

이온주입후 열처리방법{Annealing after ion implantation}Annealing after ion implantation

본 발명은 반도체소자 공정 중의 이온주입(ion implantation)에 관한 것이다. 보다 구체적으로 본 발명은 이온주입후의 열처리시의 공정조건을 개선하는 것에 관한 것이다.The present invention relates to ion implantation during semiconductor device processing. More specifically, the present invention relates to improving process conditions during heat treatment after ion implantation.

이온주입이란 에너지를 갖는 하전입자를 반도체기판 내에 강제로 침투시키는 공정을 말한다. 이온주입은 주로 기판의 전기적 성질을 변화시키는데 이용되고 있는데, 종래의 확산공정 대신에, 또는 함께 이용되고 있다. 이온을 주입시키는 에너지는 보통 30~300keV 정도이고 이온주입량(dose)은 1011~1016개/cm2정도이다. 이온주입의 주요 장점은 확산에 의한 불순물도핑보다 도핑량의 제어를 정밀하게 할 수 있고 재현성이 우수하며 확산공정보다 낮은 온도에서 실시할 수 있다는 점이다. 그러나, 이온주입은 근본적으로 도펀트(dopant)를 반도체기판에 물리적으로 침투시키는 것이기 때문에 반도체의 고유 격자구조를 파괴하여 손상(lattice defect)을 일으키는 문제가 있다. 이러한 격자손상을 보상하기 위하여 이온주입 후에는 고온열처리(annealing)를 하여 격자구조를 원상으로 회복시킨 다음에 이후 공정을 진행하고 있다.Ion implantation refers to a process of forcibly penetrating charged particles having energy into a semiconductor substrate. Ion implantation is mainly used to change the electrical properties of the substrate, and is used instead of or in conjunction with conventional diffusion processes. The energy for implanting ions is usually about 30 to 300 keV and the dose is about 10 11 to 10 16 / cm 2 . The main advantage of ion implantation is that the doping amount can be controlled more precisely than the doping of impurities by diffusion, and it is excellent in reproducibility and can be carried out at a lower temperature than the diffusion process. However, since ion implantation is essentially a physical infiltration of dopants into the semiconductor substrate, there is a problem of breaking the intrinsic lattice structure of the semiconductor and causing damage. In order to compensate for the lattice damage, after the ion implantation, the lattice structure is restored to the original state by high temperature heat treatment (annealing), and then the process is performed.

그러나, 이온주입후의 열처리는 약 1050℃의 고온에서 진행되므로 공정중에 사용되는 질소(N2)가스와 웨이퍼에 형성된 다결정실리콘이 반응하여 국부적으로 SiN이 형성되어, 다음 공정에서 필드산화막을 형성할 때에 국부적으로 산화막이 성장하지 않는 결함이 발생한다.However, since the heat treatment after ion implantation proceeds at a high temperature of about 1050 ° C., the nitrogen (N 2 ) gas used during the process and the polysilicon formed on the wafer react to form SiN locally to form a field oxide film in the next step. A defect occurs in which the oxide film does not grow locally.

구체적으로 도1a, 1b를 참조하여 설명한다. 도1a를 보면, 다결정실리콘층(1)에 마스크용으로 쓰이는 질화막(Si3N4)(3)이 코팅되어 있다. 가운데 빈 공간(F)은 필드(field)라고 부르는 영역으로서 소자와 소자의 경계영역으로서 두꺼운 산화막을 성장시킬 영역이다. 그런데, 이온주입후 고온에 의한 열처리를 하면 반응실 내에 있는 질소가스와 웨이퍼의 다결정실리콘(1)이 반응하여 SixNy의 부정형 질화막(5)이 국부적으로 형성된다. 이 부정형 질화막(5)은 필드산화막(7)을 성장시킬 때에 산화막 성장을 방해하기 때문에 도1b에서 보는 것과 같이 필드산화막(7)에 국부적으로 미성장 결함(9)이 생기게 된다. 이는 곧 반도체소자의 특성을 저하시키는 요인이 된다.Specifically, this will be described with reference to FIGS. 1A and 1B. Referring to FIG. 1A, a nitride film (Si 3 N 4 ) 3 used for a mask is coated on the polysilicon layer 1. The middle empty space F is a region called a field, and is a region in which a thick oxide film is grown as a boundary region between the device and the device. However, when the heat treatment is performed at high temperature after ion implantation, the nitrogen gas in the reaction chamber and the polysilicon 1 of the wafer react to form a Si x N y amorphous nitride film 5 locally. Since the amorphous nitride film 5 interferes with the oxide film growth when the field oxide film 7 is grown, ungrown defects 9 are locally generated in the field oxide film 7 as shown in FIG. This is a factor that lowers the characteristics of the semiconductor device.

따라서, 본 발명의 목적은 이온주입후의 열처리중에 산소(O2)가스를 소량 투입하여 SixNy대신에 SiO2와 SiON이 생성되도록 하여 필드산화막 성장시 국부적으로 미성장결함이 발생하는 것을 억제하는 방법을 제공하는 것이다.Accordingly, an object of the present invention is to add a small amount of oxygen (O 2 ) gas during the heat treatment after ion implantation, so that SiO 2 and SiON are produced instead of Si x N y , thereby suppressing local ungrowth defects during field oxide film growth. To provide a way.

도1a, 1b는 종래의 열처리공정과 필드산화공정을 나타내는 단면도.1A and 1B are sectional views showing a conventional heat treatment process and a field oxidation process.

도2a, 2b는 본 발명에 따른 열처리공정과 필드산화공정을 나타내는 단면도.Figure 2a, 2b is a cross-sectional view showing a heat treatment process and a field oxidation process according to the present invention.

<도면의 주요 부호에 대한 설명><Description of Major Symbols in Drawing>

1, 11: 다결정실리콘 3, 13: 질화막1, 11: polycrystalline silicon 3, 13: nitride film

5: 부정형 질화막 7, 17: 필드산화막5: amorphous nitride film 7, 17: field oxide film

15: SiO2/SiON막15: SiO 2 / SiON film

위 목적을 달성하기 위하여, 본 발명에 따르면 이온주입 공정과 필드산화 공정 사이에 진행되는 열처리 공정(annealing)에 있어서, N2가스가 포함되어 있는 반응실 내에 O2가스를 혼입시켜 다결정실리콘 표면에 국부적으로 형성되는 SixNy를 억제하는 것을 특징으로 한다. 여기서, N2가스:O2가스=100:5인 것이 바람직하다.In order to achieve the above object, according to the present invention, in the heat treatment process (annealing) that proceeds between the ion implantation process and the field oxidation process, by incorporating O 2 gas in the reaction chamber containing the N 2 gas localized on the surface of the polycrystalline silicon Si x N y formed to be suppressed. Here, N 2 gas: preferably from 5: O 2 gas = 100.

구체적으로 도2a, 2b를 참조하여 설명한다. 도2a를 보면, 다결정실리콘층(11)에 마스크용으로 쓰이는 질화막(Si3N4)(13)이 코팅된다. 질화막은 산화막보다 더 강도가 세기 때문에 소자 보호용이나 포토마스크용으로 많이 쓰인다. 도1a에서와 마찬가지로 가운데 빈 공간(F)은 필드(field)라고 부르는 영역으로서 소자와 소자의 경계영역으로서 두꺼운 산화막을 성장시킬 영역이다.Specifically, this will be described with reference to FIGS. 2A and 2B. Referring to FIG. 2A, a nitride film (Si 3 N 4 ) 13 used for a mask is coated on the polysilicon layer 11. Since the nitride film is more intense than the oxide film, it is used for device protection or photomask. As in FIG. 1A, the center empty space F is a region called a field and is a region in which a thick oxide film is grown as a boundary region between the device and the device.

종래에 이온주입후 고온에 의한 열처리를 하면 반응실 내에 있는 질소가스와 웨이퍼의 다결정실리콘이 반응하여 SixNy의 부정형 질화막이 국부적으로 형성되었음은 이미 설명하였다. 본 발명에서는 이온주입을 한 후 열처리를 할 때에, 반응실 내의 질소가스 이외에 산소(O2)가스도 함께 공급하여 이 문제를 해결하였다. 즉, 20ℓ의 질소가스가 존재하고 있는 반응실에 약 1ℓ의 산소가스를 투입하였다. 그러자 다결정실리콘의 표면에 SixNy가 형성되는 대신에 SiO2와 SiON층(15)이 형성되었다.In the related art, it has already been described that when annealing at high temperature after ion implantation causes nitrogen gas in the reaction chamber to react with polysilicon of a wafer, an amorphous nitride film of Si x N y is locally formed. In the present invention, this problem is solved by supplying oxygen (O 2 ) gas in addition to nitrogen gas in the reaction chamber when performing heat treatment after ion implantation. That is, about 1 liter of oxygen gas was introduced into the reaction chamber in which 20 liters of nitrogen gas exist. Then, instead of forming Si x N y on the surface of the polysilicon, SiO 2 and SiON layer 15 were formed.

이 층은 이후에 필드산화막을 성장시킬 때에 산화막 성장을 돕는 작용을 하기 때문에 도2b에서 보는 것과 같이 미성장결함이 없는 깨끗한 필드산화막(17)을 얻을 수 있었다.Since this layer serves to assist the oxide film growth when the field oxide film is grown later, a clean field oxide film 17 without ungrowth defects can be obtained as shown in FIG. 2B.

반응실에 투입하는 산소가스의 양은, 반응실 내에 존재하는 질소가스의 양의 약 3~8% 정도이어야 함이 실험적으로 결정되었는데, 약 5%일 때에 가장 효과가 컸다.It was experimentally determined that the amount of oxygen gas to be added to the reaction chamber should be about 3 to 8% of the amount of nitrogen gas present in the reaction chamber.

본 발명에 따르면, 간단한 공정상 추가로 필드산화막의 막질을 향상시킬 수 있기 때문에 소자의 수율을 높힐 수 있고 생산원가를 절감할 수 있다.According to the present invention, since the film quality of the field oxide film can be further improved in a simple process, the yield of the device can be increased and the production cost can be reduced.

Claims (2)

이온주입 공정과 필드산화 공정 사이에 진행되는 열처리 공정(annealing)에 있어서, N2가스가 포함되어 있는 반응실 내에 O2가스를 혼입시켜 다결정실리콘층에 국부적으로 형성되는 SixNy를 억제하는 것을 특징으로 하는 이온주입후 열처리 방법.In the annealing process performed between the ion implantation process and the field oxidation process, O 2 gas is mixed into the reaction chamber containing N 2 gas to suppress Si x N y formed locally in the polycrystalline silicon layer. Heat treatment method after ion implantation, characterized in that. 제1항에 있어서, N2가스:O2가스=100:5인 것을 특징으로 하는 이온주입후 열처리 방법.The method of claim 1, wherein the N 2 gas: O 2 gas is 100: 5.
KR1019980059825A 1998-12-29 1998-12-29 Annealing after ion implantation KR20000043446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980059825A KR20000043446A (en) 1998-12-29 1998-12-29 Annealing after ion implantation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980059825A KR20000043446A (en) 1998-12-29 1998-12-29 Annealing after ion implantation

Publications (1)

Publication Number Publication Date
KR20000043446A true KR20000043446A (en) 2000-07-15

Family

ID=19566701

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980059825A KR20000043446A (en) 1998-12-29 1998-12-29 Annealing after ion implantation

Country Status (1)

Country Link
KR (1) KR20000043446A (en)

Similar Documents

Publication Publication Date Title
US6905972B2 (en) Semiconductor device and method for manufacturing the same
US5998289A (en) Process for obtaining a transistor having a silicon-germanium gate
US6355580B1 (en) Ion-assisted oxidation methods and the resulting structures
US6316818B1 (en) Vertical bipolar transistor including an extrinsic base with reduced roughness, and fabrication process
KR100320796B1 (en) Method of manufacturing a semiconductor device utilizing a gate dielelctric
JPH05347249A (en) Low-temperature silicon epitaxial growth method
US6204205B1 (en) Using H2anneal to improve the electrical characteristics of gate oxide
JPS618931A (en) Manufacture of semiconductor device
JPH0437152A (en) Manufacture of semiconductor device
KR100400249B1 (en) Method for forming the MOS transistor in semiconductor device
KR100378688B1 (en) manufacturing method for semiconductor device
KR20000017498A (en) A controllable oxidation technique for high quality ultra-thin gate oxide
KR20000043446A (en) Annealing after ion implantation
KR100376886B1 (en) Method of manufacturing pmos transistor
KR100743620B1 (en) Method for forming shallow junction of semiconductor device
KR960009977B1 (en) Forming method of sacrificial oxide film for semiconductor device
KR0185985B1 (en) Method for forming epitaxial layer in silicon wafer
JPH07326750A (en) Semiconductor device and manufacture thereof
JPH06252388A (en) Fabrication of semiconductor device
JPH04330734A (en) Manufacture of semiconductor device
JPH04330733A (en) Manufacture of semiconductor device
JPH0442525A (en) Manufacture of semiconductor device
KR20020094963A (en) Method for gettering semiconductor device
KR19990027839A (en) Gate Forming Method for High Speed Semiconductor Devices
KR20010003578A (en) Method of forming a field oxide film in a semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination