KR20000042812A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
KR20000042812A
KR20000042812A KR1019980059094A KR19980059094A KR20000042812A KR 20000042812 A KR20000042812 A KR 20000042812A KR 1019980059094 A KR1019980059094 A KR 1019980059094A KR 19980059094 A KR19980059094 A KR 19980059094A KR 20000042812 A KR20000042812 A KR 20000042812A
Authority
KR
South Korea
Prior art keywords
insulating layer
hole
layer
semiconductor device
film
Prior art date
Application number
KR1019980059094A
Other languages
Korean (ko)
Inventor
김일구
황재성
유병덕
Original Assignee
윤종용
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1019980059094A priority Critical patent/KR20000042812A/en
Publication of KR20000042812A publication Critical patent/KR20000042812A/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to manufacture a semiconductor by using a Dual Damascene technique. CONSTITUTION: A method for manufacturing a semiconductor device comprises the following steps. A first insulating layer(102) and an etch barrier are formed on an upper portion of a lower conductive layer(100). A thin hole is formed by etching the etch barrier and the first insulating layer. A side wall insulating layer is formed at an inner portion of the thin hole in order to minimize or reduce a critical dimension of a via-hole. A second insulating layer(114) is formed on the etch barrier including the side wall insulating layer. A trench and the via-hole are formed on the second and the first insulating layers by etching the second insulating layer. A wiring(121) and a via-contact(123) are formed simultaneously by filling the trench and the via-hole with a conductive material.

Description

반도체 장치의 제조 방법Manufacturing Method of Semiconductor Device

본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 특히 이중-상감 기술을 이용한 반도체 장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a double damascene technique.

최근 반도체 장치가 고집적화됨에 따라 회로의 구조가 평면구조에서 수직구조로 변화되고 있으며, 이에 따라 배선의 구조도 다층화되고 있는 실정이다. 이처럼 반도체 장치의 배선 구조가 다층화됨에 따라 콘택홀의 종횡비(aspect ratio)가 증가되고 있어 종래의 배선 방법으로는 배선의 비평탄화, 불량한 스텝 커버리지(step coverage), 잔류성 금속 단락, 낮은 수율, 및 신뢰성의 열화 등과 같은 문제점들이 발생하게 된다.Recently, as semiconductor devices have been highly integrated, the circuit structure has been changed from a planar structure to a vertical structure. As a result, the structure of the wiring is also multilayered. As the wiring structure of the semiconductor device is multilayered, the aspect ratio of the contact hole increases, and thus, conventional wiring methods include uneven wiring, poor step coverage, residual metal short circuit, low yield, and reliability. Problems such as deterioration will occur.

따라서, 본 분야에서는 상기한 종래의 문제점들을 해결하기 위한 새로운 배선 기술로서 하부 배선과 상부 배선을 전기적으로 연결하는 비아콘택과 상부 배선을 동시에 형성하는 소위, "이중-상감(Dual Damascene)" 기술을 개발하게 되었으며, 이러한 이중-상감 기술은 현재 디램(DRAM)의 비트라인 및 다이렉트 콘택(Direct Contact)을 형성하거나, 에스램(SRAM)의 국부(local) 배선을 형성하는 공정에 널리 이용되고 있다. 또한, 향후 구리(Cu)를 이용한 초미세 배선을 형성함에 있어서 필수적으로 수행되어질 공정으로 전망되고 있다.Therefore, in this field, a so-called "Dual Damascene" technique for simultaneously forming a via contact and an upper interconnection electrically connecting the lower interconnection and the upper interconnection as a new interconnection technique for solving the above-described problems is employed. This dual-inlay technology is now widely used in the process of forming bit lines and direct contacts of DRAMs or local wiring of SRAMs. In addition, in the future, it is expected that the process to be essentially performed in forming ultra fine wiring using copper (Cu).

도 1은 종래 방법에 따른 이중-상감 공정을 나타내는 단면도이다. 도면을 참조하면, 하부도전막(예컨대 다결정실리콘, 알루미늄, 실리사이드등의 물질로 이루어진 도전막)(10) 상부에 비아홀 형성을 위한 제1절연막(12)을 형성한다. 예컨대, 상기 제1절연막은 TEOS(tetra-ethyl-ortho-silicate), PSG(Phosphorus Silicon Glass), BPSG(Boron Phosphorus Silicon Glass) 또는 USG(Undoped Silicon Glass)등으로 형성하는 것이 바람직하다. 이어서, 상기 제1절연막(12) 상부에 후속의 건식식각공정으로부터 상기 제1절연막(12)의 식각을 방지하기 위하여, 상기 제1절연막(12)과는 다른 물질인 SiON 또는 SiN의 질화막으로 이루어진 스토퍼막(14)을 형성한 뒤, 제1사진식각공정(건식식각공정)을 실시하여 비아콘택을 형성하기 위한 비아홀(16)을 형성한다. 그리고 나서, 상기 결과물의 상부에 배선용 트렌치를 형성하기 위한 제2절연막(18)을 증착한 뒤, 감광막(20)을 마스크로 이용하여 제2사진식각공정(건식식각공정)을 실시한다. 그 결과, 상기 제2절연막(18)에 트렌치(22)가 형성된다.1 is a cross-sectional view showing a dual-laid process according to the conventional method. Referring to the drawings, a first insulating film 12 for forming via holes is formed on the lower conductive film (eg, a conductive film made of a material such as polysilicon, aluminum, or silicide) 10. For example, the first insulating layer may be formed of tetra-ethyl-ortho-silicate (TEOS), Phosphorus Silicon Glass (PSG), Boron Phosphorus Silicon Glass (BPSG), or Undoped Silicon Glass (USG). Subsequently, in order to prevent etching of the first insulating layer 12 from a subsequent dry etching process on the first insulating layer 12, a nitride film of SiON or SiN, which is a different material from the first insulating layer 12, is formed. After the stopper film 14 is formed, a via hole 16 for forming a via contact is formed by performing a first photolithography process (dry etching process). Then, a second insulating film 18 for forming a wiring trench is deposited on the resultant, and then a second photolithography process (dry etching process) is performed using the photosensitive film 20 as a mask. As a result, a trench 22 is formed in the second insulating film 18.

그러나, 종래에는 트렌치(22)를 형성하기 위한 상기 제2사진식각공정에 사용되는 식각에천트에 대해 스토퍼막(14)의 식각선택비가 우수하지 못했으며, 식각공정시 발생되는 이온 스퍼터링(sputtering)으로 인해 비아홀(16)이 형성되어 있는 제1절연막(12)의 상부 모서리(참조부호 "a") 영역이 손상을 입게된다.However, conventionally, the etching selectivity of the stopper film 14 is not excellent with respect to the etching etchant used in the second photolithography process for forming the trench 22, and ion sputtering generated during the etching process is not excellent. As a result, the upper edge (reference numeral “a”) region of the first insulating layer 12 having the via hole 16 is damaged.

도 2는 손상된 상기 "a" 영역의 확대도이다. 도면을 참조하면, 상기 트렌치(22)를 형성하기 위한 제2사진식각공정에 의해 상기 제1절연막(12)의 프로파일이 변화된다. 즉, 이온 스퍼터링에 취약한 제1절연막(12)의 상부가 먼저 손상되며, 제2사진식각공정이 계속될 경우, 도면에 도시된 바와 같이 화살표 방향으로 식각이 진행되어 결국 최초 형성된 비아홀(16)의 임계치수가 변화하게 된다. 특히, 0.2㎛ 이하의 미세한 비아를 형성할 수 없게 되므로 반도체 장치의 고집적화를 이루는데 걸림돌이 되고 있다.2 is an enlarged view of the damaged "a" region. Referring to the drawings, the profile of the first insulating layer 12 is changed by a second photolithography process for forming the trench 22. That is, if the upper portion of the first insulating film 12, which is vulnerable to ion sputtering, is damaged first, and the second photolithography process is continued, the etching proceeds in the direction of the arrow as shown in the drawing, so that the via hole 16 is first formed. The critical dimension will change. In particular, since it is impossible to form fine vias of 0.2 μm or less, it is an obstacle to achieving high integration of the semiconductor device.

이러한 비아홀의 임계치수 변화를 막기 위해서 스토퍼막을 보다 두껍게 형성하는 방법이 시도되고 있으나, 절연막으로 이루어진 스토퍼막의 고유전율로 인해 기생 캐패시터가 증가되어 반도체 장치의 특성이 저하되는 단점이 있다.In order to prevent such a change in the critical dimension of the via hole, a method of forming a thicker stopper film has been attempted. However, due to the high dielectric constant of the stopper film made of an insulating film, parasitic capacitors are increased to deteriorate characteristics of the semiconductor device.

따라서 본 발명의 목적은, 상기한 종래의 문제점을 해소할 수 있는 개선된 이중-상감 공정 방법을 제공함에 있다.It is therefore an object of the present invention to provide an improved double-inlay process method that can solve the above-mentioned conventional problems.

본 발명의 다른 목적은, 비아홀의 임계치수를 변화시키지 않거나 임계치수를 보다 줄일 수 있는 개선된 이중-상감 공정 방법을 제공함에 있다.It is another object of the present invention to provide an improved dual-inlay process method that can not change the critical dimensions of via holes or further reduce the critical dimensions.

상기의 목적을 달성하기 위해서 본 발명에서는, 배선과 비아콘택을 동시에 구현하는 이중-상감 기술을 이용한 반도체 장치의 제조 방법에 있어서: 하부도전막 상부에 제1절연막 및 후속의 식각공정으로부터 상기 제1절연막의 손상을 방지하기 위해 상기 제1절연막과 우수한 식각선택비를 가지는 식각방지막을 차례로 형성하는 단계와; 상기 식각방지막을 패터닝한 뒤, 패터닝된 상기 식각방지막을 마스크로서 이용하여 상기 제1절연막을 일정두께 식각함으로써 얕은 홀을 형성하는 단계와; 상기 홀의 내부에 후속의 식각공정으로부터 상기 제1절연막이 손상되는 것을 방지하여 비아콘택이 형성되어질 비아홀의 임계치수 변화를 최소화하거나, 임계치수를 보다 줄이기 위하여 상기 제1절연막과 우수한 식각선택비를 가지는 측벽절연막을 형성하는 단계와; 상기 측벽절연막을 구비한 홀이 형성되어 있는 식각방지막 상에, 상기 측벽절연막 및 식각방지막과 우수한 식각선택비를 가지는 제2절연막을 형성한 뒤, 이를 식각하여 상기 제2절연막 및 제1절연막에 트렌치 및 비아홀을 각각 형성하는 단계와; 상기 트렌치 및 비아홀에 도전물질을 채움으로써 배선 및 비아콘택을 동시에 형성하는 단계를 포함함을 특징으로 하는 반도체 장치의 제조 방법을 제공한다.SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device using a double-inlay technique that simultaneously implements wiring and via contacts: a first insulating film on a lower conductive film and a subsequent etching process from a subsequent etching process. Sequentially forming an etch stop layer having an excellent etch selectivity with the first insulating layer to prevent damage to the insulating layer; Patterning the etch stop layer, and forming a shallow hole by etching the first insulating layer to a predetermined thickness by using the patterned etch stop layer as a mask; In order to prevent the first insulating layer from being damaged from a subsequent etching process in the hole, the first insulating layer has an excellent etching selectivity with the first insulating layer to minimize the change in the critical dimension of the via hole in which the via contact is to be formed or to further reduce the critical dimension. Forming a sidewall insulating film; A second insulating layer having an excellent etching selectivity with the sidewall insulating layer and the etch stop layer is formed on the etch stop layer on which the hole having the sidewall insulating layer is formed, and then etched to form a trench in the second insulating layer and the first insulating layer. And forming via holes, respectively; And forming a wiring and a via contact at the same time by filling a conductive material in the trench and via hole.

도 1은 종래 방법에 따른 이중-상감 공정을 나타내는 단면도1 is a cross-sectional view showing a double-inlay process according to a conventional method

도 2는 상기 도 1의 "a" 영역 확대도FIG. 2 is an enlarged view of region “a” of FIG. 1.

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 이중-상감 공정을 설명하기 위한 단면도들3A-3D are cross-sectional views illustrating a double-inlay process according to a preferred embodiment of the present invention.

이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3d는 바람직한 실시예에 따른 이중-상감 공정을 설명하기 위한 단면도들이다.3A-3D are cross-sectional views illustrating a double-inlay process according to a preferred embodiment.

도 3a를 참조하면, 다결정실리콘, 불순물이 도우프된 실리콘, 알루미늄 또는 실리사이드등으로 이루어진 하부도전막(100) 상부에 비아콘택용 비아홀이 형성되어질 제1절연막(102)으로서, 예컨대 PSG, BPSG 또는 USG를 증착한다. 그리고 나서, 후속의 식각공정으로부터 상기 제1절연막(102)의 손상을 방지하기 위해, 제1절연막(102)과는 우수한 식각선택비를 가지는 SiON(또는 SiN)으로 이루어진 스토퍼막(104)을 상기 제1절연막(102) 상에 형성한다. 이어서, 상기 스토퍼막(104) 상부에 제1감광막(106)을 형성한 뒤, 제1사진식각공정(건식식각공정)(108)을 실시하여 얕은 홀(110)을 형성한다. 보다 상세하게는, 상기 스토퍼막(104) 및 제1절연막(102)의 일부를 식각함으로써, 홀(110)을 형성한다. 또한, 상기 홀(110)은 얻고자 하는 비아콘택의 임계치수에 비해 보다 넓게 형성하는 것이 바람직하다.Referring to FIG. 3A, a first insulating layer 102 on which a via hole for via contact is to be formed is formed on the lower conductive layer 100 made of polycrystalline silicon, silicon doped with impurities, aluminum, or silicide, for example, PSG, BPSG, or the like. Deposit USG. Then, in order to prevent damage to the first insulating film 102 from the subsequent etching process, the stopper film 104 made of SiON (or SiN) having an excellent etching selectivity with the first insulating film 102 is It is formed on the first insulating film 102. Subsequently, after the first photoresist layer 106 is formed on the stopper layer 104, the first photolithography process (dry etching process) 108 is performed to form a shallow hole 110. More specifically, the hole 110 is formed by etching part of the stopper film 104 and the first insulating film 102. In addition, the hole 110 is preferably formed wider than the critical dimension of the via contact to be obtained.

도 3b를 참조하면, 상기 제1감광막(106)을 에싱(ashing) 처리등을 이용하여 완전히 제거한 뒤, 상기 홀(110)의 측벽에 상기 스토퍼막(104)과 동일한 물질이며, 상기 제1절연막(102)과는 식각선택비가 우수한 SiN 또는 SiON으로 이루어진 측벽절연막(112)을 형성한다. 이때, 상기 측벽절연막(112)은 상기 홀(110) 및 스토퍼막(104) 상에 절연막을 증착한 뒤, 이를 전면 에치백함으로써 형성할 수 있다.Referring to FIG. 3B, after the first photoresist layer 106 is completely removed using an ashing process or the like, the first insulating layer 104 is formed of the same material as that of the stopper layer 104 on the sidewall of the hole 110. A sidewall insulating film 112 made of SiN or SiON having an excellent etching selectivity with respect to 102 is formed. In this case, the sidewall insulating layer 112 may be formed by depositing an insulating layer on the hole 110 and the stopper layer 104 and then etching the entire surface.

계속해서, 상기 측벽절연막(112)이 형성되어 있는 홀(110) 및 스토퍼막(104) 상에 배선용 트렌치가 형성되어질 제2절연막(114)으로서 PSG, BPSG 또는 USG등과 같은 산화막을 증착한 뒤, 그 상부에 식각공정시 마스크로서 이용되어질 제2감광막(116)을 형성한다.Subsequently, an oxide film such as PSG, BPSG or USG is deposited as the second insulating film 114 on which the trench for wiring is to be formed on the hole 110 and the stopper film 104 on which the sidewall insulating film 112 is formed. A second photosensitive film 116 to be used as a mask in the etching process is formed on the upper portion.

도 3c를 참조하면, 제2감광막(116)이 형성되어 있는 상기 결과물에 제2사진식각공정(건식식각공정)(118)을 실시하여 배선이 형성되어질 트렌치(120) 및 비아콘택이 형성되어질 비아홀(122)을 동시에 형성한다.Referring to FIG. 3C, a second photolithography process (dry etching process) 118 is performed on the resultant product on which the second photoresist layer 116 is formed, to form a trench 120 and a via hole in which a via contact is to be formed. And 122 are formed at the same time.

이때, 상기 제2사진식각공정(118)을 실시하는 과정에서는 종래와 마찬가지로 이온 스퍼터링에 의해 참조부호 "b"로 나타낸 것과 같이 상기 스토퍼막(104) 및 측벽절연막(112)이 손상되어 그 두께는 다소 감소된다. 그러나, 본 발명에서는 TEOS, PSG, BPSG 또는 USG등과 같은 산화막으로 이루어진 상기 제1절연막(102) 및 제2절연막(114)과 식각선택비가 우수한 SiN 또는 SiON으로 이루어진 스토퍼막(104) 및 측벽절연막(112)으로 인해, 상기 제2사진식각공정(118)이 진행되는 동안 비아홀(122)의 임계치수가 변화되는 것이 방지되거나, 임계치수를 보다 줄일 수 있게 된다.At this time, in the process of performing the second photolithography process 118, the stopper film 104 and the sidewall insulating film 112 are damaged due to ion sputtering as indicated by reference numeral "b" as in the prior art. Somewhat reduced. However, in the present invention, the first insulating film 102 and the second insulating film 114 made of an oxide film such as TEOS, PSG, BPSG, or USG and the stopper film 104 and the sidewall insulating film made of SiN or SiON having excellent etching selectivity ( 112, the critical dimension of the via hole 122 may be prevented from being changed during the second photolithography process 118, or the critical dimension may be further reduced.

한편, 측벽절연막의 크기를 조절하여 비아홀의 면적을 조절할 수 있으므로, 보다 미세한 면적의 비아콘택을 얻고자 하는 경우에는 상기 측벽절연막의 크기를 증가시키는 것이 바람직하다.On the other hand, since the area of the via hole can be adjusted by adjusting the size of the sidewall insulating film, it is preferable to increase the size of the sidewall insulating film when obtaining a via contact having a finer area.

또한, 본 발명에 따른 이중-상감 공정에서는 상기 제1절연막 및 제2절연막으로서 유전율 3.0 이하인 저유전막(FOx, HSQ, HOSP 도는 Nano-glass등)을 사용할 경우에도 비아홀의 임계치수 변화없이 식각을 진행할 수 있는 잇점이 있다.In the double damascene process according to the present invention, even when a low dielectric film (FOx, HSQ, HOSP, or Nano-glass, etc.) having a dielectric constant of 3.0 or less is used as the first and second insulating layers, etching may be performed without changing the critical dimension of the via hole. There is an advantage to this.

도 3d를 참조하면, 상기 트렌치(120) 및 비아홀(122)에 전체적으로 텅스텐등의 금속막을 증착한다. 그리고 나서, CMP(Chemical Mechanical Polishing) 또는 에치백을 실시하여 배선(121) 및 비아콘택(123)을 형성하게 된다.Referring to FIG. 3D, a metal film such as tungsten is deposited on the trench 120 and the via hole 122 as a whole. Then, the chemical mechanical polishing (CMP) or etch back is performed to form the wiring 121 and the via contact 123.

이와 같이 본 발명에서는, 제1절연막(102) 및 제2절연막(114)과 우수한 식각선택비를 가지는 물질막을 이용하여 스토퍼막(104) 및 측벽절연막(112)을 형성함으로써, 최초 설정된 임계치수에 크게 달라지지 않거나, 임계치수가 보다 감소된 비아콘택(123)을 형성하게 된다.As described above, in the present invention, the stopper film 104 and the sidewall insulating film 112 are formed by using the material film having the excellent etching selectivity with the first insulating film 102 and the second insulating film 114, thereby achieving the threshold value initially set. The via contact 123 is not significantly changed or the critical dimension is further reduced.

상기한 바와 같이 본 발명에서는 배선과 비아콘택을 동시에 형성하는 이중-상감 공정을 실시함에 있어서, 하부도전막 상의 절연막 및 스토퍼막에 얕은 홀을 형성한 뒤, 상기 홀의 내부에 상기 절연막과는 우수한 식각선택비를 가지는 물질을 이용하여 측벽절연막을 형성한다. 상기와 같은 측벽절연막으로 인해 후속의 비아홀 형성을 위한 식각공정시, 상기 절연막의 손상이 방지되어 최초 설정된 비아홀의 임계치수가 변화되는 것을 방지할 수 있다. 또한, 임계치수를 보다 줄임으로써, 미세한 비아콘택을 형성할 수 있게 된다.As described above, in the present invention, a shallow hole is formed in the insulating film and the stopper film on the lower conductive film in the double-inlay process for simultaneously forming the wiring and the via contact. A sidewall insulating film is formed using a material having a selectivity. Due to the sidewall insulating layer as described above, in the subsequent etching process for forming the via hole, damage to the insulating layer may be prevented, thereby preventing the threshold dimension of the initially set via hole from being changed. In addition, by further reducing the critical dimension, it is possible to form a fine via contact.

Claims (5)

배선과 비아콘택을 동시에 구현하는 이중-상감 기술을 이용한 반도체 장치의 제조 방법에 있어서:A method of manufacturing a semiconductor device using a double-inlay technique for simultaneously implementing wiring and via contact: 하부도전막 상부에 제1절연막 및 후속의 식각공정으로부터 상기 제1절연막의 손상을 방지하기 위해 상기 제1절연막과 우수한 식각선택비를 가지는 식각방지막을 차례로 형성하는 단계와;Sequentially forming an etch stop layer having an excellent etch selectivity with the first insulating layer on the lower conductive layer to prevent damage to the first insulating layer and the first insulating layer from a subsequent etching process; 상기 식각방지막 및 제1절연막의 일정두께를 식각함으로써 얕은 홀을 형성하는 단계와;Forming a shallow hole by etching a predetermined thickness of the etch stop layer and the first insulating layer; 상기 홀의 내부에 후속의 식각공정으로부터 상기 제1절연막이 손상되는 것을 방지하여 비아콘택이 형성되어질 비아홀의 임계치수 변화를 최소화하거나, 임계치수를 보다 줄이기 위하여 상기 제1절연막과 우수한 식각선택비를 가지는 측벽절연막을 형성하는 단계와;In order to prevent the first insulating layer from being damaged from a subsequent etching process in the hole, the first insulating layer has an excellent etching selectivity with the first insulating layer to minimize the change in the critical dimension of the via hole in which the via contact is to be formed or to further reduce the critical dimension. Forming a sidewall insulating film; 상기 측벽절연막을 구비한 홀이 형성되어 있는 식각방지막 상에, 상기 측벽절연막 및 식각방지막과 우수한 식각선택비를 가지는 제2절연막을 형성한 뒤, 이를 식각하여 상기 제2절연막 및 제1절연막에 트렌치 및 비아홀을 각각 형성하는 단계와;A second insulating layer having an excellent etching selectivity with the sidewall insulating layer and the etch stop layer is formed on the etch stop layer on which the hole having the sidewall insulating layer is formed, and then etched to form a trench in the second insulating layer and the first insulating layer. And forming via holes, respectively; 상기 트렌치 및 비아홀에 도전물질을 채움으로써 배선 및 비아콘택을 동시에 형성하는 단계를 포함함을 특징으로 하는 반도체 장치의 제조 방법.And forming a wiring and a via contact at the same time by filling a conductive material in the trench and via hole. 제 1항에 있어서, 상기 제1절연막 및 제2절연막은 티이오에스, 피에스지, 비피에스지 또는 유에스지등의 산화막으로 이루어짐을 특징으로 하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are formed of an oxide film such as TOS, PS, BPS, or US paper. 제 2항에 있어서, 상기 측벽절연막을 SiON 또는 SiN으로 이루어짐을 특징으로 하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 2, wherein said sidewall insulating film is made of SiON or SiN. 제 3항에 있어서, 상기 스토퍼막은 SiON 또는 SiN으로 이루어짐을 특징으로 하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 3, wherein the stopper film is made of SiON or SiN. 제 4항에 있어서, 상기 트렌치 및 비아홀은 건식식각공정을 통해 형성됨을 특징으로 하는 반도체 장치의 제조 방법.The method of claim 4, wherein the trench and the via hole are formed through a dry etching process.
KR1019980059094A 1998-12-26 1998-12-26 Method for manufacturing semiconductor device KR20000042812A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980059094A KR20000042812A (en) 1998-12-26 1998-12-26 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980059094A KR20000042812A (en) 1998-12-26 1998-12-26 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20000042812A true KR20000042812A (en) 2000-07-15

Family

ID=19566065

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980059094A KR20000042812A (en) 1998-12-26 1998-12-26 Method for manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR20000042812A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100649410B1 (en) * 2000-07-21 2006-11-24 후지쯔 가부시끼가이샤 Semiconductor device and method manufacturing the same
CN113644024A (en) * 2021-07-27 2021-11-12 上海华力集成电路制造有限公司 Method for etching critical dimension of contact hole and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100649410B1 (en) * 2000-07-21 2006-11-24 후지쯔 가부시끼가이샤 Semiconductor device and method manufacturing the same
CN113644024A (en) * 2021-07-27 2021-11-12 上海华力集成电路制造有限公司 Method for etching critical dimension of contact hole and semiconductor device

Similar Documents

Publication Publication Date Title
KR100382729B1 (en) Metal contact structure in semiconductor device and forming method thereof
US6686247B1 (en) Self-aligned contacts to gates
US11594419B2 (en) Reduction of line wiggling
US6103616A (en) Method to manufacture dual damascene structures by utilizing short resist spacers
US20050200026A1 (en) Contact structure for nanometer characteristic dimensions
US6372631B1 (en) Method of making a via filled dual damascene structure without middle stop layer
CN113540096B (en) Static random access memory element and manufacturing method thereof
JP2000315777A (en) Self-alignment damascene interconnection
US20050275109A1 (en) Semiconductor device and fabricating method thereof
US6313029B1 (en) Method for forming multi-layer interconnection of a semiconductor device
KR100539444B1 (en) Method for forming a metal line in semiconductor device
US5869393A (en) Method for fabricating multi-level interconnection
US7651898B2 (en) Method for fabricating semiconductor device
TW202236707A (en) Semiconductor structure
KR20000042812A (en) Method for manufacturing semiconductor device
US6660650B1 (en) Selective aluminum plug formation and etchback process
US7084057B2 (en) Bit line contact structure and fabrication method thereof
US6690093B2 (en) Metal contact structure in semiconductor device and method for forming the same
KR20030058523A (en) Method for forming multi metal layer by dual damascene process
KR20000072897A (en) method of manufacturing semiconductor device
KR100784074B1 (en) Method of manufacturing bit line in a semiconductor device
KR100537187B1 (en) Method for fabrication of semiconductor device
KR100772077B1 (en) A method for forming contact hole of semiconductor device
KR20050003296A (en) Method for forming the semiconductor memory device having a self-aligned contact hole
KR0172725B1 (en) Multi-layer metal wire forming method of semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination