KR20000042812A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20000042812A
KR20000042812A KR19980059094A KR19980059094A KR20000042812A KR 20000042812 A KR20000042812 A KR 20000042812A KR 19980059094 A KR19980059094 A KR 19980059094A KR 19980059094 A KR19980059094 A KR 19980059094A KR 20000042812 A KR20000042812 A KR 20000042812A
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insulating film
method
etching
film
hole
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KR19980059094A
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Korean (ko)
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김일구
황재성
유병덕
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윤종용
삼성전자 주식회사
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to manufacture a semiconductor by using a Dual Damascene technique. CONSTITUTION: A method for manufacturing a semiconductor device comprises the following steps. A first insulating layer(102) and an etch barrier are formed on an upper portion of a lower conductive layer(100). A thin hole is formed by etching the etch barrier and the first insulating layer. A side wall insulating layer is formed at an inner portion of the thin hole in order to minimize or reduce a critical dimension of a via-hole. A second insulating layer(114) is formed on the etch barrier including the side wall insulating layer. A trench and the via-hole are formed on the second and the first insulating layers by etching the second insulating layer. A wiring(121) and a via-contact(123) are formed simultaneously by filling the trench and the via-hole with a conductive material.

Description

반도체 장치의 제조 방법 A method of manufacturing a semiconductor device

본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 특히 이중-상감 기술을 이용한 반도체 장치의 제조 방법에 관한 것이다. A method of manufacturing a semiconductor device using a damascene technique - the present invention, especially double relates to a method for manufacturing a semiconductor device.

최근 반도체 장치가 고집적화됨에 따라 회로의 구조가 평면구조에서 수직구조로 변화되고 있으며, 이에 따라 배선의 구조도 다층화되고 있는 실정이다. Recently as a semiconductor device is highly integrated, and the structure of the circuit change in the planar structure in a vertical structure, a situation which is also a multilayer structure of wiring accordingly. 이처럼 반도체 장치의 배선 구조가 다층화됨에 따라 콘택홀의 종횡비(aspect ratio)가 증가되고 있어 종래의 배선 방법으로는 배선의 비평탄화, 불량한 스텝 커버리지(step coverage), 잔류성 금속 단락, 낮은 수율, 및 신뢰성의 열화 등과 같은 문제점들이 발생하게 된다. Thus, it increases the aspect ratio (aspect ratio) of holes a contact as a wiring structure of a semiconductor device layered in the conventional wiring method will review carbonization of wiring, poor step coverage (step coverage), residual metal short circuit, low yield, and reliability It will arise problems such as deterioration.

따라서, 본 분야에서는 상기한 종래의 문제점들을 해결하기 위한 새로운 배선 기술로서 하부 배선과 상부 배선을 전기적으로 연결하는 비아콘택과 상부 배선을 동시에 형성하는 소위, "이중-상감(Dual Damascene)" 기술을 개발하게 되었으며, 이러한 이중-상감 기술은 현재 디램(DRAM)의 비트라인 및 다이렉트 콘택(Direct Contact)을 형성하거나, 에스램(SRAM)의 국부(local) 배선을 형성하는 공정에 널리 이용되고 있다. Accordingly, the art in the lower wiring and via contact for connecting the upper wiring is electrically and so-called forming the upper wires at the same time, a new interconnection technique to solve the above conventional problems - the "dual damascene (Dual Damascene)" Technology It was developed, such a dual-damascene technique is widely used in the step of forming a local (local) wiring of the current dynamic random access memory (DRAM) bit line and a direct contact (direct contact) in the formation, or S RAM (SRAM) of. 또한, 향후 구리(Cu)를 이용한 초미세 배선을 형성함에 있어서 필수적으로 수행되어질 공정으로 전망되고 있다. Further, the process is expected to be essentially carried out as in the next forming an ultrafine wire with copper (Cu).

도 1은 종래 방법에 따른 이중-상감 공정을 나타내는 단면도이다. Figure 1 is the double of the conventional method - a cross-sectional view showing a damascene process. 도면을 참조하면, 하부도전막(예컨대 다결정실리콘, 알루미늄, 실리사이드등의 물질로 이루어진 도전막)(10) 상부에 비아홀 형성을 위한 제1절연막(12)을 형성한다. Referring to the figures, the lower conductive film (for example, made of a material such as polysilicon, aluminum, a silicide conductive layer) 10 to form a first insulating film 12 for forming a via hole thereon. 예컨대, 상기 제1절연막은 TEOS(tetra-ethyl-ortho-silicate), PSG(Phosphorus Silicon Glass), BPSG(Boron Phosphorus Silicon Glass) 또는 USG(Undoped Silicon Glass)등으로 형성하는 것이 바람직하다. For example, it is preferable to form the first insulating layer is TEOS (tetra-ethyl-ortho-silicate), PSG (Phosphorus Silicon Glass), BPSG (Boron Phosphorus Silicon Glass) or USG (Undoped Silicon Glass) or the like. 이어서, 상기 제1절연막(12) 상부에 후속의 건식식각공정으로부터 상기 제1절연막(12)의 식각을 방지하기 위하여, 상기 제1절연막(12)과는 다른 물질인 SiON 또는 SiN의 질화막으로 이루어진 스토퍼막(14)을 형성한 뒤, 제1사진식각공정(건식식각공정)을 실시하여 비아콘택을 형성하기 위한 비아홀(16)을 형성한다. Then, the first insulating film (12) to prevent the etching of the first insulating film 12 from the subsequent dry etching process of the upper, the first insulating film 12 and is made of a nitride film of a different substance, SiON or SiN after the formation of the stopper film 14, subjected to a first photo etching process (dry etching process) to form a via hole 16 for forming a via contact. 그리고 나서, 상기 결과물의 상부에 배선용 트렌치를 형성하기 위한 제2절연막(18)을 증착한 뒤, 감광막(20)을 마스크로 이용하여 제2사진식각공정(건식식각공정)을 실시한다. Then, we perform a second photolithography process (dry etching process) after depositing the second upper insulating film 18 for forming a wiring trench in, using the photoresist 20 as a mask of the resultant product. 그 결과, 상기 제2절연막(18)에 트렌치(22)가 형성된다. As a result, a trench 22 is formed on the second insulating film 18.

그러나, 종래에는 트렌치(22)를 형성하기 위한 상기 제2사진식각공정에 사용되는 식각에천트에 대해 스토퍼막(14)의 식각선택비가 우수하지 못했으며, 식각공정시 발생되는 이온 스퍼터링(sputtering)으로 인해 비아홀(16)이 형성되어 있는 제1절연막(12)의 상부 모서리(참조부호 "a") 영역이 손상을 입게된다. However, ion Conventionally that it did not excellent etching selectivity of the stopper film 14 for the etchant to the etching used in the second photolithography process for forming the trench 22, the ratio, generated during the etching process, the sputtering (sputtering) due to wear it is the upper edge (reference symbol "a") area, the damage of the first insulating film 12 in the via hole 16 is formed.

도 2는 손상된 상기 "a" 영역의 확대도이다. Figure 2 is an enlarged view of the damaged "a" region. 도면을 참조하면, 상기 트렌치(22)를 형성하기 위한 제2사진식각공정에 의해 상기 제1절연막(12)의 프로파일이 변화된다. Referring to the figures, by a second photolithography process for forming the trench 22, the profile of the first insulating film 12 is changed. 즉, 이온 스퍼터링에 취약한 제1절연막(12)의 상부가 먼저 손상되며, 제2사진식각공정이 계속될 경우, 도면에 도시된 바와 같이 화살표 방향으로 식각이 진행되어 결국 최초 형성된 비아홀(16)의 임계치수가 변화하게 된다. That is, the upper portion of the weak first insulating film 12 to the ion sputtering and damaged first, a second photolithography when the process is to continue, a via hole 16 is etched is in progress in the direction of the arrow to end the first formed as shown in the drawing threshold number is changed. 특히, 0.2㎛ 이하의 미세한 비아를 형성할 수 없게 되므로 반도체 장치의 고집적화를 이루는데 걸림돌이 되고 있다. In particular, not be able to form a fine via the following 0.2㎛ therefore been a stumbling block in achieving a high integration of the semiconductor device.

이러한 비아홀의 임계치수 변화를 막기 위해서 스토퍼막을 보다 두껍게 형성하는 방법이 시도되고 있으나, 절연막으로 이루어진 스토퍼막의 고유전율로 인해 기생 캐패시터가 증가되어 반도체 장치의 특성이 저하되는 단점이 있다. In order to prevent such a via hole, but the threshold value may change in a method of forming thicker film is attempted stopper, the stopper is due to the high dielectric constant film made of insulating film increases, the parasitic capacitor has a disadvantage that the characteristics of the semiconductor device is decreased.

따라서 본 발명의 목적은, 상기한 종래의 문제점을 해소할 수 있는 개선된 이중-상감 공정 방법을 제공함에 있다. It is therefore an object of the present invention, a dual improvement that can solve the aforementioned conventional problems - has an inlaid process method to provide.

본 발명의 다른 목적은, 비아홀의 임계치수를 변화시키지 않거나 임계치수를 보다 줄일 수 있는 개선된 이중-상감 공정 방법을 제공함에 있다. It is another object of the present invention, the threshold value does not change the number of the via-hole improvement in the threshold value could be less than the dual-damascene process is a method to provide.

상기의 목적을 달성하기 위해서 본 발명에서는, 배선과 비아콘택을 동시에 구현하는 이중-상감 기술을 이용한 반도체 장치의 제조 방법에 있어서: 하부도전막 상부에 제1절연막 및 후속의 식각공정으로부터 상기 제1절연막의 손상을 방지하기 위해 상기 제1절연막과 우수한 식각선택비를 가지는 식각방지막을 차례로 형성하는 단계와; In the present invention, in order to achieve the above object, a double implementing the wiring and the via contact at the same time - according to the method of manufacturing a semiconductor device using a damascene technique: a lower conductive film top from the etching process of the first insulating film and the subsequent first in order to avoid damage to the insulating film and forming an etching film having the first insulating film and the excellent etching selectivity in turn; 상기 식각방지막을 패터닝한 뒤, 패터닝된 상기 식각방지막을 마스크로서 이용하여 상기 제1절연막을 일정두께 식각함으로써 얕은 홀을 형성하는 단계와; Forming a shallow hole by etching a certain thickness of the first insulating film using the patterned film after the etching, the patterned film as the etching mask and; 상기 홀의 내부에 후속의 식각공정으로부터 상기 제1절연막이 손상되는 것을 방지하여 비아콘택이 형성되어질 비아홀의 임계치수 변화를 최소화하거나, 임계치수를 보다 줄이기 위하여 상기 제1절연막과 우수한 식각선택비를 가지는 측벽절연막을 형성하는 단계와; Minimize subsequent wherein the critical dimension variation of the via hole to be formed in the via contact to prevent the damage to the first insulating film from the etching process in the inside of the hole, or to reduce more the number of the threshold value having the first insulating film and the excellent etching selectivity forming a side wall insulating film and; 상기 측벽절연막을 구비한 홀이 형성되어 있는 식각방지막 상에, 상기 측벽절연막 및 식각방지막과 우수한 식각선택비를 가지는 제2절연막을 형성한 뒤, 이를 식각하여 상기 제2절연막 및 제1절연막에 트렌치 및 비아홀을 각각 형성하는 단계와; On the etching-barrier film that has a hole having the side wall insulating film is formed, after forming a second insulating film having the side wall insulating film and the etching film and the excellent etch selectivity, and etch them trench in the second insulating film and the first insulating layer forming a via hole, and each of the; 상기 트렌치 및 비아홀에 도전물질을 채움으로써 배선 및 비아콘택을 동시에 형성하는 단계를 포함함을 특징으로 하는 반도체 장치의 제조 방법을 제공한다. It provides a method for manufacturing a semiconductor device which is characterized in that it comprises the step of forming a wiring and a via contact at the same time by filling the conductive material in the trenches and via holes.

도 1은 종래 방법에 따른 이중-상감 공정을 나타내는 단면도 Figure 1 is the double of the conventional method - a cross-sectional view showing a damascene process

도 2는 상기 도 1의 "a" 영역 확대도 Figure 2 is an enlarged view of the FIG. "A" area of ​​the

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 이중-상감 공정을 설명하기 위한 단면도들 Figures 3a to 3d is a double of the preferred embodiment of the present invention - the cross-sectional view illustrating a damascene process

이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명하고자 한다. With reference to the accompanying drawings preferred embodiments of the present invention will be described in detail.

도 3a 내지 도 3d는 바람직한 실시예에 따른 이중-상감 공정을 설명하기 위한 단면도들이다. Figures 3a to 3d is a double of the preferred embodiment - are sectional views illustrating a damascene process.

도 3a를 참조하면, 다결정실리콘, 불순물이 도우프된 실리콘, 알루미늄 또는 실리사이드등으로 이루어진 하부도전막(100) 상부에 비아콘택용 비아홀이 형성되어질 제1절연막(102)으로서, 예컨대 PSG, BPSG 또는 USG를 증착한다. Referring to Figure 3a, a polysilicon, a shadow profile of the silicon impurities, aluminum or a silicide such as a lower conductive layer 100, the first insulating film 102 to be the for a via contact via hole in the upper form consisting of, e.g., PSG, BPSG, or the deposition of USG. 그리고 나서, 후속의 식각공정으로부터 상기 제1절연막(102)의 손상을 방지하기 위해, 제1절연막(102)과는 우수한 식각선택비를 가지는 SiON(또는 SiN)으로 이루어진 스토퍼막(104)을 상기 제1절연막(102) 상에 형성한다. Then, the a SiON stopper film 104 made of (or SiN), with the excellent etching selectivity with the first insulating film 102, a non order to avoid damage of the first insulating film 102 from a subsequent etching process of the the forming on the first insulating film 102. 이어서, 상기 스토퍼막(104) 상부에 제1감광막(106)을 형성한 뒤, 제1사진식각공정(건식식각공정)(108)을 실시하여 얕은 홀(110)을 형성한다. Then, a first photoresist layer 106, a back, a first photolithography process carried out by the (dry etching process) 108 is a shallow hole 110 formed to the upper portion of the stopper film 104. 보다 상세하게는, 상기 스토퍼막(104) 및 제1절연막(102)의 일부를 식각함으로써, 홀(110)을 형성한다. More specifically, by etching a portion of the film 104 and the first insulating film 102 and the stopper, thereby forming a hole (110). 또한, 상기 홀(110)은 얻고자 하는 비아콘택의 임계치수에 비해 보다 넓게 형성하는 것이 바람직하다. Further, it is preferable to form more widely than that of the hole 110 is of a via contact threshold value to be obtained.

도 3b를 참조하면, 상기 제1감광막(106)을 에싱(ashing) 처리등을 이용하여 완전히 제거한 뒤, 상기 홀(110)의 측벽에 상기 스토퍼막(104)과 동일한 물질이며, 상기 제1절연막(102)과는 식각선택비가 우수한 SiN 또는 SiON으로 이루어진 측벽절연막(112)을 형성한다. Referring to Figure 3b, the side wall of the first photoresist layer 106, the ashing (ashing) back completely removed by using a process, the hole 110 is the same material as that of the stopper film 104, the first insulating film 102, and forms a side wall insulating film 112 made of SiN or SiON high etching selection ratio. 이때, 상기 측벽절연막(112)은 상기 홀(110) 및 스토퍼막(104) 상에 절연막을 증착한 뒤, 이를 전면 에치백함으로써 형성할 수 있다. At this time, after the side wall insulating film 112 is deposited an insulating film on the hole 110 and the stopper film 104 can be formed by etching back it to the front.

계속해서, 상기 측벽절연막(112)이 형성되어 있는 홀(110) 및 스토퍼막(104) 상에 배선용 트렌치가 형성되어질 제2절연막(114)으로서 PSG, BPSG 또는 USG등과 같은 산화막을 증착한 뒤, 그 상부에 식각공정시 마스크로서 이용되어질 제2감광막(116)을 형성한다. After continuously, depositing an oxide film such as PSG, BPSG or USG as the side wall insulating film a second insulating film 114 to be the wiring trench formed on a 112, a hole 110 and a stopper film 104 is formed, to form a second photoresist layer 116 to be used as a mask during etching processes thereon.

도 3c를 참조하면, 제2감광막(116)이 형성되어 있는 상기 결과물에 제2사진식각공정(건식식각공정)(118)을 실시하여 배선이 형성되어질 트렌치(120) 및 비아콘택이 형성되어질 비아홀(122)을 동시에 형성한다. Referring to Figure 3c, a second photolithography process (dry etching process) to carry out 118 a via hole to be the trench 120 and the via contact to be the wiring is formed on the resultant product in second photoresist layer 116 is formed to form 122 simultaneously.

이때, 상기 제2사진식각공정(118)을 실시하는 과정에서는 종래와 마찬가지로 이온 스퍼터링에 의해 참조부호 "b"로 나타낸 것과 같이 상기 스토퍼막(104) 및 측벽절연막(112)이 손상되어 그 두께는 다소 감소된다. At this time, the second in the course of performing photolithography process 118 is the stopper film 104 and the side wall insulating film 112 is damaged, as indicated by reference numeral "b" by ion sputtering, as in the prior art has a thickness It is decreased. 그러나, 본 발명에서는 TEOS, PSG, BPSG 또는 USG등과 같은 산화막으로 이루어진 상기 제1절연막(102) 및 제2절연막(114)과 식각선택비가 우수한 SiN 또는 SiON으로 이루어진 스토퍼막(104) 및 측벽절연막(112)으로 인해, 상기 제2사진식각공정(118)이 진행되는 동안 비아홀(122)의 임계치수가 변화되는 것이 방지되거나, 임계치수를 보다 줄일 수 있게 된다. However, in the present invention, the first insulating film 102 and the second insulating film 114, a stopper film 104 and the etching selection ratio consisting of excellent SiN or SiON and a side wall insulating film made of an oxide film such as TEOS, PSG, BPSG or USG ( 112) as a result, the second photolithography process 118 is prevented from being the number of the threshold value of the via hole 122 is changed during the progress, or it is possible to more reduce the number of thresholds.

한편, 측벽절연막의 크기를 조절하여 비아홀의 면적을 조절할 수 있으므로, 보다 미세한 면적의 비아콘택을 얻고자 하는 경우에는 상기 측벽절연막의 크기를 증가시키는 것이 바람직하다. On the other hand, when to adjust the size of the side wall insulating film can control the area of ​​the via holes to be obtained for the via-contact area of ​​the finer, it is preferable to increase the size of the side wall insulating film.

또한, 본 발명에 따른 이중-상감 공정에서는 상기 제1절연막 및 제2절연막으로서 유전율 3.0 이하인 저유전막(FOx, HSQ, HOSP 도는 Nano-glass등)을 사용할 경우에도 비아홀의 임계치수 변화없이 식각을 진행할 수 있는 잇점이 있다. In addition, double of the present invention damascene process, the first or lower dielectric constant 3.0 as the first insulating film and second insulating film low dielectric proceed with etching without the critical dimension variation of the via-hole even when using (FOx, HSQ, HOSP turn Nano-glass, etc.) It has the advantage that you can.

도 3d를 참조하면, 상기 트렌치(120) 및 비아홀(122)에 전체적으로 텅스텐등의 금속막을 증착한다. Referring to Figure 3d, a whole depositing a metal film such as tungsten on the trench 120 and the via hole 122. 그리고 나서, CMP(Chemical Mechanical Polishing) 또는 에치백을 실시하여 배선(121) 및 비아콘택(123)을 형성하게 된다. Then, by performing a CMP (Chemical Mechanical Polishing) or etch-back to form the wiring 121 and the via contact 123.

이와 같이 본 발명에서는, 제1절연막(102) 및 제2절연막(114)과 우수한 식각선택비를 가지는 물질막을 이용하여 스토퍼막(104) 및 측벽절연막(112)을 형성함으로써, 최초 설정된 임계치수에 크게 달라지지 않거나, 임계치수가 보다 감소된 비아콘택(123)을 형성하게 된다. In this way form a pattern, a first insulating film 102 and the second insulating film 114 and the high etching selectivity, the stopper film 104 by using material film having and a side wall insulating film 112 in the invention, a first number of predetermined threshold It does not change much, the threshold number to form the via contact 123 is reduced more.

상기한 바와 같이 본 발명에서는 배선과 비아콘택을 동시에 형성하는 이중-상감 공정을 실시함에 있어서, 하부도전막 상의 절연막 및 스토퍼막에 얕은 홀을 형성한 뒤, 상기 홀의 내부에 상기 절연막과는 우수한 식각선택비를 가지는 물질을 이용하여 측벽절연막을 형성한다. Dual forming a wiring and a via contact in the present invention, at the same time as described above - in practicing the damascene process, after forming a shallow hole in an insulating film and a stopper film on the lower conductive layer, it is excellent etching the inside of the hole above the insulating film by using a material having a selected ratio to form a side wall insulating film. 상기와 같은 측벽절연막으로 인해 후속의 비아홀 형성을 위한 식각공정시, 상기 절연막의 손상이 방지되어 최초 설정된 비아홀의 임계치수가 변화되는 것을 방지할 수 있다. When the etching process for the subsequent formation of the via hole because of the side wall insulating film as described above, is prevented from the damage of the insulating film it can be prevented from being set threshold number of changes in the first via hole. 또한, 임계치수를 보다 줄임으로써, 미세한 비아콘택을 형성할 수 있게 된다. In addition, by reducing the number than the threshold, it is possible to form a fine via contact.

Claims (5)

  1. 배선과 비아콘택을 동시에 구현하는 이중-상감 기술을 이용한 반도체 장치의 제조 방법에 있어서: A method for fabricating a semiconductor device using a damascene technique - double that implements the wiring and the via contact at the same time:
    하부도전막 상부에 제1절연막 및 후속의 식각공정으로부터 상기 제1절연막의 손상을 방지하기 위해 상기 제1절연막과 우수한 식각선택비를 가지는 식각방지막을 차례로 형성하는 단계와; In order to avoid damage of the first insulating film from the etching process of the first insulating film and subsequently to the lower conductive layer and an upper etching step of forming a film with the first insulating film and the excellent etching selectivity in turn;
    상기 식각방지막 및 제1절연막의 일정두께를 식각함으로써 얕은 홀을 형성하는 단계와; Forming a shallow hole by etching a predetermined thickness of said etching-barrier film and the first insulating film and;
    상기 홀의 내부에 후속의 식각공정으로부터 상기 제1절연막이 손상되는 것을 방지하여 비아콘택이 형성되어질 비아홀의 임계치수 변화를 최소화하거나, 임계치수를 보다 줄이기 위하여 상기 제1절연막과 우수한 식각선택비를 가지는 측벽절연막을 형성하는 단계와; Minimize subsequent wherein the critical dimension variation of the via hole to be formed in the via contact to prevent the damage to the first insulating film from the etching process in the inside of the hole, or to reduce more the number of the threshold value having the first insulating film and the excellent etching selectivity forming a side wall insulating film and;
    상기 측벽절연막을 구비한 홀이 형성되어 있는 식각방지막 상에, 상기 측벽절연막 및 식각방지막과 우수한 식각선택비를 가지는 제2절연막을 형성한 뒤, 이를 식각하여 상기 제2절연막 및 제1절연막에 트렌치 및 비아홀을 각각 형성하는 단계와; On the etching-barrier film that has a hole having the side wall insulating film is formed, after forming a second insulating film having the side wall insulating film and the etching film and the excellent etch selectivity, and etch them trench in the second insulating film and the first insulating layer forming a via hole, and each of the;
    상기 트렌치 및 비아홀에 도전물질을 채움으로써 배선 및 비아콘택을 동시에 형성하는 단계를 포함함을 특징으로 하는 반도체 장치의 제조 방법. A semiconductor device manufacturing method characterized by comprising the step of forming a wiring and a via contact at the same time by filling the conductive material in the trenches and via holes.
  2. 제 1항에 있어서, 상기 제1절연막 및 제2절연막은 티이오에스, 피에스지, 비피에스지 또는 유에스지등의 산화막으로 이루어짐을 특징으로 하는 반도체 장치의 제조 방법. The method of claim 1, wherein the method of manufacturing a semiconductor device, characterized by the first insulating film and second insulating film is constituted by any of the OS Chantilly, PS resin, or bipyridinium eseuji US not including the oxide film.
  3. 제 2항에 있어서, 상기 측벽절연막을 SiON 또는 SiN으로 이루어짐을 특징으로 하는 반도체 장치의 제조 방법. The method of claim 2 wherein the method of manufacturing a semiconductor device, characterized by yirueojim the side wall insulating film as SiON or SiN.
  4. 제 3항에 있어서, 상기 스토퍼막은 SiON 또는 SiN으로 이루어짐을 특징으로 하는 반도체 장치의 제조 방법. The method of claim 3 wherein the method of manufacturing a semiconductor device characterized in that the stopper film is constituted by any SiON or SiN.
  5. 제 4항에 있어서, 상기 트렌치 및 비아홀은 건식식각공정을 통해 형성됨을 특징으로 하는 반도체 장치의 제조 방법. The method of claim 4 wherein the method for manufacturing a semiconductor device characterized by the trench and the via hole formed through the dry etching process.
KR19980059094A 1998-12-26 1998-12-26 Method for manufacturing semiconductor device KR20000042812A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100649410B1 (en) * 2000-07-21 2006-11-24 후지쯔 가부시끼가이샤 Semiconductor device and method manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100649410B1 (en) * 2000-07-21 2006-11-24 후지쯔 가부시끼가이샤 Semiconductor device and method manufacturing the same

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