KR20000027652A - Photoelectric devices and method for manufacturing photoelectric devices - Google Patents
Photoelectric devices and method for manufacturing photoelectric devices Download PDFInfo
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- KR20000027652A KR20000027652A KR1019980045609A KR19980045609A KR20000027652A KR 20000027652 A KR20000027652 A KR 20000027652A KR 1019980045609 A KR1019980045609 A KR 1019980045609A KR 19980045609 A KR19980045609 A KR 19980045609A KR 20000027652 A KR20000027652 A KR 20000027652A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 98
- 239000010703 silicon Substances 0.000 claims abstract description 97
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 57
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 47
- 229910003811 SiGeC Inorganic materials 0.000 claims abstract description 26
- 239000010409 thin film Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000007943 implant Substances 0.000 claims abstract description 16
- 239000010408 film Substances 0.000 claims description 39
- 230000005693 optoelectronics Effects 0.000 claims description 15
- 230000007547 defect Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000010791 quenching Methods 0.000 claims description 4
- 230000000171 quenching effect Effects 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000348 solid-phase epitaxy Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035209—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures
- H01L31/035218—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures the quantum structure being quantum dots
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
- H01L31/125—Composite devices with photosensitive elements and electroluminescent elements within one single body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/0004—Devices characterised by their operation
- H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
Abstract
Description
본 발명은 실리콘 기판상에 SiGe 양자우물구조를 이용한 적외선용 광전소자 및 그 제조방법에 관한 것이다.The present invention relates to an infrared photoelectric device using a SiGe quantum well structure on a silicon substrate and a method of manufacturing the same.
SiGe 이형구조는 기존의 실리콘 기술을 이용한 고집적화, 고속화의 기술이 발달함에 따라 그 한계점을 돌파하고자 새로이 개발되는 분야이다. SiGe 기술은 크게 두가지 기술로 나뉘는데 그 하나는 SiGe 이형접합에서 스트레인을 이용한 높은 이동도 특성을 사용하여 FET의 특성 향상에 사용하거나 HBT특성을 이용한 고속, 고이득특성 등의 전자소자의 특성 향상에 사용된다. 또다른 한가지 사용처는 SiGe 소자의 낮은 밴드 갭을 이용한 적외선 광 센서, 높은 굴절율 특성을 이용한 웨이브가이드(WAVEGUIDE) 구조 등의 광학 소자용으로 사용되는 분야이다. 이와같은 SiGe 특성은 구조 MBE와 같은 박막성장장치를 이용하는 방법, 임플란트(Implant) 방식을 이용하여 Ge를 Si 기판내에 투입하는 고상 성장(Solid Phase Epitaxy) 방법이 사용되고 있다. 그러나 Si과 Ge은 그 격자상수가 약 3%가량으로 차이를 보이며 이로 인해 심한 스트레인이 발생하게 되는데 스트레인의 양을 조절함으로써 밴드갭의 구조 조절이 가능해 지게 되었다. 최근에는 1.3㎛대역의 일렉트로 루미니센스(ELECTRO LUMINESCENCE) 특성이 발표되고 있으며 박막성장 기술의 발전에 따라 소자의 발광효율이 증가하는 추세에 있다.SiGe release structure is a newly developed field to overcome the limitations as the technology of high integration and high speed using existing silicon technology is developed. SiGe technology is largely divided into two technologies, one of which is used to improve the characteristics of FET using high mobility characteristics using strain in SiGe heterojunction, or to improve the characteristics of electronic devices such as high speed and high gain using HBT characteristics. do. Another use is in the field of use for optical devices such as infrared light sensors using the low band gap of SiGe devices, and waveguide structures using the high refractive index. Such SiGe characteristics include a method using a thin film growth apparatus such as a structural MBE, and a solid phase epitaxy method in which Ge is introduced into a Si substrate using an implant method. However, Si and Ge have a lattice constant of about 3%, which causes severe strain, and by adjusting the amount of strain, the band gap structure can be controlled. Recently, the ELECTRO LUMINESCENCE characteristic of 1.3 mu m band has been announced and the luminous efficiency of the device is increasing with the development of thin film growth technology.
그러나 현재까지 사용되는 구조는 이러한 소자의 발달에 미치지 못하고 있다. 도1a, 도1b는 기존의 방법에 의해 제조된 웨이브가이드 구조를 도시한 것이다.However, the structure used to date has not reached the development of these devices. 1A and 1B show a waveguide structure manufactured by a conventional method.
도1a는 실리콘 기판상에 굴절율이 높은 SiGe 합금층을 도입하여 평면 도파로 구조를 형성하는 것을 도시하는 것으로, 실리콘 기판(31), SiGe 합금층(32) 및 실리콘층(33)으로 적층된 것을 알수가 있다.FIG. 1A illustrates the formation of a planar waveguide structure by introducing a SiGe alloy layer having a high refractive index on a silicon substrate, and it can be seen that the silicon substrate 31 is stacked with the SiGe alloy layer 32 and the silicon layer 33. There is.
또한 더욱 발전된 구조로서 도1b는 실리콘 기판(31), SiGe 합금층(32) 및 실리콘층(33)으로 적층된 구조에서 LOCOS 공정 등으로 굴절율이 낮은 실리콘 산화막(34)을 국부적으로 형성하여 횡방향으로의 광도파특성도 함께 얻을 수 있는 구조이다.In addition, as a more advanced structure, FIG. 1B shows a silicon oxide film 34 having a low refractive index locally formed by a LOCOS process or the like in a structure in which a silicon substrate 31, a SiGe alloy layer 32, and a silicon layer 33 are stacked in the transverse direction. The optical waveguide characteristic can also be obtained.
그러나 지금까지는 단일소자의 구조수준을 벗어나지 못하고 있으며 여러 가지 소자들을 한 기판내에 제작하는 기술이 발달되지 못하고 있다. 본 특허에서는 효율적으로 광전소자의 집적을 구현하기 위한 구조를 제안하였다.However, until now, the structure of a single device has not escaped, and technology for manufacturing various devices in one substrate has not been developed. In this patent, a structure for efficiently integrating an optoelectronic device has been proposed.
따라서 본 발명은 앞에서 설명한 바와 같이 광전소자의 집적화를 구현하기 위하여 SiGe/SiGeC 수퍼래티스(SUPERLATTICE) 기술을 이용한 광전 소자 및 그 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide an optoelectronic device using the SiGe / SiGeC superlattice (SUPERLATTICE) technology and a method of manufacturing the same to implement the integration of the optoelectronic device as described above.
도1a, 도1b는 기존의 방법에 의한 웨이브가이드 구조를 각각 도시한 것이다.1A and 1B show a waveguide structure according to a conventional method, respectively.
도2는 본 발명의 실시예에 의해 제조된 광전소자를 도시한 단면도이다.2 is a cross-sectional view showing an optoelectronic device manufactured by an embodiment of the present invention.
도3a 내지 도3e는 본 발명의 실시예에 의해 광전소자를 제조하는 단계를 도시한 단면도이다.3A to 3E are cross-sectional views illustrating steps of manufacturing an optoelectronic device according to an embodiment of the present invention.
도4a와 도4b는 상기한 본 발명의 실시예에 의해 광전소자를 제조하고, 도3e의 세로 방향으로 도시하되 웨이브가이드부와 발광부의 단면 구조를 도시한 것이다.4A and 4B illustrate a cross-sectional structure of a waveguide part and a light emitting part, which are manufactured in the photoelectric device according to the embodiment of the present invention described above and shown in the vertical direction of FIG. 3E.
※ 도면부호의 간단한 설명※ Brief Description of Drawings
1 : 실리콘 기판 2 : 제1 산화막1 silicon substrate 2 first oxide film
3 : N+ 실리콘층 4 : N- 실리콘층3: N + silicon layer 4: N- silicon layer
5 : SiGe/SiGeC 박막 6 : P- 실리콘층5: SiGe / SiGeC thin film 6: P- silicon layer
7 : Ge 임플란트 영역 9 : 제2 산화막7 Ge implant region 9 Second oxide film
11 : P형전극 13 : 제3 산화막11: P-type electrode 13: Third oxide film
12 : N형전극 15 : 빔12 N-type electrode 15 Beam
17 : 발광부 18 : 웨이브가이드부17: light emitting portion 18: wave guide portion
19 : 수광부 20 22 : 소자분리막19: light receiver 20 22: device isolation film
25 : 트렌치25: trench
상기한 목적을 잘성하기 위한 본 발명은 SiGe 광전소자에 있어서,The present invention for achieving the above object in the SiGe optoelectronic device,
실리콘 기판 상부에 산화막이 적층되고,An oxide film is laminated on the silicon substrate,
상기 산화막 상부에 웨이브가이드부에는 두꺼운 두께의 N+ 실리콘층이 구비되고, 수광부와 발광부는 얇은 두께의 N+ 실리콘층이 구비되고,A thick N + silicon layer is provided on the waveguide part on the oxide film, and the light receiving part and the light emitting part are provided with a thin N + silicon layer.
상기 수광부와 발광부에서 상기 N+ 실리콘층 상부에 순차적으로 적층된 N-실리콘층, SiGe/SiGeC 박막이 적층되고,N-silicon layers and SiGe / SiGeC thin films sequentially stacked on the N + silicon layer in the light receiving unit and the light emitting unit are stacked,
상기 SiGeC 박막 상부에 적층된 P- 실리콘층이 구비되고,P-silicon layer is stacked on the SiGeC thin film,
상기 수광부의 N- 실리콘층과 SiGe/SiGeC 박막에 다수의 Ge 임플란트영역이 구비되고,A plurality of Ge implant regions are provided in the N-silicon layer and the SiGe / SiGeC thin film of the light receiving unit,
상기 수광부와 발광부의 경계면에 N+ 영역이 구비되고,N + region is provided on the interface between the light receiving portion and the light emitting portion,
상기 웨이브가이드부의 상부면과 상기 수광부와 발광부의 경계면에 소자분리산화막이 구비되고,A device isolation oxide film is provided on an upper surface of the wave guide part and an interface between the light receiving part and the light emitting part.
상기 수광부와 발광부의 상부면에 P형 전극이 구비되고,P-type electrode is provided on the light receiving portion and the upper surface of the light emitting portion,
상기 수광부와 발광부 및 웨이브가이드부는 일정폭을 가지고, 상기 제1 산화막 상부의 N+ 실리콘층의 일정 두께까지 식각되고,The light receiving portion, the light emitting portion, and the waveguide portion have a predetermined width, and are etched to a predetermined thickness of the N + silicon layer on the first oxide film,
상기 수광부와 발광부의 측면 하부면에 N형 전극이 구비되는 것을 포함한다.It includes an N-type electrode is provided on the lower surface side of the light receiving portion and the light emitting portion.
상기 웨이브가이드부에 있는 N+ 실리콘층과 P- 실리콘층의 계면에 국부적으로 N- 영역이 구비되되, 하부의 N- 실리콘층까지 구비되며, 상기 수광부의 Ge은 디펙트를 최소화시키기 위하여 약 5㎛×5㎛ 정도의 극소면적으로 여러군데에 걸쳐 임플란트 영역이 구비된다.The N- region is provided locally at the interface between the N + silicon layer and the P- silicon layer in the waveguide part, and the lower N-silicon layer is provided, and the Ge of the light receiving part is about 5 μm to minimize the defect. The implant area is provided in several places with a very small area of about 5 μm.
상기 발광부에 해당되는 영역은 디펙트를 최소화시키기 위하여 10㎛ 이내로 하며, 상기 P- 실리콘층의 두께는 SiGe계열의 활성층을 통하여 가이드되는 빔의 직경보다 훨씬 크게 되도록 1-2㎛ 정도로 형성한다.The area corresponding to the light emitting part is within 10 μm to minimize defects, and the thickness of the P-silicon layer is formed to be about 1-2 μm so as to be much larger than the diameter of the beam guided through the active layer of the SiGe series.
상기 수광부와 발광부에 성장되는 N- 실리콘층은 수광소자에서 역바이서스를 걸었을 때 충분히 디플리션 되도록 낮은 농도를 갖도록 한다.The N-silicon layer grown on the light receiving unit and the light emitting unit has a low concentration so as to be sufficiently depleted when the reverse light is applied to the light receiving element.
상기한 목적을 달성하기 위한 본 발명은 SiGe 광전소자 제조방법에 있어서,In the present invention for achieving the above object in the SiGe photoelectric device manufacturing method,
실리콘 기판, 제1 산화막 및 N+ 실리콘층을 적층하는 단계와,Stacking a silicon substrate, a first oxide film and an N + silicon layer;
상기 N+ 실리콘층 상부에 제2 산화막을 증착한후, 패턴닝 공정으로 웨이브가이드 영역에만 상기 제2 산화막을 남기는 단계와,Depositing a second oxide film over the N + silicon layer, and leaving the second oxide film only in a waveguide region by a patterning process;
상기 제2 산화막을 마스크로 상기 수광부과 발광부에 있는 N+ 실리콘층을 식각하여 얇은 두께가 남도록 하는 단계와,Etching the N + silicon layer in the light receiving portion and the light emitting portion by using the second oxide film as a mask to leave a thin thickness;
상기 수광부와 발광부에 N- 실리콘층과 SiGe/SiGeC 박막을 성장시키고, 그 표면에 P-실리콘층을 성장시키는 단계와,Growing an N-silicon layer and a SiGe / SiGeC thin film on the light receiving portion and the light emitting portion, and growing a P-silicon layer on the surface thereof;
상기 수광부에 국부적으로 Ge을 임플란트하여 N- 실리콘층과 SiGe/SiGeC 박막에 Ge 임플란트 영역을 다수개 형성하고, 열공정으로 활성화시키는 단계와,Locally implanting Ge into the light-receiving portion to form a plurality of Ge implant regions on an N-silicon layer and a SiGe / SiGeC thin film, and activating by thermal process;
상기 제2 산화막을 제거하고, 웨이브가이드층과 수광부와 발광부의 경계부에 일정깊이의 트렌치를 형성한다음, 수광부와 발광부의 경계면으로 N+ 불순물을 임플란트 시키는 단계와,Removing the second oxide layer, forming a trench having a predetermined depth at the boundary between the waveguide layer, the light receiving portion, and the light emitting portion, and implanting N + impurities into the interface between the light receiving portion and the light emitting portion;
상기 트렌치에 소자분리막을 형성하는 단계와,Forming an isolation layer in the trench;
수광부와 발광부 및 웨이브가이드부의 일정 폭을 남기고 제1 산화막 상부의 N+ 실리콘층의 일정 두께까지 식각하는 단계와,Etching to a predetermined thickness of the N + silicon layer on the first oxide layer, leaving a predetermined width of the light receiving part, the light emitting part, and the waveguide part;
제3 산화막을 증착하고, 전극이 형성될 부분의 제3 산화막은 제거하는 단계와,Depositing a third oxide film and removing the third oxide film of the portion where the electrode is to be formed;
상기 수광부와 발광부의 상부에 P형전극을 형성하고, 상기 수광부와 발광부의 측면 하부에 N형전극을 형성하는 단계를 포함한다.Forming a P-type electrode on the light receiving portion and the light emitting portion, and forming an N-type electrode on the lower side of the light receiving portion and the light emitting portion.
상기 실리콘 기판의 제1 산화막 상부에 N+ 실리콘층을 성장시키는 온도는 500-600℃ 이며,상기 SiGeC/SiGe 계열의 양자우물구조는 인장력(Tensile Strain)을 받는 조건으로 형성한다.The temperature at which the N + silicon layer is grown on the first oxide layer of the silicon substrate is 500-600 ° C., and the SiGeC / SiGe-based quantum well structure is formed under a condition of being subjected to tensile strain.
상기 수광부와 발광부에 성장되는 N- 실리콘층은 도핑농도를 낮추어서 소광소자에서 역바이서스를 걸었을 때 충분히 디플리션 되도록 하며, 상기 수광부의 Ge 임플란트 영역은 디펙트를 최소화시키기 위하여 약 5㎛×5㎛ 정도의 극소면적으로 여러군데에 걸쳐 임플란트 한다. 그리고, 상기 Ge영역을 활성화시키기 위하여 700-900C에서 열처리를 하며, 상기 웨이브가이드부의 폭은 1-3㎛ 으로 설정한다.The N-silicon layer grown on the light-receiving part and the light-emitting part lowers the doping concentration so that it is sufficiently depleted when the reverse quenching device is placed on the quenching device. It is implanted in several places with a very small area of about 5 µm. Then, heat treatment is performed at 700-900C to activate the Ge region, and the width of the wave guide portion is set to 1-3 μm.
발광다이오드의 높이와 웨이브가이드층의 높이를 맞추어 주기 위하여 발광다이오드부위는 선택적으로 식각한 후에 제작한다. 이 발광다이오드는 SiGe 양자우물구조 발광영역을 통해 웨이브가이드층을 통해 전파되는 빛은 수광소자(DETECTOR) 영역에 도달하여 흡수되게 된다. 이때 낮은 흡수율을 보상하기 위해 SiGe층 근방에 국부적으로 Ge 임플란트 하여서 디텍터 근방의 밴드갭을 더욱 낮추에 주어 수광소자의 효율을 증대시킨다.In order to match the height of the light emitting diodes with the height of the waveguide layer, the light emitting diodes are selectively etched and manufactured. The light emitting diodes, which propagate through the waveguide layer through the SiGe quantum well structure light emitting region, reach and absorb the DETECTOR region. At this time, in order to compensate for the low absorption rate, the Ge implant is locally placed near the SiGe layer to further lower the band gap near the detector, thereby increasing the efficiency of the light receiving device.
스트레인을 이용한 박막의 이점은 이미 Ⅲ-Ⅴ족/Ⅱ-Ⅳ족 화합물반도체에서 널리 연구되었듯이 밴드갭의 특성변화, 흡수율/발광천이율의 변화, 이동도의 증가 등의 많은 이점을 가지고 있다. Ge은 주기율표상에서 Si보다 아래쪽에 있고 동일 족에 해당하기 때문에 격자상수가 더 크고 유사한 원자구조를 가진다. 반면 C(Carbon)은 주기율표상에서 Si보다 위쪽에 있기 때문에 격자상수가 작고 동일한 원자구조를 가진다. 따라서 적층한 수퍼레티스의 경우 SiGe층은 압축 스트레인(COMPRESSIVE STRAIN)을 받게 되며 SiGeC계열의 삼원화합물을 이용하면 C의 농도를 조절하여 압축/인장 스트레인(COMPRESSIVE/TENSILE STRAIN)을 조절할 수 있게 된다. 이 특성을 이용하여 SiGe/SiGeC 수퍼래티스를 적층하여 발광천이가 가능한 타입 Ⅰ 형태의 밴드구조를 형성한다.The advantages of thin films using strains have many advantages, such as changes in bandgap characteristics, changes in absorption / luminescence transition rates, and mobility, as are widely studied in III-V / II-IV compound semiconductors. Ge is lower than Si in the periodic table and is of the same family, so the lattice constant is larger and has a similar atomic structure. On the other hand, since C (Carbon) is above Si in the periodic table, the lattice constant is small and has the same atomic structure. Therefore, in the case of stacked superretires, the SiGe layer receives a compressive strain, and when using a tertiary compound of the SiGeC series, it is possible to control the compressive / tensile strain by adjusting the concentration of C. By using this property, SiGe / SiGeC superlattices are laminated to form a band structure of type I type which can emit light emission.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명하기로 한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
도3a 내지 도3e는 본 발명의 실시예에 의해 광전소자를 제조하는 단계를 도시한 단면도이다.3A to 3E are cross-sectional views illustrating steps of manufacturing an optoelectronic device according to an embodiment of the present invention.
도3a는 실리콘 기판(1)에 제1 산화막(2)과 N+ 실리콘층(3)을 적층하고, 상기 N+ 실리콘층(3) 상부에 제2 산화막(9)를 증착한 후 웨이브가이드부에 제2 산화막(9)을 남긴다음, 이것을 마스크로 이용한 식각공정으로 수광부(19)와 발광부(17)의 N+ 실리콘층(3)을 식각하여 상기 제1 산화막(2) 상부에 얇은 두께의 N+ 실리콘층(3)만 남긴 것을 도시한 것이다.FIG. 3A shows a first oxide film 2 and an N + silicon layer 3 stacked on a silicon substrate 1, a second oxide film 9 deposited on the N + silicon layer 3, and then a wave guide portion. After leaving the oxide film 9, the N + silicon layer 3 of the light receiving portion 19 and the light emitting portion 17 is etched using an etching process using the same as a mask to form a thin N + silicon layer on the first oxide film 2. Only the layer 3 is shown.
도3b는 N+ 실리콘층(3)이 식각된 위치에 N- 실리콘층(4)을 에피텍셜 성장시킨다음, 그 상부에 MBE를 이용하여 SiGe/SiGeC 박막(5)을 성장시킨다. 그리고, 그상부에 P- 실리콘층(6)을 에피텍셜 성장으로 상기 제2 산화막(9) 까지 형성시킨 것을 도시한다.3B epitaxially grows the N− silicon layer 4 at the position where the N + silicon layer 3 is etched, and then grows a SiGe / SiGeC thin film 5 using MBE on top thereof. The P-silicon layer 6 is formed thereon up to the second oxide film 9 by epitaxial growth.
여기서, 상기 SiGe/SiGeC 박막(5)은 500-600℃에서 성장시키고, 양자우물구조는 인장 스트레인(Tensile Strain)을 받는 조건으로 한다. 발광부(17)에 해당되는 영역은 10㎛ 이내로 하여 생성되는 디펙트를 최소화 시키고 소자의 전류밀도를 높여 소자의 효율을 증대시킨다. P- 실리콘층(6)의 두께는 활성층으로 작용하는 SiGe/SiGeC 박막(5)을 통하여 가이드되는 빔의 직경보다 훨씬 크게 되도록 1-2㎛ 정도로 하여 표면으로 방출되는 빔을 최소화한다. 상기 N- 실리콘층(4)은 도핑을 낮추어 주어서 수광소자에서 역바이어스를 걸었을 때 충분히 디플리트(DEPLETE) 되도록 한다.Herein, the SiGe / SiGeC thin film 5 is grown at 500-600 ° C., and the quantum well structure is subjected to a tensile strain. The area corresponding to the light emitting unit 17 is within 10 μm to minimize the defects generated and increase the current density of the device to increase the efficiency of the device. The thickness of the P-silicon layer 6 is about 1-2 탆 so as to be much larger than the diameter of the beam guided through the SiGe / SiGeC thin film 5 serving as the active layer, thereby minimizing the beam emitted to the surface. The N-silicon layer 4 lowers the doping so that it sufficiently depletes when the reverse bias is applied to the light receiving device.
도3c는 표준 공정을 거쳐 수광부(19) 부위에만 Ge을 임프란트하여 상기 SiGe/SiGeC 박막(5)의 양자우물층으로 주입되는 Ge 임플란트 영역(7)을 형성하는데 이때 넓은 면적에 높은 Ge 농도로 임플란트할 경우 많은 디펙트가 생성되어 수광소자의 암전류가 증가하게 된다. 따라서 디펙트 생성을 최소화시키기 위하여 약 5㎛×5㎛ 정도의 국소면적으로 여러군데에 걸쳐 임플란트를 시행한다. 그후 700-900℃에서 열처리를 하여 주입된 Ge 임플란트 영역(7)을 활성화시킨다. 이때 발광부의 양자우물층도 적절한 열처리를 받아서 SiGe 양자우물층의 계면이 향상되어 발광효율이 증대되게 된다.3C shows Ge implant regions 7 implanted into the quantum well layer of the SiGe / SiGeC thin film 5 by implanting Ge only in the light-receiving portion 19 through a standard process, with a high Ge concentration in a large area. In this case, many defects are generated, which increases the dark current of the light receiving device. Therefore, in order to minimize defect generation, implants are applied in several places with a local area of about 5 μm × 5 μm. Thereafter, heat treatment is performed at 700-900 ° C. to activate the implanted Ge implant region 7. At this time, the quantum well layer of the light emitting part is also subjected to appropriate heat treatment, so that the interface of the SiGe quantum well layer is improved, thereby increasing the luminous efficiency.
도3d는 상기 제2 산화막(9)을 제거한다음, 상기 발광부(17) 및 수광부(19)의 경계부 하부의 P- 실리콘층(6)와 N+ 실리콘층(3)의 일정 두께와 웨이브가이드부(18) 하부의 N+ 실리콘층(3)의 일정 두께를 식각하여 트렌치(25)를 형성하고, 상기 발광부(17) 및 수광부(19)의 경계부에 있는 P- 실리콘층(6)와 N+ 실리콘층(3)으로 N+ 농도의 불순물을 임플란트하여 N+ 임플란트 영역(14)을 형성하되, SiGe/SiGeC 박막(5)과 N- 실리콘층(4) 까지 형성한다.그리고, 상기 트렌치(25)에 산화막을 채워서 소자분리막(20,22)을 각각 형성한다.3D shows that after removing the second oxide film 9, the P-silicon layer 6 and the N + silicon layer 3 have a predetermined thickness and waveguide portion under the boundary between the light emitting portion 17 and the light receiving portion 19. (18) The trench 25 is formed by etching a predetermined thickness of the lower N + silicon layer 3, and the P-silicon layer 6 and the N + silicon at the boundary between the light emitting portion 17 and the light receiving portion 19 are formed. Impurities of N + concentration are implanted into the layer 3 to form the N + implant region 14, but the SiGe / SiGeC thin film 5 and the N-silicon layer 4 are formed. An oxide film is formed in the trench 25. To form the device isolation layers 20 and 22, respectively.
상기 N+ 영역(14)은 실리콘 에피텍셜 성장시 발생되는 계면에서의 불안한 영역과 상단부의 P- 실리콘층(6)을 분리시켜 주며, SiGe층의 낮은 밴드갭으로 인하여 P- 실리콘층(6)과 N+ 실리콘층(14, 3) 사이에서 이루어지는 PN 다이오드를 턴온시키는 전압이 P- 실리콘층(6)에서 SiGe층(5)사이의 다이오드 턴온 전압 보다 높기 때문에 먼저 SiGe 다이오드 쪽으로 흐르게 된다. 따라서 웨이브가이드부(18)로의 누설전류를 감소시켜주는 역할을 한다.The N + region 14 separates the unstable region at the interface generated during silicon epitaxial growth and the P-silicon layer 6 at the upper end, and the P-silicon layer 6 and the lower band gap due to the SiGe layer. Since the voltage for turning on the PN diode formed between the N + silicon layers 14, 3 is higher than the diode turn-on voltage between the P− silicon layer 6 and the SiGe layer 5, it first flows toward the SiGe diode. Therefore, it serves to reduce the leakage current to the wave guide portion 18.
그리고, 상기 공정후에 웨이브가이드부(18)의 폭(도4a의 16)을 조절하기 위하여 웨이브가이드부(18)와 발광부(17) 및 수광부(19)에 일정 폭을 남겨 두고 N+ 실리콘층(3) 까지 식각 공정을 진행하여 사각형의 평면 형상을 가지게 된다. 한편, 상기 웨이브가이드부(18)의 형상은 평면이 사각형 뿐아니라 굴곡을 갖는 형상으로도 제조가 가능하다.After the process, in order to adjust the width of the wave guide part 18 (16 in FIG. 4A), the N + silicon layer (with a predetermined width left in the wave guide part 18, the light emitting part 17 and the light receiving part 19) The etching process is performed until 3) to have a rectangular planar shape. On the other hand, the shape of the wave guide portion 18 can be manufactured in a shape having a curvature as well as a square plane.
도3e는 전체적으로 제3 산화막(13)을 증착하고, 수광부(19)와 발광부(17)의 전극영역에 위치하는 제3 산화막(13)을 제거한다음, 수광부(19)와 발광부(17)의 상부전극에는 P형전극(12)을 형성하고, 수광부(19)와 발광부(17)의 하부전극영역에는 N형전극(11)을 형성한다.3E deposits the third oxide film 13 as a whole, removes the third oxide film 13 positioned in the electrode region of the light receiving portion 19 and the light emitting portion 17, and then receives the light receiving portion 19 and the light emitting portion 17. FIG. The P-type electrode 12 is formed on the upper electrode of the N-type electrode 11 in the lower electrode region of the light receiving portion 19 and the light emitting portion 17.
참고로, 도2는 상기 도3e와 동일한 구조를 가지므로 별도의 설명을 생략한다.For reference, since FIG. 2 has the same structure as that of FIG. 3E, a separate description thereof will be omitted.
도4a와 도4b는 상기한 본 발명의 실시예에 광전소자를 제조할 때 도3e의 세로 방향으로 도시하되 웨이브가이드부(18)와 발광부(17)에의 단면 구조를 도시한 것이다. 도4a에서 굴절율이 낮은 소자분리막(22)과 제1산화막(2) 사이에 N+ 실리콘층(3)이 위치하고, 측변에는 제3 산화막(13)이 구비되어 빔(15)이 상하방향 및 좌우방향으로 가이드된다.4A and 4B illustrate the cross-sectional structure of the waveguide portion 18 and the light emitting portion 17 in the longitudinal direction of FIG. 3E when the photoelectric device is manufactured in the above-described embodiment of the present invention. In FIG. 4A, the N + silicon layer 3 is positioned between the device isolation film 22 and the first oxide film 2 having a low refractive index, and a third oxide film 13 is provided at the side, so that the beam 15 is vertically and horizontally disposed. Guided by.
이때 웨이브가이드부(18)의 폭은 1-3㎛ 으로 설정하여 웨이브가이드를 효율적으로 할 수 있게 한다.At this time, the width of the wave guide portion 18 is set to 1-3㎛ to enable the wave guide efficiently.
도4b는 상기한 본 발명의 실시예의 광전소자의 발광소자 또는 수광소자의 단면으로, 도3e의 세로 방향으로 도시한 것으로, 상부전극에는 P형전극(12)이 구비되고, 수광부(19)와 발광부(17)의 하부전극으로 N형전극(11)이 구비됨을 알수가 있고, 측면으로는 제3 산화막(13)이 구비됨을 도시한다.4B is a cross-sectional view of the light emitting device or the light receiving device of the photoelectric device according to the embodiment of the present invention, which is illustrated in the vertical direction of FIG. 3E. The upper electrode is provided with a P-type electrode 12, It can be seen that the N-type electrode 11 is provided as the lower electrode of the light emitting part 17, and the third oxide film 13 is provided on the side.
본 발명에 의한 광전소자는 차후 고속화에 따른 실리콘 칩 내에서의 정보전달방법에 사용된다. 또한 광 화이버(FIBER)를 이용하여 칩간의 정보전달매체로서 사용될 수 있다. SiGe층은 500℃정도의 낮은 온도에서 이루어지는 공정으로서 기존의 실리콘 공정의 대부분을 그대로 적용할 수 있으므로 생산비용이 절감된다.The optoelectronic device according to the present invention is used in a method of transferring information in a silicon chip at a later speed. In addition, it may be used as an information transfer medium between chips using an optical fiber (FIBER). The SiGe layer is a process performed at a low temperature of about 500 ° C., and thus, most of the existing silicon processes can be applied as it is, thereby reducing production costs.
그리고, 수광소자와 발광소자가 하나의 실리콘 기판에 형성됨으로 인하여 빔의 전달이 빠르고 손실이 적어서 효율이 높다.In addition, since the light receiving element and the light emitting element are formed on one silicon substrate, the beam is transmitted quickly and the loss is high, so the efficiency is high.
Claims (15)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002061842A1 (en) * | 2001-01-31 | 2002-08-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor crystal film and method for preparation thereof |
| US8901694B2 (en) | 2011-09-14 | 2014-12-02 | Samsung Electronics Co., Ltd. | Optical input/output device and method of fabricating the same |
-
1998
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002061842A1 (en) * | 2001-01-31 | 2002-08-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor crystal film and method for preparation thereof |
| US6852602B2 (en) | 2001-01-31 | 2005-02-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor crystal film and method for preparation thereof |
| US8901694B2 (en) | 2011-09-14 | 2014-12-02 | Samsung Electronics Co., Ltd. | Optical input/output device and method of fabricating the same |
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