KR20000027056A - Oscillator for generating high voltage of flash memory device - Google Patents

Abstract

PURPOSE: An oscillator for generating high voltage of flash memory device is provided to output a stable high voltage by outputting an oscillating signal having a varied period according to the change of a power supply voltage using a reference voltage. CONSTITUTION: A detecting circuit(100) has a delay circuit(110), a first detecting circuit(120), and a second detecting circuit(130). The first detecting circuit(120) has resistors(111-116) and NMOS transistors(117,118). Resistors(111-116) are connected between a supply terminal of a reference voltage(Vref) and a drain of the NMOS transistors(117). The NMOS transistor(117) has a current path formed between the resistor(116) and the NMOS transistor(118) and a gate connected to a drain. The NMOS transistors(118) have a current path formed between a source of the NMOS transistors(117) and a ground voltage(Vss) and a gate connected to a bias circuit(200). The second detecting circuit(130) has NMOS transistors(121-124) and capacitors(125-127). The bias circuit(200) has an inverter(210) and a MOS transistor(220).

Description

OSCILLATOR FOR GENERATING HIGH VOLTAGE OF FLASH MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device, and more particularly to an oscillator of a program voltage generator for generating a high voltage.

An electrically erasable and programmable flash memory device generates a high voltage required by a program voltage generator built into a chip for erasing and programming. For example, a program operation in a NAND flash memory device is performed by emitting electrons of a floating gate by applying a high voltage of '18 V (volt) 'or more to the control gate, and an erase operation is performed. Contrary to the program operation, it is performed by applying a high voltage of '20 V 'or more to the bulk and' 0 V 'to the control gate.

Referring to FIG. 1, a general program voltage generator includes a high voltage generation circuit 10, a detection circuit 20, an oscillation circuit 30, a NAND gate 40, and an inverter 50. The high voltage generation circuit 10 generates a high voltage Vpgm by control of control signals Opgm and nOpgm supplied through the NAND gate 40 and the inverter 50. The high voltage generating circuit 10 generally uses a well-known J.F.Dickson type charge pump. The detection circuit 20 detects a voltage level of the high voltage Vpgm from the high voltage generation circuit 10 and outputs a detection signal DET. The oscillation circuit 30 outputs an oscillation signal Obpp having a predetermined pulse width. The NAND gate 40 outputs the control signal nOpgm which combines the detection signal DET from the detection circuit 20 and the oscillation signal Ovpp from the oscillation circuit 30. The inverter 50 outputs a control signal Opgm inverting the control signal nOpgm from the NAND gate 40.

However, in NAND memory cells, conservative memory cells are connected in series to form a string. Due to the above structure, '0 V' is applied to the control gate of the selected memory cell, and a power supply voltage VCC or a specific voltage is applied to the control gates of the remaining non-selected memory cells, so the threshold voltage of the memory cell is thresholded. If voltage (Vth) is higher than the voltage applied to the control gate of the unselected memory cells, it becomes difficult to determine whether the selected memory cells are turned on or off, resulting in device fail.

The program voltage generator should generate a high voltage having a constant voltage level regardless of the variation of the power supply voltage VCC (for example, 2.5 V to 6.5 V). Because, when the voltage level of the program voltage Vpgm is changed according to the change in the power supply voltage VCC, a difference occurs in the number of electrons emitted from the floating gate of the memory cell, and thus the threshold voltage of the memory cell. This is because a difference in the distribution of (Vth) occurs, and a difference in program speed occurs due to process variables. As a result, the program voltage Vpgm is generated high, the program speed of the memory cell is increased, and the threshold voltage Vth of the memory cell is distributed high, resulting in device failing.

Although not shown, the J.F.Dickson type charge pump used in the high voltage generation circuit 10 has current paths connected in series and capacitors connected to the gate. The high voltage generation circuit 10 generates a high voltage Vpgm by performing a pumping operation whenever the voltage levels of the control signals Opgm and nOpgm are changed. The high voltage Vpgm output from the high voltage generation circuit 10 is determined by the number of the transistors, the period of the oscillation signal Obvpp, and the voltage level of the power supply voltage VCC. Has the same correlation as

[Equation 1]

Vpgm = 2N × (VCC-Vt) × td

In Equation 1, N denotes the number of transistors provided in the charge pump, VCC denotes the power supply voltage VCC, and Vt denotes the threshold voltage of the transistors provided in the charge pump. And td means the period of the oscillation signal (Ovpp). As can be seen from [Equation 1], when the power supply voltage increases, the voltage level of the program voltage Vpgm generated by the charge pump increases, which may cause a mal-function in the device. Accordingly, an oscillation circuit for outputting an oscillation signal Oppp having a period varying with the variation of the power supply voltage VCC is required.

Referring to FIG. 2, the oscillation circuit 20 according to the related art outputs an oscillation signal Obpp having a period varying with the variation of the power supply voltage VCC. The oscillation circuit 20 uses the reference current Iref, which is variable according to the change in the power supply voltage VCC, as a current source, so that the reference current Iref with respect to the change in the power supply voltage VCC. It is characterized by a constant take. Therefore, looking at it as an equation, it is shown as Equation 2 below.

[Equation 2]

Iref = 1 / r _ds ... (One)

CV = it ... (2)

Td = ... (3)

Td = = r _ds C (VCC-Vref) ... (4)

Equation 2 of Equation 2 is a constant value because the transistor NM1 of FIG. 2 used as the current source is operated in a saturation region. Therefore, the period td of the oscillation signal Obpp obtained from 'CV = it' of Equation (2) is the same as Equation (3). Also, since the currents Iref and Iref 'flowing through the transistors NM4, NM5, NM7 and NM8 of the delay circuits 31b and 31c of FIG. 2 are the same, the period of the oscillation signal Obpp is It can be represented by (4).

The program voltage generator including the oscillation circuit 20 increases the period of the oscillation signal Ovpp as the power supply voltage rises, thereby canceling a potion increased by the power supply voltage VCC. It generates a high voltage (Vpgm). However, the oscillation circuit 20 of the current source type is sensitive to process variation due to the use of the transistor current source NM1, and the variation range of the power supply voltage VCC is widened (for example, 2.5). According to V to 6,5 V), there is a problem in that the oscillation signal Oppp having a period for stabilizing the efficiency of the program voltage generator cannot be output.

Accordingly, an object of the present invention is to provide an oscillation circuit of a program voltage generator for generating an oscillation signal having a period varying with a change in power supply voltage.

1 is a block diagram of a typical high voltage generation circuit;

2 is a circuit diagram of an oscillation circuit provided in a high voltage generation circuit according to the prior art;

3 is a detailed circuit diagram of an oscillation circuit according to the present invention;

4 is a waveform diagram showing oscillation frequencies of oscillation circuits according to the prior art and the present invention.

* Explanation of symbols on the main parts of the drawings

100: detection circuit 200: bias circuit

300, 400: comparison circuit 500: flip-flop

600: discharge transistor 700: inverter

(Configuration)

According to one aspect of the present invention for achieving the above object, the oscillation circuit receives a reference voltage having a constant voltage level and a power supply voltage and an activation signal for informing the oscillation operation, and according to the fluctuation voltage level of the power supply voltage. Detection means for generating first and second detection voltages having a varying voltage level; Comparison means for comparing the reference voltage and the first and second detection voltages from the detection means and outputting first and second comparison signals as a comparison result; Bias means for receiving the power supply voltage and supplying electric charges corresponding to the power supply voltage to the comparing means in response to an activation signal from the outside informing an oscillation operation; Oscillating means for receiving charges corresponding to the first and second comparison signals from the comparing means and the power supply voltage from the biasing means and outputting first and second oscillating signals having a predetermined pulse width; The detecting means may include: a voltage dividing means for dividing the reference voltage, and a first detection circuit outputting the first detection voltage in response to the reference voltage from the voltage dividing means and the second oscillation signal from the oscillating means. And a second detection circuit which generates the second voltage in response to the reference voltage from the voltage dividing means and the first oscillation signal from the oscillation means.

In this embodiment, the voltage dividing means has a plurality of resistors connected in series, the load circuit for dividing the reference voltage and the reference voltage according to the inversion signal of the activation signal and the reference voltage from the load circuit. Discharge transistors that discharge corresponding charges to the ground voltage.

(Action)

By such an apparatus, a stable high voltage can be output by outputting an oscillation signal having a period in which the power supply voltage varies with a change.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 3 and 4 according to an embodiment of the present invention.

Referring to FIG. 3, the oscillating circuit of the novel program voltage generator of the present invention includes a detection circuit 100, a bias circuit 200, a first comparison circuit 300, a second comparison circuit 400, and a flip-flop 500. ), A discharge transistor 600, and an inverter 700. The detection circuit 100 receives the reference voltage Vref from a reference voltage generating circuit (not shown) and has first and second detection voltages having a voltage level that varies according to a change in the power supply voltage VCC. Outputs Vcom1, Vcom2). The bias circuit 200 supplies charges corresponding to the power supply voltage VCC to the flip-flop 500. The first comparison circuit 300 compares the reference voltage Vref with the first detection voltage Vcom1 and outputs a first comparison signal COM1 as a comparison result. The second comparison circuit 400 compares the reference voltage Vref with the second detection voltage Vcom2 and outputs a second comparison signal COM2 as a comparison result. The flip-flop 500 receives the first and second comparison signals COM1 and COM2 and outputs the oscillation signal Obpp having a predetermined pulse width. The discharge transistor 600 receives the activation signal nOSCvpp from the outside and discharges the electric charges charged to the output terminal of the second comparison circuit 400. The inverter 700 inverts and outputs the oscillation signal Obpp from the flip-flop 500.

In the following description, the same or similar reference numerals and signs in the drawings represent the same or similar components as much as possible.

Referring to FIG. 3, the oscillation circuit according to the present invention includes a detection circuit 100, a bias circuit 200, a first comparison circuit 300, a second comparison circuit 400, a flip-flop 500, and a discharge transistor ( 600) and inverter 700. The detection circuit 100 includes a delay circuit 110, a first detection circuit 120, and a second detection circuit 120. The first detection circuit 110 includes resistors 111, 112, 113, 114, 115, and 116 and NMOS transistors 117 and 118. The resistors 111, 112, 113, 114, 115, and 116 are connected in series between a reference voltage (Vref) supply terminal and the drain of the NMOS transistor 117. The NMOS transistor 117 has a gate connected to a drain and a current path formed between the resistor 116 and the NMOS transistor 118. The NMOS transistor 118 has a current path formed between the source of the NMOS transistor 117 and the ground voltage VSS and a gate connected to the bias circuit 200.

The first detection circuit 120 includes NMOS transistors 121, 122, 123, and 124 and capacitors 125, 126, and 127. The NMOS transistors 121 and 122 have a current path formed between the power supply voltage VCC and the drain of the NMOS transistor 123 and gates connected to a second output terminal of the flip-flop 500. The NMOS transistor 123 is connected to a current path formed between the source of the NMOS transistor 122 and the ground voltage VSS and a gate connected to the gate of the NMOS transistor 118 of the delay circuit 110. Have The NMOS transistor 124 has a current path formed between a connection point of the NMOS transistors 121 and 122 and the ground voltage VSS and a gate connected to the activation signal nOSCvpp input terminal. The capacitors 125, 126, and 127 are connected in parallel between the connection point of the NMOS transistors 121, 122, and 124 and the ground voltage VSS.

The second detection circuit 130 includes NMOS transistors 131, 132, 133 and capacitors 134, 135, 136. The NMOS transistors 121 and 122 have a current path formed between the power supply voltage VCC and the drain of the NMOS transistor 133 and gates connected to a first output terminal of the flip-flop 500. The NMOS transistor 133 is connected to a current path formed between the source of the NMOS transistor 132 and the ground voltage VSS and a gate connected to the gate of the NMOS transistor 118 of the delay circuit 110. Have The capacitors 134, 135, and 136 are connected in parallel between the connection point of the NMOS transistors 131 and 132 and the ground voltage VSS.

The bias circuit 200 includes an inverter 210 and a MOS transistor 220. An input terminal of the inverter 210 is connected to the activation signal nOSCvpp input terminal and an output terminal is the MOS transistor 220. Is connected to the gate. The MOS transistor 220 is formed by the current path formed between the power supply voltage VCC and the first input terminal of the flip-flop 500 and the activation signal OSCvpp inverted by the inverter 210. Has a gate controlled.

The first comparison circuit 300 includes MOS transistors 310, 320, 330, 340, 350, and 360 configured in the form of a differential amplifier. The MOS transistor 310 has a current path connected between the power supply voltage VCC and the sources of the MOS transistors 320 and 330 and a gate controlled by the activation signal nOSCvpp. The MOS transistors 320 and 330 are commonly connected to current paths formed between the drain of the MOS transistor 310 and the drains of the MOS transistors 340 and 350 and the drain of the MOS transistor 330. Have gates.

The NOS transistor 340 has a current path formed between the drain of the MOS transistor 320 and the drain of the MOS transistor 360 and a gate controlled by the reference voltage Vref. The MOS transistor 350 is a current path formed between the drain of the MOS transistor 330 and the drain of the MOS transistor 360 and the first detection voltage Vcom1 from the first detection circuit 120. It has a gate controlled by The MOS transistor 360 has a current path formed between the sources of the MOS transistors 340 and 350 and the ground voltage VSS and a gate controlled by the inverted activation signal OSCvpp.

The second comparison circuit 400 includes MOS transistors 410, 420, 430, 440, 450, and 460 configured as differential amplifiers. The MOS transistor 410 has a current path connected between the power supply voltage VCC and the sources of the MOS transistors 420 and 430 and a gate controlled by the activation signal nOSCvpp. The MOS transistors 420 and 430 are commonly connected to current paths formed between the drain of the MOS transistor 410 and the drains of the MOS transistors 440 and 450 and the drain of the MOS transistor 430. Have gates.

The NOS transistor 440 has a current path formed between the drain of the MOS transistor 420 and the drain of the MOS transistor 460 and a gate controlled by the reference voltage Vref. The MOS transistor 450 is a current path formed between the drain of the MOS transistor 430 and the drain of the MOS transistor 460 and the second detection voltage Vcom2 from the second detection circuit 130. It has a gate controlled by The MOS transistor 460 has a current path formed between the sources of the MOS transistors 440 and 450 and the ground voltage VSS and a gate controlled by the inverted activation signal OSCvpp.

The flip-flop 500 includes NAND gates 510 and 520 configured in the form of an SR latch. The first input terminal of the NAND gate 510 is connected to the drain of the MOS transistor 220 of the bias circuit 200 and the output terminal of the first comparison circuit 300, and the second input terminal is connected to the NAND. The output terminal is connected to the gates of the MOS transistors 131 and 132 of the second detection circuit 130. The first input terminal of the NAND gate 520 is connected to the output terminal of the NAND gate 510, the second input terminal is connected to the output terminal of the second comparison circuit 400, and the output terminal is the It is connected to the input terminal of the inverter 700.

The discharge transistor 600 includes a current path formed between a connection point of the output terminal of the second comparison circuit 400 and the second input terminal of the NAND gate 520 and the ground voltage VSS. It has a gate controlled by an activation signal nOSCvpp. The input terminal of the inverter 700 is connected to the output terminal of the NAND gate 520, and the output terminal is connected to the second input terminal of the high voltage generation circuit 10 of FIG. 1.

3 and 4, the operation of the oscillation circuit according to the present invention will be described.

3 and 4, the detection circuit 100 receives a reference voltage Vref from a reference voltage generation circuit (not shown) and has a voltage level that varies with a change in the power supply voltage VCC. The first and second detection voltages Vcom1 and Vcom2 are output. The bias circuit 200 supplies charges corresponding to the power supply voltage VCC to the flip-flop 500. The first comparison circuit 300 compares the reference voltage Vref with the first detection voltage Vcom1 and outputs a first comparison signal COM1 as a comparison result. The second comparison circuit 400 compares the reference voltage Vref with the second detection voltage Vcom2 and outputs a second comparison signal COM2 as a comparison result. The flip-flop 500 receives the first and second comparison signals COM1 and COM2 and outputs the oscillation signal Obpp having a predetermined pulse width. The discharge transistor 600 receives the activation signal nOSCvpp from the outside and discharges the electric charges charged to the output terminal of the second comparison circuit 400. The inverter 700 inverts and outputs the oscillation signal Obpp from the flip-flop 500.

Unlike the conventional oscillation circuit, the oscillation circuit according to the present invention is characterized in that the stable reference voltage Vref controls the first and second detection circuits 120 and 130. In the conventional embodiment, the power supply voltage VCC is used as the power supply voltage of the first and second detection circuits 120 and 130, and the gate of the MOS transistor NM1 of FIG. By applying a reference voltage Vref, a method of controlling the first and second detection circuits 120 and 130 is used. However, in the oscillation circuit of the present invention, the oscillation period of a desired oscillation signal can be tracked by applying the reference voltage Vref to the first and second detection circuits 120 and 130, and It is possible to control a range of malfunction occurrence caused by temperature or a fixed variable generated by the first and second detection circuits 120 and 130.

Currents flowing through the MOS transistors 123 and 133 of the first and second detection circuits 120 and 130, respectively, are expressed by Equation 4 below. The period of the oscillation signal Oppp output from the oscillation circuit is as shown in Equation (2) below.

[Equation 4]

Iref = ... (One)

td = = ...(2)

The period td of the oscillation circuit according to the conventional embodiment is changed in the turn-on resistance of the MOS transistors NM5 and NM8 of FIG. 2 as shown in Equation 4 of Equation 2 above. By giving, the oscillation period of the oscillation signal Obpp is obtained according to the change of the power supply voltage VCC.

In the oscillation circuit according to the present invention, by obtaining the oscillation period of the oscillation signal Ovpp with the relative reference voltages Vref1-Vref2, an oscillation signal having a more stable and desired period can be obtained. Referring to FIG. 5, the first waveform ① of FIG. 5 illustrates a waveform required by the high voltage generation circuit 10 of FIG. 1. The second waveform ② shows a waveform output from the oscillation circuit according to the prior art of FIG. The third waveform ③ represents a waveform output from the oscillation circuit according to the present invention. Looking at the waveforms, it can be seen that the third waveform ③ of the oscillation signal Obpp output from the oscillation circuit according to the present invention is close to the first waveform ①.

In the above, the configuration and operation of the circuit according to the present invention is shown according to the above description and drawings, but this is merely described for example, and various changes and modifications are possible without departing from the technical spirit of the present invention. .

As described above, a stable high voltage can be output by outputting an oscillation signal having a period in which the power supply voltage varies according to the variation using the reference voltage.

Claims (2)

In an oscillator of a program voltage generator for generating a program voltage for programming and erasing a flash memory cell: Detection means for receiving a reference voltage having a power supply voltage and a constant voltage level and an activation signal indicating an oscillation operation and generating first and second detection voltages having a voltage level that is varied according to a varying voltage level of the power supply voltage; Comparison means for comparing the reference voltage and the first and second detection voltages from the detection means and outputting first and second comparison signals as a comparison result; Bias means for receiving the power supply voltage and supplying electric charges corresponding to the power supply voltage to the comparing means in response to an activation signal from the outside informing an oscillation operation; Oscillating means for receiving charges corresponding to the first and second comparison signals from the comparing means and the power supply voltage from the biasing means and outputting first and second oscillating signals having a predetermined pulse width; But The detection means, Voltage dividing means for dividing the reference voltage; A first detection circuit outputting said first detection voltage in response to said reference voltage from said voltage divider and said second oscillation signal from said oscillation means, and And a second detection circuit for generating said second voltage in response to said reference voltage from said voltage divider and said first oscillation signal from said oscillation means. The method of claim 1, The partial pressure means, A load circuit having a plurality of resistors connected in series and dividing the reference voltage; And discharge transistors for discharging charges corresponding to the reference voltage to the ground voltage according to the inversion signal of the activation signal and the reference voltage from the load circuit.