KR20000024843A - Method for manufacturing capacitor - Google Patents

Method for manufacturing capacitor Download PDF

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Publication number
KR20000024843A
KR20000024843A KR1019980041595A KR19980041595A KR20000024843A KR 20000024843 A KR20000024843 A KR 20000024843A KR 1019980041595 A KR1019980041595 A KR 1019980041595A KR 19980041595 A KR19980041595 A KR 19980041595A KR 20000024843 A KR20000024843 A KR 20000024843A
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South Korea
Prior art keywords
semiconductor substrate
insulating material
dielectric material
capacitor
polysilicon
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KR1019980041595A
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Korean (ko)
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오보석
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김영환
현대반도체 주식회사
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Priority to KR1019980041595A priority Critical patent/KR20000024843A/en
Publication of KR20000024843A publication Critical patent/KR20000024843A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A method for manufacturing capacitor is provided to easily perform a following process by minimizing a faulting between an upper electrode of a capacitor and a gate electrode to improve a flatness. CONSTITUTION: An insulating material(24) is deposited on an upper front surface of a semiconductor substrate(21). A poly silicon(25) and a dielectric material(26) are successively deposited on an upper portion of the insulating material(24). The dielectric material(26) and the poly silicon(25) are patterned through a photo engraving process and a deposit structure of the dielectric material(26) and the poly silicon(25) is formed on the insulating material(24). The patterned poly silicon(25) is a lower electrode. An insulating material(27) is deposited to an upper front surface of the semiconductor substrate(21). The semiconductor substrate(21) and the dielectric material(26) are exposed by a chemical mechanical polishing(CMP). A gate oxidation film(28) is formed on an upper portion of the semiconductor substrate(21) and a poly silicon(29) is deposited to an upper front surface of the semiconductor substrate(21).

Description

커패시터의 제조방법Manufacturing method of capacitor

본 발명은 커패시터의 제조방법에 관한 것으로, 특히 정교한 커패시턴스가 요구되는 아날로그 회로에 사용되는 폴리-폴리(poly to poly) 구조를 갖는 커패시터의 제조공정을 단순화함과 아울러 평탄도를 개선하기에 적당하도록 한 커패시터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor, and in particular, to simplify the manufacturing process of a capacitor having a poly-poly structure used in an analog circuit requiring sophisticated capacitance, and to improve the flatness. It relates to a method of manufacturing a capacitor.

일반적으로, 정교한 커패시턴스가 요구되는 아날로그 회로에 사용되는 커패시터는 외부 커패시턴스의 간섭을 차단하기 위하여 필드산화막의 상부에 형성되며, 논-메모리 칩(non-memory chip)에서 사용되는 커패시터는 폴리-폴리 구조를 사용한다.In general, capacitors used in analog circuits requiring sophisticated capacitances are formed on top of field oxides to block interference of external capacitances, and capacitors used in non-memory chips have a poly-poly structure. Use

도1은 일반적인 시스템 집적회로(IC)의 커패시터를 보인 단면도로서, 그 제조방법은 다음과 같다.1 is a cross-sectional view illustrating a capacitor of a general system integrated circuit (IC), and a method of manufacturing the same is as follows.

먼저, 반도체기판(1) 상에 필드영역과 액티브영역을 구현한다. 이때, 필드영역에는 로코스(LOCOS)공정을 통해 필드산화막(2)이 형성되어 액티브영역에 형성되는 반도체소자들을 전기적으로 절연시키고, 액티브영역에는 웰이 형성되어 이후에 그 웰에 반도체소자가 형성된다.First, a field region and an active region are implemented on the semiconductor substrate 1. At this time, the field oxide film 2 is formed in the field region through a LOCOS process to electrically insulate the semiconductor devices formed in the active region, and wells are formed in the active region, and then semiconductor devices are formed in the wells. do.

그리고, 상기 필드산화막(2)이 형성된 반도체기판(1)의 상부 전면에 폴리실리콘을 증착하고, 그 폴리실리콘의 상부에 유전물질(3)을 증착한 후, 그 유전물질(3)과 폴리실리콘을 패터닝하여 커패시터의 하부전극(4)을 형성한다.After depositing polysilicon on the entire upper surface of the semiconductor substrate 1 on which the field oxide film 2 is formed, and depositing dielectric material 3 on the polysilicon, the dielectric material 3 and polysilicon are deposited. Patterning to form the lower electrode (4) of the capacitor.

그리고, 액티브영역 상에 게이트산화막(5)을 형성한 후, 반도체기판(1)의 상부 전면에 폴리실리콘을 증착하고 패터닝하여 커패시터의 상부전극(6) 및 게이트전극(7)을 형성한다.After the gate oxide film 5 is formed on the active region, polysilicon is deposited and patterned on the entire upper surface of the semiconductor substrate 1 to form the upper electrode 6 and the gate electrode 7 of the capacitor.

그리고, 반도체기판(1)의 상부 전면에 평탄화막(8)을 증착한 후, 커패시터의 상부전극(7) 및 액티브영역 상부에 콘택(9,10)을 형성한다.After the planarization film 8 is deposited on the entire upper surface of the semiconductor substrate 1, the contacts 9 and 10 are formed on the upper electrode 7 and the active region of the capacitor.

그러나, 상기한 바와같은 종래 커패시터의 제조방법은 폴리-폴리 적층구조와 액티브영역의 단차로 인해 커패시터의 상부전극 및 게이트전극의 형성을 위한 폴리실리콘의 패터닝시에 커패시터의 하부전극에 폴리실리콘 측벽이 형성되어 단락을 유발하는 신뢰성 저하의 문제점과; 콘택 형성을 위해 평탄화막을 식각할 때, 콘택의 깊이가 서로 다름에 따라 식각이 용이하지 않은 문제점이 있었다.However, in the conventional method of manufacturing a capacitor as described above, polysilicon sidewalls are formed on the lower electrode of the capacitor during the patterning of the polysilicon for forming the upper electrode and the gate electrode of the capacitor due to the poly-poly stack structure and the step difference between the active region. A problem of deterioration of reliability which is formed to cause a short circuit; When etching the planarization layer to form the contact, there is a problem that the etching is not easy as the contact depths are different.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 제조공정을 단순화함과 아울러 평탄도를 개선할 수 있는 커패시터의 제조방법을 제공하는데 있다.The present invention has been made to solve the conventional problems as described above, an object of the present invention is to provide a method of manufacturing a capacitor that can simplify the manufacturing process and improve the flatness.

도1은 일반적인 시스템 집적회로의 커패시터를 보인 단면도.1 is a cross-sectional view showing a capacitor of a typical system integrated circuit.

도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

21:반도체기판 22:산화막21: semiconductor substrate 22: oxide film

23:질화막 24,27:절연물질23: nitride film 24, 27: insulating material

25,29:폴리실리콘 26:유전물질25, 29: polysilicon 26: dielectric material

28:게이트산화막 30:커패시터 상부전극28: gate oxide film 30: capacitor upper electrode

31:게이트전극31: gate electrode

상기한 바와같은 본 발명의 목적을 달성하기 위한 커패시터 제조방법의 바람직한 일 실시예는 반도체기판에 트랜치구조를 형성하는 공정과; 상기 트랜치구조가 형성된 반도체기판의 상부 전면에 제1절연물질, 제1폴리실리콘 및 유전물질을 순차적으로 증착하는 공정과; 상기 유전물질과 제1폴리실리콘을 사진식각공정을 통해 패터닝하여 트랜치구조 상의 제1절연물질 상부에 유전물질과 제1폴리실리콘의 적층구조를 형성하는 공정과; 상기 적층구조가 형성된 반도체기판의 상부 전면에 제2절연물질을 증착한 후, 상기 유전물질 및 반도체기판이 노출될때까지 평탄화하는 공정과; 상기 노출된 반도체기판상에 웰 형성 이온주입 및 문턱전압 조절 이온주입을 수행한 후, 게이트산화막을 형성하는 공정과; 상기 게이트산화막이 형성된 반도체기판의 상부 전면에 제2폴리실리콘을 증착한 후, 패터닝하여 커패시터의 상부전극 및 게이트전극을 형성하는 공정을 구비하여 이루어짐을 특징으로 한다.One preferred embodiment of the capacitor manufacturing method for achieving the object of the present invention as described above comprises the steps of forming a trench structure in a semiconductor substrate; Sequentially depositing a first insulating material, a first polysilicon, and a dielectric material on an upper front surface of the semiconductor substrate on which the trench structure is formed; Patterning the dielectric material and the first polysilicon through a photolithography process to form a stacked structure of the dielectric material and the first polysilicon on the first insulating material on the trench structure; Depositing a second insulating material on the entire upper surface of the semiconductor substrate on which the stacked structure is formed, and then planarizing the dielectric material and the semiconductor substrate until the semiconductor substrate is exposed; Forming a gate oxide film after performing well formation ion implantation and threshold voltage implantation ion implantation on the exposed semiconductor substrate; And depositing a second polysilicon on the entire upper surface of the semiconductor substrate on which the gate oxide film is formed, and then patterning to form an upper electrode and a gate electrode of the capacitor.

상기한 바와같은 본 발명의 일 실시예에 따른 커패시터의 제조방법을 도2a 내지 도2h의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a capacitor according to an embodiment of the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 2A to 2H.

먼저, 도2a에 도시한 바와같이 반도체기판(21)의 상부에 산화막(22)과 질화막(23)을 순차적으로 형성한다.First, as shown in FIG. 2A, an oxide film 22 and a nitride film 23 are sequentially formed on the semiconductor substrate 21.

그리고, 도2b에 도시한 바와같이 상기 질화막(23)과 산화막(22)을 사진식각공정을 통해 패터닝하여 반도체기판(21)에 트랜치구조를 형성하고, 반도체기판(21)의 상부전면에 절연물질(24)을 증착한다. 이때, 절연물질(24)로는 트랜치구조를 채우는 물질로 산화막등을 이용한다.As shown in FIG. 2B, the nitride film 23 and the oxide film 22 are patterned through a photolithography process to form a trench structure in the semiconductor substrate 21, and an insulating material on the upper surface of the semiconductor substrate 21. (24) is deposited. In this case, the insulating material 24 uses an oxide film or the like as a material for filling the trench structure.

그리고, 도2c에 도시한 바와같이 상기 절연물질(24)의 상부에 폴리실리콘(25)과 유전물질(26)을 순차적으로 증착한다.As shown in FIG. 2C, polysilicon 25 and dielectric material 26 are sequentially deposited on the insulating material 24.

그리고, 도2d에 도시한 바와같이 상기 유전물질(26)과 폴리실리콘(25)을 사진식각공정을 통해 패터닝하여 트랜치구조 상의 절연물질(24) 상부에 유전물질(26)과 폴리실리콘(25)의 적층구조를 형성한다. 이때, 패터닝된 폴리실리콘(25)은 커패시터의 하부전극이 된다.As shown in FIG. 2D, the dielectric material 26 and the polysilicon 25 are patterned by a photolithography process to form the dielectric material 26 and the polysilicon 25 on the insulating material 24 on the trench structure. To form a laminated structure. At this time, the patterned polysilicon 25 becomes a lower electrode of the capacitor.

그리고, 도2e에 도시한 바와같이 상기 적층구조가 형성된 반도체기판(21)의 상부 전면에 절연물질(27)을 증착한다. 이때, 절연물질(27)은 적층구조가 형성된 반도체기판(21)의 상부를 평탄화시키는 물질로 상기 절연물질(24)과 마찬가지로 산화막등을 증착한다.As shown in FIG. 2E, an insulating material 27 is deposited on the entire upper surface of the semiconductor substrate 21 having the stacked structure. At this time, the insulating material 27 is a material for flattening the upper portion of the semiconductor substrate 21 on which the stacked structure is formed.

그리고, 도2f에 도시한 바와같이 상기 절연물질(27)이 형성된 반도체기판(21)에 화학기계적 연마공정(chemical mechanical polishing : CMP)을 수행하여 반도체기판(21) 및 유전물질(26)을 노출시킨 후, 그 노출된 반도체기판(21)에 웰 형성 이온주입 및 문턱전압 조절 이온주입을 수행한다. 이때, 상기 질화막(23) 및 산화막(22)이 제거되며, 상기 이온주입된 반도체기판(21)은 소자가 형성되는 액티브영역이다.As shown in FIG. 2F, a chemical mechanical polishing (CMP) is performed on the semiconductor substrate 21 on which the insulating material 27 is formed to expose the semiconductor substrate 21 and the dielectric material 26. After that, well-formed ion implantation and threshold voltage regulation ion implantation are performed on the exposed semiconductor substrate 21. In this case, the nitride film 23 and the oxide film 22 are removed, and the ion implanted semiconductor substrate 21 is an active region in which a device is formed.

그리고, 도2g에 도시한 바와같이 상기 이온주입된 반도체기판(21)의 상부에 게이트산화막(28)을 형성한 후, 게이트산화막(28)이 형성된 반도체기판(21)의 상부전면에 폴리실리콘(29)을 증착한다.As shown in FIG. 2G, after the gate oxide film 28 is formed on the ion implanted semiconductor substrate 21, the polysilicon layer is formed on the upper surface of the semiconductor substrate 21 on which the gate oxide film 28 is formed. 29).

그리고, 도2h에 도시한 바와같이 상기 폴리실리콘(29)을 패터닝하여 커패시터의 상부전극(30) 및 게이트전극(31)을 형성한다.As shown in FIG. 2H, the polysilicon 29 is patterned to form the upper electrode 30 and the gate electrode 31 of the capacitor.

이후에, 반도체기판(21)의 상부 전면에 평탄화막을 증착한 후, 커패시터의 상부전극(30) 및 액티브영역 상부에 콘택을 형성한다.Thereafter, after the planarization film is deposited on the entire upper surface of the semiconductor substrate 21, a contact is formed on the upper electrode 30 and the active region of the capacitor.

상기한 바와같은 본 발명에 의한 커패시터의 제조방법은 커패시터의 상부전극과 게이트전극의 단차를 최소화하여 평탄도를 개선함으로써, 후속 공정이 용이해지는 효과와; 커패시터의 하부전극에 폴리실리콘 측벽이 형성되는 것을 방지하여 커패시터의 신뢰성을 향상시킬 수 있는 효과가 있다.The method of manufacturing a capacitor according to the present invention as described above is to minimize the step difference between the upper electrode and the gate electrode of the capacitor to improve the flatness, the subsequent process is easy to effect; It is possible to prevent polysilicon sidewalls from being formed on the lower electrode of the capacitor, thereby improving reliability of the capacitor.

Claims (3)

반도체기판에 트랜치구조를 형성하는 공정과; 상기 트랜치구조가 형성된 반도체기판의 상부 전면에 제1절연물질, 제1폴리실리콘 및 유전물질을 순차적으로 증착하는 공정과; 상기 유전물질과 제1폴리실리콘을 사진식각공정을 통해 패터닝하여 트랜치구조 상의 제1절연물질 상부에 유전물질과 제1폴리실리콘의 적층구조를 형성하는 공정과; 상기 적층구조가 형성된 반도체기판의 상부 전면에 제2절연물질을 증착한 후, 상기 유전물질 및 반도체기판이 노출될때까지 평탄화하는 공정과; 상기 노출된 반도체기판상에 웰 형성 이온주입 및 문턱전압 조절 이온주입을 수행한 후, 게이트산화막을 형성하는 공정과; 상기 게이트산화막이 형성된 반도체기판의 상부 전면에 제2폴리실리콘을 증착한 후, 패터닝하여 커패시터의 상부전극 및 게이트전극을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 하는 커패시터의 제조방법.Forming a trench structure in the semiconductor substrate; Sequentially depositing a first insulating material, a first polysilicon, and a dielectric material on an upper front surface of the semiconductor substrate on which the trench structure is formed; Patterning the dielectric material and the first polysilicon through a photolithography process to form a stacked structure of the dielectric material and the first polysilicon on the first insulating material on the trench structure; Depositing a second insulating material on the entire upper surface of the semiconductor substrate on which the stacked structure is formed, and then planarizing the dielectric material and the semiconductor substrate until the semiconductor substrate is exposed; Forming a gate oxide film after performing well formation ion implantation and threshold voltage implantation ion implantation on the exposed semiconductor substrate; And depositing a second polysilicon on the entire upper surface of the semiconductor substrate on which the gate oxide film is formed, and then patterning to form an upper electrode and a gate electrode of the capacitor. 제 1항에 있어서, 상기 제1,제2절연물질은 산화막인 것을 특징으로 하는 커패시터의 제조방법.The method of claim 1, wherein the first and second insulating materials are oxide films. 제 1항에 있어서, 상기 제2절연물질의 평탄화는 화학기계적 연마공정으로 이루어지는 것을 특징으로 하는 커패시터의 제조방법.The method of claim 1, wherein the planarization of the second insulating material is performed by a chemical mechanical polishing process.
KR1019980041595A 1998-10-02 1998-10-02 Method for manufacturing capacitor KR20000024843A (en)

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