KR20000022911A - A flip-flop circuit and a automatic layout device - Google Patents

Abstract

PURPOSE: An automatic design device of flip-flop circuit and clock signal lines having delay function is provided to receive accurate data input signals though the data input signals to a flip-flop circuit is delayed. CONSTITUTION: An automatic design device of flip-flop circuit(10) and clock signal lines having delay function comprises a delay circuit(20) and a data sustain output circuit. The delay circuit receives exterior clock signals(ECLK) and outputs interior clock signals (ICLK) having constant delay time relative to the exterior clock signals. The data sustain output circuit receives data input signals(DIS) and the interior clock signals, is synchronized to the inside clock signals to sustain the value of the data input signals, thereby outputting them as data output signals(DOS).

Description

Automatic design of flip-flop circuit and clock signal wiring with delay function {A FLIP-FLOP CIRCUIT AND A AUTOMATIC LAYOUT DEVICE}

The present invention relates to a flip-flop circuit and a circuit design method using the flip-flop circuit. The present invention also relates to an automatic design method of clock signal wiring for automatically designing the wiring of the clock signal in consideration of the delay of the data path.

15 shows a general sequence circuit. As can be seen from FIG. 15, the sequential circuit is composed of a combinational logic circuit LC and a flip-flop circuit FF. Normally, the operation speed of such a sequential circuit is determined by the propagation delay time Tpd of the combinational logic circuit LC. That is, it is determined by the propagation delay time Tpd, which is a time required for the signal to propagate the combined logic circuit LC. The propagation delay time Tpd, the setup time Tsu of the flip-flop circuit FF, and the clock period Tck satisfying the relationship of Tpd + Tsu <Tck are conditions for the sequential circuit to operate correctly.

In the present situation, the setup time Tsu of the flip-flop circuit FF is extremely close to 0, and is about 1 to 5% of the clock period Tck. Since the design is carried out using only the flip-flop circuit FF, the operation speed of the sequential circuit is determined by the propagation delay time Tpd. That is, the operation speed of the sequential circuit is determined by the maximum propagation delay time Tpd of the combined logic circuit LC located between each flip-flop circuit FF. In other words, the critical path determines the operating speed of the sequential circuit.

16 is a diagram showing a general sequence circuit and a timing chart thereof. As can be seen from FIG. 16, in a semiconductor integrated circuit including a sequential circuit, a timing at which the flip-flop circuit FF outputs a data output signal or a data input signal to which the flip-flop circuit FF is input is received. The timing is synchronized with the timing of the rising (or falling) edge of the clock signal being supplied. In Fig. 16, the path from the flip-flop circuit (FF) 1 to the flip-flop circuit (FF) 2, the path from the flip-flop circuit (FF) 2 to the flip-flop circuit 3, and two paths. There is. That is, there are a path of the combinational logic circuit (LC) 2, a path of the combinational logic circuit (LC) 3, and two paths. In these paths, the value of the propagation delay time Tpd of the combinational logic circuit LC 2 may be large, and the value of the propagation delay time Tpd of the combinational logic circuit LC 3 may be small. In this case, the maximum operating frequency of the clock signal is determined only by the value of the propagation delay time Tpd of the combinational logic circuit LC 2. In this case, the slack value SL indicating the margin for the clock signal is larger in the combinational logic circuit LC 3 than in the combinational logic circuit LC 2. For this reason, the maximum operating frequency of the clock signal is determined in accordance with the combinational logic circuit LC 2 having a small slack value SL. In addition, the slack value SL can be represented by SL = Tck-Tsu-Tpd.

Here, in the step of designing such a sequential circuit, it is designed using a computer or the like using RTL (register transfer level) technology. In the design stage of the sequential circuit, in order to improve the operation speed of the sequential circuit, a separate flip-flop circuit FF must be newly inserted into the combined logic circuit LC corresponding to the critical path. That is, in order to divide the combinational logic circuit LC having the largest propagation delay time Tpd, it is necessary to artificially insert the flip-flop circuit FF into this combinational logic circuit LC. When the flip-flop circuit FF was inserted in this way, the RTL technology had to be artificially modified.

In addition, the design of the clock signal wiring in the design stage included automatic wiring and manual wiring. Among these, the automatic wiring had no choice but to route the clock signal to all the flip-flop circuits FF simultaneously. That is, the clock signals were forced to be input to all the flip-flop circuits FF at the same timing. On the other hand, when the manual wiring is performed, the clock signal can be wired in consideration of the delay of the data path. That is, it was possible to supply a clock signal by shifting the timing among the plurality of flip-flop circuits FF. However, manual wiring requires a lot of labor and time for the design of the wiring, and has a problem that the design efficiency is not so good.

Accordingly, the present invention has been made in view of the above-described problem, and a flip-flop circuit having a delay function for causing an internal clock signal to rise after a predetermined time has elapsed after the external clock signal has risen by incorporating a delay circuit in the flip-flop circuit is provided. It aims to provide. In addition, the use of a flip-flop circuit to which such a delay function is added is aimed at minimizing the modification of the RTL technique at the design stage of the sequential circuit.

Moreover, an object of this invention is to provide the automatic design apparatus and method of the clock signal wiring in the semiconductor integrated circuit which can automatically perform the clock signal wiring which considered the data path delay.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a circuit configuration of a flip-flop circuit with a delay function according to a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the flip-flop circuit with the delay function shown in FIG. 1; FIG.

FIG. 3 is a diagram showing a specific circuit configuration of a flip-flop circuit to which a delay function shown in FIG. 1 is added.

4 is a diagram showing a modification of the first embodiment of the present invention.

Fig. 5 is a block diagram showing a circuit configuration of a flip-flop circuit to which a delay function according to a second embodiment of the present invention is added.

FIG. 6 is a flowchart for explaining the operation of the flip-flop circuit with the delay function shown in FIG. 5; FIG.

FIG. 7 is a diagram showing a specific circuit configuration of a flip-flop circuit to which a delay function shown in FIG. 5 is added. FIG.

FIG. 8 is a view for explaining the flow in the case of preparing a flip-flop circuit with a delay function as a library to design a sequential circuit. FIG.

9 is a diagram illustrating a state in which a hold violation occurs.

FIG. 10 is a flowchart for explaining an algorithm for automatically designing clock signal wiring in a semiconductor integrated circuit according to a fourth embodiment of the present invention. FIG.

Fig. 11 is a diagram showing a timing chart of the flip-flop circuit and the clock signal in the case where the clock signal supply timing of the flip-flop circuit at the start and end points can be changed in the clock signal arrival time setting process.

Fig. 12 is a diagram showing a flip-flop circuit and a timing chart of the clock signal in the case where only the flip-flop circuit at the time point can change the clock signal supply timing in the clock signal arrival time setting process.

Fig. 13 is a diagram showing a flip-flop circuit and a timing chart of the clock signal in the case where only the flip-flop circuit at the end point can change the clock signal supply timing in the clock signal arrival time setting process.

Fig. 14 is a diagram showing a flip-flop circuit in the case where the clock signal supply timing of the flip-flop circuit at the start and end points cannot be changed in the clock signal arrival time setting process.

Fig. 15 shows a general sequence circuit consisting of a combinational logic circuit and a flip-flop circuit.

Fig. 16 is a diagram showing timing of supplying a clock signal to a flip-flop circuit in a general sequence circuit composed of a combinational logic circuit and a flip-flop circuit.

<Explanation of symbols for main parts of the drawings>

10: flip-flop circuit

20: delay circuit

Detailed Description of the Invention The present invention will be fully understood from the detailed description and drawings of embodiments of the present invention shown below. However, these drawings are not intended to be limited to the specific embodiments but are merely used for explanation and understanding.

[First Embodiment]

The first embodiment of the present invention delays the timing of the clock signal supplied only to a specific flip-flop circuit from the timing of the clock signal supplied to another flip-flop circuit, so that the clock cycle of only the specific flip-flop circuit can be made apparent. will be. As a result, the sequential circuit can be operated with a high frequency clock signal. More details will be described below.

1 is a block diagram showing the configuration of a flip-flop circuit with a delay function according to the present embodiment. As can be seen from FIG. 1, the flip-flop circuit with the delay function according to the present embodiment includes a flip-flop circuit 10 and a delay circuit 20.

The data input signal DIS from the outside is input to the input terminal D of the flip-flop circuit 10. The internal clock signal ICLK from the delay circuit 20 is input to the clock terminal of the flip-flop circuit 10. The data output signal DOS is output from the output terminal Q of the flip-flop circuit 10 to the outside in synchronization with the internal clock signal ICLK. That is, the flip-flop circuit 10 is a circuit which receives and holds the data input signal DIS when the internal clock signal ICLK rises, and outputs it as a data output signal DOS.

The external clock signal ECLK from the outside is input to the delay circuit 20, and the above-described internal clock signal ICLK is output. The internal clock signal ICLK is a signal delayed by a predetermined time than the external clock signal ECLK.

Next, the operation of the flip-flop circuit with the delay function according to the first embodiment will be described based on FIG. 2. 2 is a timing chart for explaining the operation of the flip-flop circuit to which the delay function according to the first embodiment is added.

As can be seen from FIG. 2, it is assumed that the external clock signal ECLK is switched from low to high at time t1. However, the internal clock signal ICLK is in a low state at the time t1 due to the movement of the delay circuit 20. Next, it is assumed that the input data signal DIS has been switched from low to high at time t2. That is, since the propagation delay time Tpd of the combined logic circuit provided in front of the flip-flop circuit to which the delay function is added is large, the data input signal DIS is delayed by ΔT1 from the rising time t1 of the external clock signal ECLK. Assume that has risen.

Subsequently, at time t3, the internal clock signal ICLK is switched from low to high. That is, due to the movement of the delay circuit 20, the internal clock signal ICLK rises by delaying ΔT2 from the external clock signal ECLK. In synchronization with the internal clock signal ICLK, the flip-flop circuit 10 receives the data input signal DIS and outputs it as the data output signal DOS. For this reason, at time t3, the data output signal DOS is switched from low to high.

In this way, since the propagation delay time Tpd of the combined logic circuit of the previous stage is large, the flip-flop circuit 10 can receive the data input signal DIS delayed by ΔT1 and output it as the data output signal DOS. have.

3 is a diagram showing an example of a specific circuit configuration of a flip-flop circuit with a delay function according to the present embodiment.

As can be seen from FIG. 3, the delay circuit 20 includes a plurality of inverters 20a connected in series. In this embodiment, an even number of inverters 20a are provided in this delay circuit 20. By changing the number of this inverter 20a, the delay time (DELTA) T2 of the delay circuit 20 can be changed.

The output of the delay circuit 20 is connected to the inverter 30a, and the inverted internal clock signal / ICLK is output from the inverter 30a. The output of the inverter 30a is connected to the inverter 30b, and the internal clock signal ICLK is output from the inverter 30b.

The flip-flop circuit 10 is comprised with the clock inverter 10a, the inverter 10b, the transfer gate 10c, the inverter 10d, and the inverter 10e connected in series. Moreover, this flip-flop circuit 10 is comprised with the clock inverter 10f connected in parallel with the inverter 10b, and the clock inverter 10g connected in parallel with the inverter 10d. The data input signal DIS is input to the clock inverter 10a, and the data output signal DOS is output from the inverter 10e.

As described above, according to the flip-flop circuit to which the delay function according to the present embodiment is added, since the internal clock signal ICLK rises with a constant delay time ΔT2 after the external clock signal ECLK rises, the flip-flop circuit increases. The reception of the data input signal DIS in the flop circuit 10 can be delayed by the delay time DELTA T2. That is, the setup time Tsu can have a negative value in appearance. For this reason, even if the arrival of the data input signal DIS to the flip-flop circuit with the delay function arrives later than the delay time [Delta] T2 minutes, the flip-flop circuit 10 can correctly receive the data input signal DIS. Can be. Therefore, the flip-flop circuit to which this delay function is added can be operated with the external clock signal ECLK of a short period.

In addition, in 1st Embodiment, the case where this invention was applied to the flip-flop circuit 10 was demonstrated as an example. However, as can be seen from FIG. 4, the present invention can also be applied to a latch circuit 11 that requires a clock signal, such as the flip-flop circuit 10. FIG. The latch circuit 11 receives the data input signal DIS while the internal clock signal ICLK is at the high level and outputs it as the data output signal DOS, and high while the internal clock signal ICLK is at the low level. It is a circuit which holds the received data input signal DIS while outputting it as a data output signal DOS during the level. Therefore, the circuit shown in FIG. 4 constitutes a flip-flop circuit with a delay function in a broad sense, which can also be referred to as a latch circuit with a delay function.

As can be seen from this, any data holding output circuit which holds the data input signal DIS in synchronization with a clock signal such as the flip-flop circuit 10 or the latch circuit 11 and outputs it as the data output signal DOS is used. The present invention can be applied.

Second Embodiment

In the second embodiment of the present invention, the latch circuit and the pulse signal generation circuit are provided in place of the flip-flop circuit in the first embodiment to reduce the area occupied by the semiconductor integrated circuit.

5 is a block diagram showing the configuration of a flip-flop circuit to which a delay function according to the second embodiment is added.

As can be seen from FIG. 5, the flip-flop circuit with a delay function according to the second embodiment includes a latch circuit 40, a pulse generating circuit 42, and a delay circuit 20. In the present embodiment, the flip circuit operation is realized by the latch circuit 40 and the pulse generator circuit 42.

The delay circuit 20 outputs the external clock signal ECLK input in the same manner as in the first embodiment as described above with a constant delay time as the internal clock signal ICLK. This internal clock signal ICLK is input to the pulse signal generation circuit 42.

The pulse signal generation circuit 42 generates a pulse signal PS having a short pulse width in synchronization with the rise of the internal clock signal ICLK. That is, the pulse signal PS is shorter than the time of the high level in one clock cycle of the internal clock signal ICLK. This pulse signal PS is input to the latch circuit 40.

The data input signal DIS is input to the latch circuit 40 in addition to the pulse signal PS, and outputs the data output signal DOS. The latch circuit 40 receives the value of the data input signal DIS while the pulse signal PS is high and outputs it as the data output signal DOS, and this pulse while the pulse signal PS is low. The circuit maintains the value of the data input signal DIS when the signal PS falls and outputs it as the data output signal DOS.

Next, the operation of the flip-flop circuit with the delay function according to the second embodiment will be described based on FIG. 6. This figure is a figure which shows the timing chart for demonstrating operation | movement of the flip-flop circuit with the delay function which concerns on 2nd Embodiment.

As can be seen from FIG. 6, it is assumed that the external clock signal ECLK is changed from low to high at time t1. However, the internal clock signal ICLK is in a low state at the time t1 due to the movement of the delay circuit 20. For this reason, the pulse signal PS is also in a low state at this time t1. Next, it is assumed that the input data signal DIS has been switched from low to high at time t2. That is, since the propagation delay time Tpd of the combined logic circuit provided in front of the flip-flop circuit to which the delay function is added is large, the data input signal DIS is delayed by ΔT1 from the rising time t1 of the external clock signal ECLK. It is assumed to have risen.

Subsequently, at time t3, the internal clock signal ICLK is switched from low to high. That is, due to the movement of the delay circuit 20, the internal clock signal ICLK rises by delaying ΔT2 from the external clock signal ECLK. In synchronization with this internal clock signal ICLK, the pulse signal PS is switched from low to high. Since the pulse signal PS becomes high, the latch circuit 40 receives the data input signal DIS and outputs it as the data output signal DOS. For this reason, at time t3, the data output signal DOS is switched from low to high. That is, since the propagation delay time Tpd of the combined logic circuit of the previous stage is large, the latch circuit 40 can receive the data input signal DIS delayed by ΔT1 and output it as the data output signal DOS. Subsequently, at time t4, the pulse signal PS is switched from high to low. That is, the pulse signal PS is output for a short time between the time t3 and the time t4.

7 is a diagram showing an example of a specific circuit configuration of a flip-flop circuit with a delay function according to the present embodiment.

As can be seen from FIG. 7, the delay circuit 20 is configured by connecting even-numbered inverters 20a in series as in the first embodiment described above. The internal clock signal ICLK, which is the output of the delay circuit 20, is input to the inverter 42a and the NAND circuit 42b of the pulse signal generation circuit 42. An odd number of inverters 42a are provided and connected in series. The final output of this inverter 42a is also connected to the NAND circuit 42b. That is, the internal clock signal ICLK and the final output of the inverter 42a are input to the NAND circuit 42b. The inverted pulse signal / PS is output from the NAND circuit 42b. The inverted pulse signal / PS is input to the inverter 42c, and the pulse signal PS is output from the inverter 42c. These pulse signals PS and the inverted pulse signals / PS are input to the latch circuit 40.

The latch circuit 40 includes a clock inverter 40a and an inverter 40b connected in series. In addition, the latch circuit 40 includes a clock inverter 40c connected in parallel with the inverter 40b. The data input signal DIS is input to the clock inverter 40a, and the data output signal DOS is output from the inverter 40b.

As described above, according to the flip-flop circuit to which the delay function according to the present embodiment is added, since the flip-flop operation can be performed by the pulse signal generation circuit 42 and the latch circuit 40, the area occupied by the semiconductor integrated circuit is reduced. can do. That is, as in the above-described first embodiment, when the delay circuit 20 and the normal flip-flop circuit 10 are combined to form a flip-flop circuit with a delay function having a negative setup time Tsu, As a matter of course, the area and power consumption are larger than that of the normal flip-flop circuit 10. On the other hand, in this embodiment, in order to compensate for this drawback, the delay circuit 20, the pulse signal generation circuit 42, and the latch circuit 40 add a delay function having a negative setup time Tsu. Since the flip-flop circuit is configured, the area can be approximately 2/3 of that of the first embodiment described above. In other words, since the conventional flip-flop circuit 10 is composed of a master latch circuit and a slave latch circuit, the latch circuit 40 can be realized with about half the area of the flip-flop circuit 10. By providing the delay circuit 20 and the pulse signal generation circuit 42 in this reduced portion, a flip-flop circuit with a delay function added to a smaller area can be realized.

[Third Embodiment]

The third embodiment relates to a design method using a flip-flop with a delay function according to the first and second embodiments described above, and includes a flip-flop circuit with a plurality of delay functions with different setup times Tsu. In other words, it is to prepare a design development computer and perform design development.

One order circuit includes a plurality of combinational logic circuits. For this reason, the delay time of the combined logic circuit which comprises a sequential circuit is large and small. In the design stage of the sequential circuit, generally, the largest delay time among these is called a critical path, and determines the operation cycle of the sequential circuit. That is, the highest clock signal frequency is determined by the critical path. If the operation period does not reach the target value, the combination logic circuit of the critical path portion is forced to change. Specifically, it is necessary to insert a flip-flop circuit into the combinational logic circuit of the critical path portion to divide the combinational logic circuit. When such a change is made, it usually responds by changing the RTL description.

However, by using the flip-flop circuit to which the delay function according to the above-mentioned first and second embodiments is added, the operation cycle can be increased without changing the combinational logic circuit of the critical path. In other words, a flip-flop circuit having a delay function having a delay circuit 20 equal to a short time Td which is desired to be shortened among the delay times of the combined logic circuit of the critical path may be used at the rear end of the combined logic circuit. . In other words, the flip-flop circuit to which the critical path signal is input may be changed.

For example, since the propagation delay time Tpd of the combinational logic circuit LC 2 in FIG. 15 is large, it is delayed by a delay time Td than the clock signal, so that the output signal of the combinational logic circuit LC 2 is reduced. It is assumed that the flip-flop circuit (FF) 2 has been reached. That is, it is assumed that the under time is Td. In this case, flip-flop is replaced by replacing the rear flip-flop circuit FF 2 of the combinational logic circuit LC with a flip-flop circuit with a delay function having a delay of less than the time Td. The circuit (FF) 2 can receive the output signal of the correct combinational logic circuit.

In addition, there may be a case in which a path of a combinational logic circuit is actually smaller than a critical path but does not meet a target value of an operation period. In order to correspond to the paths of these combinational logic circuits, it is preferable to prepare a flip-flop circuit with a delay function having a delay time smaller than the delay time Td of the critical path. That is, it is desirable to prepare a plurality of flip-flop circuits to which a delay function having various delay times is added. In this way, the flip-flop circuit to which the delay function with different delay time was added is registered in a library, and logic synthesis is performed again.

The flow of this design is shown by a flowchart as shown in FIG. That is, the invention concerning this embodiment can be implement | achieved by performing this process shown in FIG. 8 with a computer for design development.

As shown in Fig. 8, first, an RTL technique is performed on the designed sequence circuit (S1). Subsequently, logical synthesis is performed with the logical synthesis device based on this RTL description (S2). Next, a gate level description is performed based on this logical synthesis result (S3). Based on this gate level technique, a critical path analysis for detecting a critical path is performed (S4). Next, a time Td for the operation period of the clock signal in this critical path is obtained (S5). In this case, in addition to this critical path, there may be a combination logic circuit that is delayed from the operation period of the clock signal. In such cases, these undertimes may also be obtained simultaneously.

Next, logic synthesis is performed once again using a library of flip-flop circuits to which a delay function having a setup time Tsu of -Td to 0 is added (S6). In other words, the flip-flop circuit of the rear end of the combined logic circuit in the critical path is replaced by the flip-flop circuit with a delay function having a delay time equal to the delay time Td in the critical path. Specifically, a flip-flop circuit having a delay time longer than the under time Td and having the smallest delay time is added.

Further, among the combinational logic circuits in other passes, the flip-flop circuit at the rear end of the path having the under time is replaced by the flip-flop circuit to which the delay function having the delay time equal to the delay time is added. Specifically, it is replaced by a flip-flop circuit having a delay time longer than the delay time and having a delay function having the smallest delay time. This obtains a gate level technique that satisfies the operation period of the desired clock signal (S7).

In addition, when there are many paths that do not meet the target value of the operation period, it is conceivable to make the maximum delay time of the flip-flop circuit with the replacement delay function larger than the critical time Td of the critical path.

However, the flip-flop circuit with the delay function has a large positive hold time instead of having a negative setup time Tsu, so that a hold violation is likely to occur. 9 is a diagram for explaining a process in which this hold violation occurs. As can be seen from this figure, in this example, since the propagation delay time Tpd of the combined logic circuit LC 4 is large, the flip-flop circuit FF 6 has a delay time DELTA T2. A flip-flop circuit with a delay function is used. Therefore, the output signal itself of the combinational logic circuit LC 4 is suitable for reception of the flip-flop circuit FF 6 even through the AND circuit 50. By the way, when the propagation delay time Tpd of the combinational logic circuit LC 5 is not very large, the combinational logic circuit (F) before the flip-flop circuit FF 6 receives the output signal of the AND circuit 50 ( It is also conceivable that the output signal of LC) 5 changes in synchronization with the rise of the clock signal at the next timing. This is a hold violation. Therefore, in order to prevent such a hold violation from occurring, a delay time generation circuit 52 having a small area and a large delay time must be inserted between the combinational logic circuit LC 5 and the AND circuit 50. For this purpose, it is also necessary to register the delay time generation circuit 52 in the library for delaying and outputting the input signal for a predetermined time.

As described above, according to the designing method of the sequential circuit according to the present embodiment, even if a short time occurs in the combined logic circuit, it is possible to cope without changing the RTL technique. In other words, it is possible to ensure correct operation only by replacing the flip-flop circuit having a short time with a flip-flop circuit with a delay function. This eliminates the need to change the RTL technology and enables efficient design work.

Further, even in the present situation, the setup time Tsu of the flip-flop circuit registered in the library is different, but it is incidentally (as a side effect) as a result of changing other characteristics (for example, driving force, etc.). In contrast, in the present invention, only the setup time Tsu is actively changed while maintaining the characteristics other than the setup time Tsu of the flip-flop circuit.

As a result, by partially using a flip-flop circuit having a negative setup time Tsu, even if the propagation delay time Tpd is larger than the clock period Tck, the relational expression of Tpd + Tsu <Tck can be satisfied. That is, by using a flip-flop circuit in which a delay function having a negative setup time Tsu is added to the flip-flop circuit forming the critical path, the operation speed of the entire sequence circuit can be improved. This can be done without changing the insertion position of the flip-flop circuit, and there is no need to change the RTL technique at the design stage. In addition, since the clock signal is delayed inside the flip-flop circuit, there is no need to modify the clock distribution mechanism, and the delay can be precisely added.

In addition, according to the designing method of the order circuit according to the present embodiment, since the timing for supplying the clock signal to the flip-flop circuit is distributed, the noise generated from the clock signal can be reduced.

Further, since the timing for supplying the clock signal is distributed, the timing for consuming power by the combinational logic circuit is also distributed, so that the peak current in the entirety of the sequence circuit can be suppressed low. For this reason, the wiring for supplying power to the flip-flop circuit and the combination order circuit can be made thinner than when the timing for supplying the clock signal is not dispersed.

[4th Embodiment]

The fourth embodiment of the present invention improves the maximum operating frequency by controlling the timing of the clock signal supplied to all flip-flop circuits in the semiconductor integrated circuit constituting the sequential circuit in consideration of the delay of the path of each combination logic circuit. I will. Then, it is to provide an algorithm which automatically determines the timing of supply of such clock signals and wires the clock signals. More details will be described below.

FIG. 10 is a flowchart for explaining a clock automatic wiring algorithm according to the present embodiment. FIG. By performing the process shown in FIG. 10 with a computer for design development, the invention concerning this embodiment can be implement | achieved. Hereinafter, this clock automatic wiring algorithm will be described based on this FIG.

<Premise>

First, the premise is described before entering the description of the flowchart.

(1) Set the current cycle time to Clock_TimeA. That is, the time of one clock cycle when the operating frequency of the current clock signal is used is Clock_TimeA.

(2) Set the previous cycle time to Clock_TimeB. In other words, the time of one clock cycle when the operating frequency of the previous clock signal is used is set to Clock_TimeB.

(3) Set the new cycle time as Clock_TimeN. That is, the time of one clock cycle when the operating frequency of the new clock signal is used is set to Clock_TimeN.

(4) The minimum transition value of the procedure determination is set to Delta_Convg. That is, if the absolute value of the difference between the current cycle time Clock_TimeA and the previous cycle time Clock_TimeB is less than or equal to Delta_Convg, it is determined that the best cycle time is obtained once.

(5) Set the clock arrival time to Clock_Arrive_Time. In other words, the time when the clock signal reaches the flip-flop circuit is called Clock_Arrive_Time.

(6) As a kind of start and end point, a flip-flop circuit, an input port for inputting a signal from another semiconductor chip to this sequential circuit, an output port for outputting a signal from this sequential circuit to another semiconductor chip, and Consider an input / output port for inputting / outputting a semiconductor chip and a signal. Incidentally, the start point and the end point are distinguished using three types of attributes: prefixed, postfixed, and unfixed. That is, when the clock arrival time Clock_Arrive_Time of the flip-flop circuit or the like cannot be accelerated earlier than this, the property of all-fixed is given. When the clock arrival time Clock_Arrive_Time of the flip-flop circuit or the like cannot be delayed later, the property of post-fixing is given. When the clock arrival time Clock_Arrive_Time of the flip-flop circuit or the like can be accelerated or delayed, the non-fixed property is given. Among these, the pre-fixing and the post-fixing may be provided in duplicate in one flip-flop circuit or the like.

Clock Arrival Time of the Input Port Clock_Arrive_Time cannot be fast because it is input from another semiconductor chip. Therefore, the fixed property is given to the input port. The clock arrival time Clock_Arrive_Time of the output port cannot be delayed because it is an output to another semiconductor chip. Therefore, the post-fixed attribute is given to the output port. Clock Arrival Time of I / O Port Clock_Arrive_Time cannot be quickly or delayed because it is an I / O with other semiconductor chips. Therefore, the input and output ports are given attributes of pre-fixed and post-fixed. The clock arrival time Clock_Arrive_Time of the flip-flop circuit can be quickly or delayed initially, but in this process, due to the limitation of the clock arrival time Clock_Arrive_Time to another flip-flop circuit, it cannot be made fast or delayed. do. Thus, flip-flop circuits are given attributes of pre-fixed, post-fixed, and non-fixed. The meanings of these pre-fixed, post-fixed, and non-fixed attributes are shown in Table 1 below.

Type of property Changing the arrival time of the clock signal Full Fix It is impossible to work before After fixing It is impossible to work later Unfixed It is impossible to work at the same time

(7) Prepare a list table of flip-flop circuits. This list table is shown in Table 2.

(a) (b) (c) (d) (e) (f) (g) REG1 Unfixed 0.0 REG2 Unfixed 0.0 REG3 Unfixed 0.0

The items in the list table of this flip-flop circuit include (a) the name of the flip-flop circuit of the target, (b) the attributes of the flip-flop circuit of the target, (c) the arrival time of the clock signal to the flip-flop circuit of the target, and (d) the target. The starting point name of the path that results in the worst slack when the flip-flop circuit is set as the end point, (e) the slack value SL of the path, and (f) the worst slack when the target flip-flop circuit is set as the starting point. The end name of the path to be used, (g) The slack value SL of the path. Here, the target flip-flop circuit refers to the flip-flop circuit which is focused on a certain path. In Table 2, it is assumed that there are three flip-flop circuits.

(8) The path having the worst slack value SL among the paths in the list table of the flip-flop circuit shown in Table 2 is called the worst path. In other words, the path having the smallest slack value SL is called the worst path. In addition, the combinational logic circuit constituting the worst path will be referred to as the worst combinational logic circuit.

<Initial setting (S11)>

Sets the initial value of the current cycle time Clock_TimeA and the initial value of the minimum transition value Delta_Convg. Current cycle time The initial value of Clock-TimeA sets the cycle time that can be realized. All flip-flop circuits are extracted from the net constituting the sequential circuit, and the target flip-flop circuit name is entered in the items of the list table of the flip-flop circuit shown in Table 2. Initially, among the items in the list table of the flip-flop circuit, (b) all the attributes of the target flip-flop circuit are set to non-fixed. Among the items in the list table of the flip-flop circuit, (c) the arrival time of the clock signal to the target flip-flop circuit is set to all zeros. Then, Table 2 is completed.

<Path analysis (S12)>

For all flip-flop circuits, the flip-flop circuit analyzes the pass at which the start or end point is, and lists the worst slack value SL in consideration of the clock arrival time Clock_Arrive_Time for each flip-flop circuit. By the path analysis, as shown in Table 3, the starting point name of the path which becomes the worst slack value SL when the target flip-flop circuit (d) in the list table of the flip-flop circuit is the end point, and (e) the slack value SL of the path, (f) the end name of the path which is the worst slack value SL when the target flip-flop circuit is taken as the starting point, and (g) the slack value of the path ( SL) is buried. That is, items (d) (e) (f) (g) are embedded.

(a) (b) (c) (d) (e) (f) (g) REG1 Unfixed 1.2 REG3 -2.4 REG2 0.7 REG2 Unfixed 0.3 REG3 -1.1 REG3 -1.3 REG3 Unfixed -0.9 REG1 2.5 REG1 1.6

<Condition judgment 1 (S13)>

If the slack value SL of the worst pass is positive, it is OK, and if it is negative, it is determined as NG. That is, if the slack value SL of the worst pass is positive, the slack value SL is positive in all passes, and this sequence circuit operates normally at the current Clock_TimeA. In Table 3, the worst path is a case where the flip-flop circuit REG1 is the end point and the flip-flop circuit REG3 is the start point, and the slack value SL is -2.4.

<Change of cycle time (S14)>

In condition judgment 1, when the slack value SL is positive, the cycle time is changed. When this processing block comes from this condition determination 1 (S13), it is changed to Clock_TimeN = (Clock_TimeA) / 2. That is, 1/2 of the current cycle time Clock_TimeA is set as the new cycle time Clock_TimeN.

On the other hand, when it comes to this process block from condition determination 2 (S18) mentioned later, it changes to Clock_TimeN = (Clock_TimeA + Clock_TimeB) / 2. That is, the cycle time located in the middle of the previous cycle time Clock_TimeB in which this sequential circuit operates normally and the current cycle time Clock_TimeA in which this sequential circuit cannot operate normally is referred to as a new cycle time Clock_TimeN.

Even when it comes to this processing block from condition determination 1 or when it comes to this processing block from condition determination 2, Clock_TimeB = Clock_TimeA (however, this process is not executed when it comes from condition judgment 2). The cycle time is updated by executing Clock_TimeA = Clock_TimeN in order. That is, the current cycle time Clock_TimeA is set to the previous cycle time Clock_TimeB (however, this process is not executed when it comes from condition judgment 2), and the new cycle time Clock_TimeN is set to the current cycle time Clock_TimeA. In addition, the list table of the flip-flop circuit is reset. That is, the list table of the flip-flop circuit shown in Table 2 is prepared again.

<End judgment (S15)>

This termination determination determines whether or not the cycle time of the clock signal has converged. Specifically, it is OK in condition determination 1 (S13), and when the absolute error between the previous cycle time Clock_TimeB and the current cycle time Clock_TimeA is smaller than the minimum transition value Delta_Convg, it is set to NG otherwise. That is, when the sequence circuit operates normally at the current cycle time Clock_TimeA, and the difference between the current cycle time Clock_TimeA and the previous cycle time Clock_TimeB converges within a certain range, it is determined that the best cycle time has already been obtained.

<Wire processing of clock signal (S16)>

Using the list table of the flip-flop circuit, the clock signal wiring process is performed so that the clock arrival time Clock_Arrive_Time satisfies the condition of this list table. Specifically, the clock signal is wired from the flip-flop circuit having the minimum clock arrival time Clock_Arrive_Time among all the flip-flop circuits. In this way, when the clock signal is wired and a flip-flop circuit that is wired beyond the clock arrival time Clock_Arrive_Time has occurred, the excess is added to the clock arrival time Clock_Arrive_Time of all the flip-flop circuits and then wired again from the beginning. By repeating this process, the clock arrival time Clock_Arrive_Time relatively matches the list table.

<Setting the arrival time of the clock signal (S17)>

If the slack value SL of the worst path is negative in the condition determination 1 described above, processing for setting the arrival time of this clock signal is performed. Here, the timing of the clock signal between the flip-flop circuit at the start of the worst pass and the flip-flop circuit at the end point is changed using the list table of the flip-flop circuit. The method of change depends on the type of attribute imparted to the flip-flop circuit at the start and end points. Specifically, there are three kinds of modification methods. In addition, the slack value of the worst pass is set to Slack_A.

(1) When the timing of both the start and end flip-flop circuits can be changed

The list table of the flip-flop circuit in this case is as shown in Table 3, and the state thereof is as shown in FIG. If the timing of the start point and the end point can be changed, the clock arrival time Clock_Arrive_Time of the flip-flop circuit of the starting point is accelerated by | Slack_A / 2 |, and the clock arrival time Clock_Arrive_Time of the flip-flop circuit of the end point is delayed by | Slack_A / 2 | . For example, in the case of the list table of the flip-flop circuit as shown in Table 3, the worst pass is the pass from the flip-flop circuit REG3 to the flip-flop circuit REG1 and Slack_A is -2.4. In addition, the flip-flop circuit REG3, which is the point of the worst pass, is also unfixed. Therefore, the clock arrival time of the flip-flop circuit REG1 is set to Clock_Arrive_Time = (1.2- (| -2.4 / 2 |)) = 0.0. That is, the clock arrival time Clock_Arrive_Time of the flip-flop circuit REG1 which is the end point is delayed by 1.2. Also, the clock arrival time Clock_Arrive_Time of the flip-flop circuit REG3 is set to (-0.9+ (| -2.4 / 2 |) = 0.3, that is, the clock arrival time Clock_Arrive_Time of the flip-flop circuit REG3 which is the time point is increased by 2.4. As a result, the slack value SL of the worst path of the flip-flop circuit REG1 can be zero.

(2) Only the flip-flop circuit at the time can change the timing

The list table of the flip-flop circuit in this case is as shown in Table 4, and the state thereof is as shown in FIG. When only the flip-flop circuit of the viewpoint can change the timing, the clock arrival time Clock_Arrive_Time of the flip-flop circuit of the viewpoint is made faster by | Slack_A |. For example, in the case of the list table of the flip-flop circuit as shown in Table 4, the worst path is the path from the flip-flop circuit REG3 to the flip-flop circuit REG1, and the attribute of the flip-flop circuit REG1, which is the end point, is post-fixed. For this reason, the clock arrival time Clock_Arrive_Time of the flip-flop circuit REG1 cannot be delayed further. Therefore, the flip-flop circuit REG1 is not changed, but the clock-floor time of the flip-flop circuit REG3 is changed to Clock_Arrive_Time = (-0.9+ | -2.4 |) = 1.5. That is, the clock arrival time Clock_Arrive_Time of the flip-flop circuit REG3 which is the time point is increased by 1.2. As a result, the slack value SL of the worst path of the flip-flop circuit REG1 can be zero.

(a) (b) (c) (d) (e) (f) (g) REG1 After fixing 1.2 REG3 -2.4 REG2 0.7 REG2 Unfixed 0.3 REG3 -1.1 REG3 -1.3 REG3 Unfixed -0.9 REG1 2.5 REG1 1.6

(3) Only the flip-flop circuit at the end point can change the timing

In this case, the list table of the flip-flop circuit is as shown in Table 5, and the state thereof is as shown in FIG. When only the end flip-flop circuit can change the timing, the clock arrival time Clock_Arrive_Time of the end flip-flop circuit is delayed by | Slack_A |. For example, in the case of the list table of the flip-flop circuit as shown in Table 5, the worst pass is the pass from the flip-flop circuit REG3 to the flip-flop circuit REG1, and the attribute of the flip-flop circuit REG3, which is the starting point, is fully fixed. For this reason, the clock arrival time Clock_Arrive_Time of the flip-flop circuit REG3 cannot be accelerated. Therefore, the clock arrival time of the flip-flop circuit REG1 is set to Clock_Arrive_Time = (1.2+ | -2.4 |) = 3.6 without changing the flip-flop circuit REG3. That is, the clock arrival time Clock_Arrive_Time of the flip-flop circuit REG1 which is the end point is delayed by 2.4. As a result, the slack value SL of the worst path of the flip-flop circuit REG1 can be zero.

(a) (b) (c) (d) (e) (f) (g) REG1 Unfixed 1.2 REG3 -2.4 REG2 0.7 REG2 Unfixed 0.3 REG3 -1.1 REG3 -1.3 REG3 Full Fix -0.9 REG1 2.5 REG1 1.6

(4) When both the start and end flip-flop circuits cannot change timing

The list table of the flip-flop circuit in this case is as shown in Table 6, and the state thereof is as shown in FIG. If both the flip-flop circuit at the start point and the flip-flop circuit at the end point cannot be changed in timing, nothing is done. That is, since the flip-flop circuit REG3 as the start point is pre-fixed and the flip-flop circuit REG1 as the end point is post-fixed, it is already impossible to adjust the timing of the clock signal in accordance with this worst path. In other words, the slack value SL of the worst pass cannot be zero.

(a) (b) (c) (d) (e) (f) (g) REG1 After fixing 1.2 REG3 -2.4 REG2 0.7 REG2 Unfixed 0.3 REG3 -1.1 REG3 -1.3 REG3 Full Fix -0.9 REG1 2.5 REG1 1.6

<Condition judgment 2 (S18)>

In the process of setting the arrival time of the clock signal (S17), (4) when both the flip-flop circuits at the start point and the end point cannot be changed in timing, the result is NG; otherwise, the result is OK. That is, (4) when both the start and end flip-flop circuits cannot be changed in timing, the timing of the supply of the clock signal to the flip-flop circuit cannot be adjusted in the current cycle time Clock_TimeA. (S14) Processing is performed. (1) In the case where the timing of the flip-flop circuit at the start point and the end point can be changed,

(2) when only the flip-flop circuit at the time can change timing, and,

(3) When only the flip-flop circuit at the end point can be changed in timing, since the timing of supply of the clock signal to the flip-flop circuit may be adjusted, processing at the current cycle time Clock_TimeA is continued (S19).

<Set properties of start and end points (S19)>

Here, the processing result of the arrival time setting S17 of the clock signal described above is reflected in the list table of the flip-flop circuit. Specifically, (2) When only the flip-flop circuit at the time point is processed when the timing can be changed, the post-fixed attribute is set for the flip-flop circuit at the time point. That is, as can be seen from Fig. 12, since the clock arrival time Clock_Arrive_Time of the flip-flop circuit REG3, which is the time point, is accelerated by 2.4, the attribute of the flip-flop circuit REG3 is set to post-fixing. This is because the clock arrival time Clock_Arrive_Time of the flip-flop circuit REG3 cannot be delayed any longer due to the relationship with the flip-flop circuit REG1. (3) When only the flip-flop circuit of the end point is processed when the timing can be changed, the fixed property is set for the flip-flop circuit of the end point.

That is, as can be seen from Fig. 13, since the clock arrival time Clock_Arrive_Time of the flip-flop circuit REG1 as the end point is delayed by 2.4, the attribute of this flip-flop circuit REG1 is set to all fixed. This is because the clock arrival time Clock_Arrive_Time of this flip-flop circuit REG1 cannot be made any faster.

(1) When the timing of the flip-flop circuits at the start and end points can be changed, the flip-flop circuit REG3 at the start point and the flip-flop circuit REG1 at the end point can all adjust the timing of the clock signal relatively. It is not fixed either.

As described above, according to the present embodiment, the clock signal wiring considering the propagation delay time Tpd of the combinational logic circuit can be automatically performed. For this reason, the time required for the design of the wiring can be greatly reduced. That is, since the clock signal wiring can be automatically made in consideration of the delay of the data path, the design efficiency can be improved.

Further, according to the present embodiment, since the timing for supplying the clock signal to the flip-flop circuit is distributed, the noise generated from the clock signal can be reduced.

Further, since the timing for supplying the clock signal is distributed, the timing for consuming power by the combinational logic circuit is also distributed, so that the peak current in the entirety of the sequence circuit can be suppressed low. For this reason, the wiring for supplying power to the flip-flop circuit and the combination order circuit can be made thinner than when the timing for supplying the clock signal is not dispersed.

In addition, this invention is not limited to the said embodiment, It can variously change. For example, the relationship between the high and the low in the above-described embodiments may be changed. That is, the above-described flip-flop circuit 10 is replaced with a flip-flop circuit that operates in synchronization with the falling edge of the internal clock signal ICLK. Alternatively, the above-described latch circuits 11 and 40 are replaced with latch circuits that output the value of the data input signal DIS as the data output signal DOS while the internal clock signal ICLK is low. Each of the above embodiments can also be realized by using the signals in which the low and high of each signal are changed.

In the above embodiment, the sequential circuit has been described as an example, but the present invention can be applied to any circuit having a plurality of combinational logic circuits and a plurality of flip-flop circuits connecting the plurality of combinational logic circuits.

Furthermore, for each of the processes described in the above-described third and fourth embodiments, a program for executing each of these processes is stored in a recording medium such as a floppy disk, a compact disc-read only memory (ROM), a ROM, a memory card, or the like. It is possible to record and distribute in the form of a recording medium. In this case, the above-described embodiment can be realized by reading and executing the recording medium on which the program is recorded on a computer for design development.

In addition, a computer may be provided with other programs, such as an operating system and a separate application program. In this case, a program for invoking a program for realizing processing equivalent to the present embodiment may be recorded on the recording medium by utilizing another program included in the computer.

Moreover, such a program can be distributed as a carrier through a network rather than in the form of a recording medium. The program transmitted on the network in the form of a carrier wave can be received by a computer and executed by the computer, thereby implementing the above-described third and fourth embodiments.

In addition, when a program is recorded on a recording medium or when a network is transmitted as a carrier wave, the program may be encrypted or compressed. In this case, a computer reading a program from these recording media or carriers needs to execute the program after decoding or decompressing the program.

As described above, according to the flip-flop circuit with the delay function according to the present embodiment, since the internal clock signal rises with a constant delay time after the external clock signal rises, the flip-flop circuit with the delay function is added. Even if the arrival of the data input signal to the installed flip-flop circuit arrives late by the delay time, the flip-flop circuit can correctly receive the data input signal. Therefore, the sequential circuit using the flip-flop circuit to which this delay function was added can operate with the external clock signal of a short period.

In addition, according to the automatic design method of the clock signal wiring in the semiconductor integrated circuit according to the present invention, the clock signal wiring in consideration of the propagation delay time of the combined logic circuit can be automatically performed. You can cut the time required.

Here, although embodiment for easy understanding of this invention was disclosed, this invention can be implement | achieved in various forms in the range which does not deviate from the mind. Accordingly, it is to be understood that the present invention includes modifications that do not depart from the spirit of the invention described in all possible forms and claims.

Claims (26)

A delay circuit which receives an external clock signal and outputs an internal clock signal having a predetermined delay time with respect to the external clock signal; And a data holding output circuit for inputting a data input signal and the internal clock signal and maintaining the value of the data input signal in synchronization with the internal clock signal and outputting the data input signal as a data output signal. Flip-flop circuit. The flip-flop circuit with a delay function according to claim 1, wherein said delay circuit is configured by connecting an even number of inverters in series. 2. The data holding output circuit of claim 1, wherein the data holding output circuit comprises a flip-flop circuit that receives and holds the data input signal when the internal clock signal rises or falls, and outputs the same as the data output signal. Flip-flop circuit with delay function added. 2. The data storage device of claim 1, wherein the data retention output circuit receives the data input signal while the internal clock signal is at a first level and outputs the data input signal as the data output signal. And a latch circuit for holding the data input signal received while being at one level and outputting the data input signal as the data output signal. 5. The pulse signal according to claim 4, wherein the internal clock signal output from the delay circuit is input and is shorter in width than the first level in one clock cycle of the internal clock signal in synchronization with the internal clock signal. And a pulse signal generation circuit for outputting the signal to the latch circuit. The pulse signal generating circuit of claim 5, A first inverter having an odd number of inverters connected in series and having the internal clock signal input from one side and an inverted internal clock signal output from the other side, A NAND circuit for inputting the internal clock signal and the inverted internal clock signal and outputting an inverted pulse signal; And a second inverter configured to receive the inverted pulse signal and output the pulse signal. A semiconductor integrated circuit, comprising: a flip-flop circuit to which a delay function according to claim 1 is added. The flip-flop circuit of claim 7, wherein a plurality of flip-flop circuits having a delay function are provided, and at least one of the flip-flop circuits having a plurality of delay functions is different from a flip-flop circuit having a different delay function. A semiconductor integrated circuit having a delay time. A semiconductor integrated circuit, which is designed by performing logic synthesis after registering flip-flop circuits with delay functions having different delay times as described in claim 8 as libraries, respectively. A circuit design method for a circuit having a plurality of combinational logic circuits and a plurality of flip-flop circuits connecting the combinational logic circuits, Performing a logic synthesis using a library of a normal flip-flop circuit, Calculating timing under which the output signal of the combined logic circuit is delayed with respect to the clock signal when timing analysis is performed based on the logic synthesis and operated with a clock signal of a desired speed; And performing a logic synthesis again by substituting a library used for logic synthesis with a library to which a flip-flop circuit with a delay function with a delay circuit having a delay time corresponding to the delay time is added is added. Circuit design method. The flip-flop circuit of claim 10, wherein the library includes a flip-flop circuit having a plurality of delay functions incorporating delay circuits having different delay times. In case of replacing the flip-flop circuit of the rear end of the combined logic circuit having the delay time with the flip-flop circuit to which the delay function is added, the delay function having a delay time longer than the delay time and having the smallest delay time is added. A circuit design method using a flip-flop circuit. The method of claim 11, wherein the library is provided with a delay time generation circuit for delaying and outputting an input signal for a predetermined time. And when the hold violation occurs, inserting the delay time generation circuit between the flip-flop circuit to which the hold violation occurs and the combinational logic circuit. An automatic design apparatus for clock signal wiring in a semiconductor integrated circuit having a plurality of combinational logic circuits and a plurality of flip-flop circuits provided between the combinational logic circuits, Path analysis means for setting a clock signal at a predetermined cycle time and analyzing a path at which the flip-flop circuit starts or ends with respect to all flip-flop circuits, and obtaining the worst slack value for each flip-flop circuit; Of all the flip-flop circuits, the path having the worst slack value is found as the worst path, and the timing of the output signal from the worst combination logic circuit constituting the worst path reaches the clock signal in the worst path. First condition determining means for determining whether or not it is timely; In the first condition determining means, when it is determined that the timing of the output signal from the worst combination logic circuit matches the arrival time of the clock signal of the worst path, the cycle time of the clock signal is further shortened. Cycle time resetting means for In the first condition determining means, when it is determined that the timing of the output signal from the worst combination logic circuit does not coincide with the arrival time of the clock signal of the worst pass, the front end flip-flop circuit of the worst combination logic circuit. And arrival time setting means for adjusting the arrival time of the clock signal in at least one flip-flop circuit in the subsequent flip-flop circuit so that the output signal from the worst combination logic circuit is set in time. Automatic design device for clock signal wiring. 15. The non-fixation method according to claim 13, wherein the arrival time setting means includes a non-fixation that may speed up or delay the arrival time of the clock signal applied to the flip-flop circuit, and a full fixation that cannot accelerate the arrival time of the clock signal. And adjusting said arrival time of said clock signal on the basis of three attributes of post-fixing which cannot delay the arrival time of a clock signal. 15. The second condition according to claim 14, wherein after setting the arrival time of the clock signal, the second condition for determining whether the arrival time of the clock signal could be adjusted so that the output signal from the worst combinational logic circuit is in time. Further comprising a judging means, When it is determined that the arrival time of the clock signal cannot be adjusted by the second condition determining means, the cycle time resetting means sets the cycle time of the clock signal to be longer. Automatic design device. 16. The non-fixed, the power supply according to claim 15, wherein when it is determined that the supply timing of the clock signal can be adjusted by the second condition determining means, the flip-flop circuit at the front and rear ends of the worst combination logic circuit is used. And an attribute setting means for changing a required attribute during fixing and post-fixing. 17. The automatic design apparatus for clock signal wiring according to claim 16, wherein said path analysis means is executed again after changing the attribute of said flip-flop circuit by said attribute setting means. 17. The end determination means according to claim 16, wherein after resetting the cycle time, the cycle time currently set is compared with the cycle time previously set, and the difference is within a predetermined value, the end determination means for determining that the best cycle time has been obtained. An automatic design apparatus for clock signal wiring, further comprising: a. 19. The wiring processing of the clock signal according to claim 18, wherein when it is determined that the best cycle time has been obtained by the end determining means, the wiring process of the clock signal is performed so that the arrival time of the clock signal is satisfied for each of the plurality of flip-flop circuits. An automatic design apparatus for clock signal wiring, further comprising wiring processing means for performing the processing. A method for automatically designing clock signal wiring in a semiconductor integrated circuit having a plurality of combinational logic circuits and a plurality of flip-flop circuits provided between the combinational logic circuits, A pass analysis step of setting a clock signal at a predetermined cycle time and analyzing a path at which the flip-flop circuit starts or ends with respect to all flip-flop circuits, and obtaining the worst slack value for each flip-flop circuit; The path having the worst slack value among all the flip-flop circuits is found as the worst path, and the timing of the output signal from the worst combination logic circuit constituting the worst path is the arrival time of the clock signal in the worst path. A first condition determination step of determining whether or not In the first condition determination step, when it is determined that the timing of the output signal from the worst combination logic circuit does not coincide with the arrival time of the clock signal of the worst path, the cycle time of the clock signal is further shortened. Cycle time reset process, In the first condition determination step, when it is determined that the timing of the output signal from the worst combination logic circuit does not coincide with the arrival time of the clock signal of the worst pass, the front end flip-flop of the worst combination logic circuit. And an arrival time setting step for adjusting the arrival time of the clock signal in at least one flip-flop circuit of the circuit and the subsequent flip-flop circuit so that the output signal from the worst combination logic circuit is set in time. Automatic design of clock signal wiring 21. The non-fixing method according to claim 20, wherein in the arrival time setting step, non-fixation that may speed up or delay the arrival time of the clock signal applied to the flip-flop circuit; And adjusting the arrival time of the clock signal on the basis of three attributes of post-fixing, which cannot delay the arrival time of the clock signal. 22. The second condition according to claim 21, wherein after the setting of the arrival time of the clock signal, the second condition for determining whether the arrival time of the clock signal could be adjusted so that the output signal from the worst combinational logic circuit is in time. Further comprising a judgment process, When it is determined that the arrival time of the clock signal cannot be adjusted in the second condition determination step, the cycle time reset step sets the cycle time of the clock signal to be longer. Auto design method. 23. The non-fixed, the front circuit according to claim 22, wherein when it is determined that the supply timing of the clock signal can be adjusted in the second condition determination process, the flip-flop circuits at the front and rear ends of the worst combination logic circuit are used. And an attribute setting step of changing the necessary attributes during the fixation and the post-fixing. 24. The automatic design method of a clock signal wiring line according to claim 23, wherein the path analysis step is executed again after changing the property of the flip-flop circuit in the property setting step. The end determination step according to claim 24, wherein the cycle time currently set after the cycle time resetting step is compared with a cycle time previously set, and if the difference is within a predetermined value, an end determination step for determining that the best cycle time has been obtained. The automatic design method of the clock signal wiring characterized in that it further comprises. 26. The method of claim 25, wherein when it is determined that the best cycle time has been obtained in the termination determination step, wiring processing of the clock signal is performed so that the arrival time of the clock signal is satisfied for each of the plurality of flip-flop circuits. An automatic design method for clock signal wiring, further comprising a wiring processing step.