KR20000022240A - Reproduction of information signal from record carrier - Google Patents

Abstract

PURPOSE: A regenerative apparatus capable of interpreting information from a medium for writing is provided with additional digital components. The rate of specific clock frequency and bit frequency is a certain figure N. CONSTITUTION: A medium for writing(4) interprets information from reading part(2) and input to A/D invertor. The invertor inverts the information with a specific clock frequency, and the information goes through bit sensing station(24) and arrives at output terminal(28). The specific bit frequency FB of the bit sensing station(24) looks up the bit sequence. Both FB and FS have no relation with velocity of the head(6) and FS/FB is a certain figure N representing sample number per bit from A/D invertor. N detects from bit sensing station(24).

Description

Apparatus for reproducing information signal from record carrier

The present invention relates to an apparatus for reproducing an information signal from a recording medium. Such devices are well known in the art. See, for example, US Pat. No. 5,569,912, which is a document D1 in the list of related documents described later in this specification.

The apparatus described above may have an SDAT form or a DCC form or a helical scan method. In all such devices, at least one readhead reads the information signal from the track on the record carrier, while the head moves with respect to the track at a particular speed. The recording medium is configured to be conveyed at a nominal speed during the reproduction process so that an information signal having an almost constant bit rate can be reproduced from the recording medium.

It is an object of the present invention to provide a reproducing apparatus which is more versatile and can read information from a recording medium at various speeds.

According to the present invention, the reproducing apparatus reproduces an information signal from a recording medium,

Reading means (6, 8) having at least one read head (6) for reading an information signal from a track on the record carrier (4) and for reading the information signal from the track;

-A / D conversion means (12, 34) for A / D converting the information signal read from the recording medium using a specific clock frequency f _s in response to the first control signal cs1,

Bit detection means 24 having an input connected to said A / D conversion means and configured to retrieve a bit sequence using a specific bit frequency f _b from a signal applied to said input,

Output means 28 for supplying said bit sequence;

Means for deriving the first control signal;

A reproduction device comprising means (30) for deriving said specific bit frequency,

The means for deriving the first control signal comprises means (48, 60) for deriving a second control signal (cs2), which is a measure of the relative speed of at least one readhead relative to the track, and the bit frequency. Means 30, 70, 72 for deriving a third control signal cs3 having a and a means 84 for deriving a first control signal from the second and third control signals.

The present invention is based on the idea of providing an A / D converter and an additional digital component such as an equalizer and bit detection means, wherein the device has a value N where the ratio between a particular clock frequency and the bit frequency is constant. have. This is accomplished by two control loops, one coarse control loop and a fine control loop. The coarse control loop generates a second control signal and causes the A / D converter to supply a substantially constant number of N samples per bit to be detected regardless of the relative speed of the readhead relative to the track. To control. In addition, the fine control loop generates a third control signal and controls the specific clock frequency to correct a deviation of a specific clock frequency expressed by the number of samples per bit from the value of N samples per bit.

As a result, even if the means for deriving the specific bit frequency described above has a small capture range, the apparatus of the present invention can control very quickly in accordance with the situation of N samples per bit.

These and other inventions of the present invention will become more apparent with reference to the following preferred embodiments, which are described with reference to the accompanying drawings in which:

1 shows an embodiment of an apparatus according to the invention,

2 is a view showing the addition of an output buffer to the device shown in FIG.

3 shows another embodiment of an A / D converter in the apparatus shown in FIG.

Figure 4 shows an embodiment of the equalizer in the apparatus shown in Figure 1,

Fig. 5 shows magnitude characteristics as a function of frequency of the information signal read out from the recording medium, for two different speeds of the recording medium during the reproduction process;

6 likewise shows the filter curve of the equalizer as a function of frequency for two different velocities of the record carrier,

FIG. 7 shows a capture range of the phase locked loop in the apparatus shown in FIG. 1.

1 shows an embodiment of a playback apparatus according to the present invention. The apparatus includes a reading section 2 for reading information from the recording medium 4. The readout has at least one readhead 6 and typically further comprises a preamplifier 8. The output of the reading unit 2 described above is connected to the input 10 of the A / D converter 12 having the output 14. The A / D converter 12 samples the information read from the track on the recording medium 4 using a specific clock frequency (i.e., sampling) f _s and takes a sample of the information signal having the above specified clock frequency. To the output 14 of.

The equalizer 16 is usually installed in the above apparatus. However, the equalizer 16 is not necessary to explain the present invention, and can be omitted. The input 18 of the equalizer 16 is connected to the output! 4 of the A / D converter 12, and the output of the equalizer 16 is connected to the input 22 of the bit detector 24. In addition, the output 26 of the bit detector 24 is connected to the output terminal 28.

The bit detector 24 described above is configured to retrieve a bit sequence from a signal applied to its input 22 using a specific bit frequency f _b .

The apparatus further includes a generation circuit 30 for generating a bit frequency f _b and a generation circuit 32 for generating a clock frequency f _s . The generation circuit 32 includes a phase comparator 70, a loop filter 72, and a voltage controlled oscillator 74 as a phase locked loop. At this time, the first input of the phase comparator 70 is connected to the output of the equalizer 16, and the second input of the phase comparator 70 is connected to the output of the oscillator 74. The output of the phase comparator 70 is connected to the input of the loop filter 72 having the output connected to the input of the oscillator 74 via the signal combiner 76. In addition, the output of the oscillator 74 is further connected to the clock input of the bit detector 24.

The generating circuits 30 and 32 generate frequencies f _b and f _s , respectively, such that f _s / f _b = N, regardless of the relative speed of the head 6 with respect to the track on the recording medium to be read. Where N is a constant but need not be a constant with an integer value.

The value N described above indicates the number of samples per bit to be detected by the bit detector 24 and to be generated by the A / D changer 12.

The A / D converter 12 converts the information signal read out from the recording medium using the specific clock frequency f _s described above in response to the first control signal cs1. In this embodiment, this clock signal is generated by a voltage controlled oscillator 34 which is part of the loop 32 and supplies the clock frequency f _s to the clock input 36 of the A / D converter 12. This clock frequency f _s is also supplied to the clock input 80 and converter 82 of the equalizer 16. Converter (82) has the form of a frequency divider, divides a given frequency f _s to its input by N and supplies a frequency f _s / N for its output. This output is connected to another input of the signal combiner 76.

Drive motors 40 and 42 are provided to convey the recording medium 4 in the direction indicated by the arrow 44 or in the reverse direction thereof. When driven in the direction indicated by arrow 44, the record carrier passes from feed reel 46 through roller 50 to readhead 6 and friction roller 48, and again through roller 52 to wind reel 56. Is transferred to). The friction roller 48 is provided with a taco generator for supplying tacho pulses through the line 58 toward the transducer 60. Drive signals for driving the drive motors 40, 41 are supplied through their terminals 62a, 62b and 64a, 64b, respectively.

The transducer 60 generates the second control signal cs2 in response to the taco pulse generated by the taco generator connected to the friction roller 480. This second control signal cs2 is a track on which the readhead reads out the information signal. This second control signal cs2 is supplied to the input 82 of the signal synthesizing unit 84. The second input of this synthesizing unit 84 corresponds to the measured value of the relative speed of the readhead 6. The third control signal cs3 is supplied through 86. The third control signal cs3 corresponds to the output signal of the loop filter 72 inside the PLL 30.

The operation of the device is described in more detail below. In this case, it is assumed that the recording medium is driven at a specific speed v ₁ . Accordingly, taco pulses are supplied to the transducer 60 and the transducer 60 generates a second control signal cs2 in response thereto. The second control signal cs2 is supplied to the oscillator 34 to generate a clock frequency f _s supplied to the A / D converter 12. In response to this, the A / D converter 12 samples the information signal read out from the recording medium so that approximately N samples per bit to be detected are generated. As the speed of the record carrier changes, i.e. increases or decreases, the frequency of the generated taco pulses increases or decreases. As a result, the clock frequency f _s increases or decreases. However, if the recording medium speed is increased (decreased) in this way, the information signal is read at an increased (decreased) speed and this information signal is sampled using the increased (decreased) clock frequency f _s , thereby Similarly, regardless of the speed of the recording medium, approximately N samples per bit detected are generated by the A / D converter 12.

Thus, the control loop consisting of components 48, 60, and 34 constitutes a coarse control loop that causes an approximately constant number of samples per bit to be generated at the output of the A / D converter 12. At this time, for example, N may be selected as three.

The equalizer 16 also receives a clock frequency f _s . FIG. 4 shows an embodiment of the equalizer 16, FIG. 5 shows an example of the magnitude characteristic M ₁ as a function of the frequency of the information signal read out from the recording medium at the specified speed v ₁ , FIG. Denotes a frequency characteristic of the equalizer 16 at the specific recording medium speed v ₁ as a curve H ₁ . At this time, the magnitude characteristic M ₁ has a constant magnitude M ₁ (f _b ) at the bit frequency f _b .

The delay element denoted by T in the equalizer shown in FIG. 4 is controlled by the clock frequency f _s and forms a delay time T equal to 1 / f _s . By this delay, the equalizer 16 shown in FIG. 4 exhibits the frequency characteristic H ₁ shown in FIG.

When the speed of the recording medium is changed, such as by reducing the speed of the recording medium by 2 times, the magnitude characteristic of the signal read out from the recording medium is reduced by 2 times, and the characteristic M _{2 shown} in FIG. At this time, the magnitude M ₂ (f _b ′) at the new bit frequency f _b ′ is equal to M ₁ (f _b ). Due to the control loop consisting of components 48, 60 and 34, the clock frequency f _s changes (decreases) at the same rate of two. As a result, the delay inside the equalizer shown in Fig. 4 is changed in that its delay time increases by the same double. This causes the frequency characteristic H ₂ shown in FIG. Therefore, this characteristic H ₂ is reduced to the same magnitude as the magnitude characteristic M ₂ of the information signal read out from the recording medium.

Thus, the function of the equalizer 16 is similarly read out by the equalizer 16 from the recording medium, regardless of the speed of the recording medium, under the control of the clock frequency f _s generated by the oscillator 34. To equalize the signal correctly.

The conversion section 82 is supplied at its output to the oscillator 74 via the synthesis section 76 to generate a control signal for setting the oscillation section 74 to the frequency f _s / N.

At this time, it should be noted that the PLL 30 controls the frequency of the oscillator 74 to be f _b . However, the PLL 30 has a smaller capture range, for example, 10% smaller or larger than f _b , see FIG. 7. Using a control signal applied to VCO 74 via line 90 and signal synthesis 76, this VCO 74 is quickly moved to the vicinity of f _b as shown by line 92 in FIG. Is set. As described later, when fine control is not performed using the control signal cs3, the VCO 74 maintains the frequency value fb &_quot;, for example, the disturbance generated by the change in the speed of the recording medium, As shown by curve 92 in FIG. 7, the frequency is out of the capture range of the loop 30, causing the PLL to lose synchronization.

However, the phase comparator 70 and the loop filter 72 generate the control signal which is the control signal cs3 corresponding to the measured value of the frequency deviation of the VCO 74 from the required bit frequency f _b . At this time, it should be noted that the required bit frequency f _b is not a constant frequency value, but a value that is converted according to the speed of the recording medium.

The control signal cs3 is supplied to the second input 86 of the signal synthesizing unit 84. The control signal cs3 is a fine control signal and controls the frequency of the VCO 74 to be a required bit frequency. This is illustrated by line 94 in FIG. 7. For example, the disturbance caused by the change in the recording medium speed causes the frequency of the VCO 74 to fluctuate. However, this change is kept within the capture range of the loop 30, as shown by curve 94 in FIG. 7, so that the PLL 30 remains synchronized.

FIG. 2 shows a buffer memory 100 that may be connected to the output terminal 28 of the apparatus shown in FIG. 1. This buffer memory 100 performs a function as a FIFO memory. The bit sequence detected by the bit detector 24 described above can be stored in the buffer memory using a specific frequency f _in equal to the frequency f _b generated by the oscillator 74.

The detected bits may be retrieved from the buffer memory 100 using the read clock frequency f _out . This frequency f _out may have a value smaller or larger than f _in . In the former case, the buffer memory 100 is gradually filled with information, causing an overflow. In the case of the latter, becomes the buffer is gradually emptied until no bit is left not more that can be used to supply the required data rate of f _out. In order to solve this problem, the buffer memory 100 described above has an output 102, in which a signal indicating the degree of filling of the buffer memory 100 is generated. This signal is converted into a control signal by the converter 104 and supplied to the motor control unit 106. The motor controller 106 supplies drive signals to the inputs 62a, 62b; 64a, 64b of the motors 40, 42, respectively.

If f _out is greater than f _in , the filling amount decreases. As a result, a control signal is generated so that the feed speed of the recording medium 4 is increased. On the other hand, when f _out is smaller than f _in , the filling information increases. As a result, a control signal is generated so that the conveying speed of the recording medium 4 decreases. In addition to the coarse control loops through components 60, 82 and 34, the fine control loops 30 through components 70, 72, 82 and 34 themselves, as described above, are adapted to varying feed rates of the recording medium. Transforms automatically.

3 shows another embodiment of the A / D converter 12 shown in FIG. The A / D converter shown in FIG. 3 includes an A / D converter 110 that receives a sampling frequency generated by the oscillator 112 via a clock input 114. In this case, the sampling frequency generated by the oscillator 112 may have a value greater than f _s . The sample generated by the converter 110 is supplied to a down sampler, which is given to its input 118 in response to the first control signal cs1 applied to the control signal input 120. Downsample the signal. At its output 14, an information signal sampled at the frequency f _s is generated.

At this time, the down sampler 116 not only downsamples an array of a plurality of samples applied to its input 118, but also performs interpolation if necessary to obtain its output signal. It should be noted that

Although the present invention has been described with reference to its preferred embodiments, it is obvious that these embodiments are not given to limit the invention. Accordingly, various modifications may be made by those skilled in the art to which the present invention pertains without departing from the scope of the present invention as defined by the appended claims. As an example, the control signal cs2 described above need not be derived from the taco impulse supplied by the taco generation connected to the friction roller 48. This second control signal is derived in a different way, such as a signal (e.g., a control pulse signal) recorded inside a track on which the recording medium 4 travels (e.g., in the longitudinal direction). Can be. Moreover, in another embodiment, the third control signal cs3 may be generated in a manner different from that described above, ie from the output 102 of the buffer memory 100. In another embodiment, f _out is derived, for example, from component 82 shown in FIG. 1 and has a value equal to f _s / N. According to this, the control signal present at the output 102 of the buffer memory 100 corresponds to an integer measurement of f _b -f _s / N, and thus an integer measurement of the control signal cs3. Moreover, the recording medium may be a longitudinal recording medium or a disc shaped recording medium in magnetic or optical form.

Moreover, the present invention includes each of these novel features or combinations of these features.

Related literature

(D1) USP 5,569,912 (PHN 14.875)

Claims (6)

Reproduces an information signal from a recording medium, Reading means (6, 8) having at least one read head (6) for reading an information signal from a track on the record carrier (4) and for reading the information signal from the track; -A / D conversion means (12, 34) for A / D converting the information signal read from the recording medium using a specific clock frequency f _s in response to the first control signal cs1, Bit detection means 24 having an input connected to said A / D conversion means and configured to retrieve a bit sequence using a specific bit frequency f _b from a signal applied to said input, Output means 28 for supplying said bit sequence; Means for deriving the first control signal; A reproduction device comprising means (30) for deriving said specific bit frequency, The means for deriving the first control signal comprises means (48, 60) for deriving a second control signal (cs2) which is a measure of the relative speed of the at least one readhead relative to the track; Means (30, 70, 72) for deriving a third control signal (cs3) having a relationship; and means (84) for deriving a first control signal from the second and third control signals. Playback device. The method of claim 1, And a voltage controlled oscillation means (34) for generating said specific clock frequency in response to said first control signal (cs1). The method according to claim 1 or 2, And a digital equalizer filter means (16) for performing an equalization process on the digitalized information signal read from the recording medium to obtain an equalized information signal using the specific clock frequency. The method of claim 3, wherein And the means (30) for deriving the specific bit frequency has a digital form and is configured to derive the specific bit frequency from the equalized information signal. Reproduces an information signal from a recording medium, Reading means (6, 8) having at least one read head (6) for reading an information signal from a track on the record carrier (4) and for reading the information signal from the track; -A / D conversion means (12, 34) for A / D converting the information signal read from the recording medium using a specific clock frequency f _s in response to the first control signal cs1, Bit detection means 24 having an input connected to said A / D conversion means and configured to retrieve a bit sequence using a specific bit frequency f _b from a signal applied to said input, Output means 28 for supplying said bit sequence; Means for deriving the first control signal; A reproduction device comprising means (30) for deriving said specific bit frequency, The means for deriving the first control signal further comprises generating a first control signal such that the specific clock frequency and the bit frequency have a constant ratio N relative to each other, regardless of the relative speed of the at least one readhead relative to the track. Playback equipment, wherein N is a positive integer value. Reproduces an information signal from a recording medium, Reading means (6, 8) having at least one read head (6) for reading an information signal from a track on the record carrier (4) and for reading the information signal from the track; -A / D conversion means (12, 34) for A / D converting the information signal read from the recording medium using a specific clock frequency f _s in response to the first control signal cs1, Bit detection means 24 having an input connected to said A / D conversion means and configured to retrieve a bit sequence using a specific bit frequency f _b from a signal applied to said input, Output means for supplying said bit sequence; Means for deriving the first control signal; A reproduction device comprising means (30) for deriving said specific bit frequency, The means for deriving the first control signal is supplied with approximately N samples per bit by the A / D conversion means 12, 34, regardless of the state velocity of the at least one read head for the track. Deviation of the coarse control signal generating means 48 and 60 which derive the coarse control signal to generate a specific clock frequency f _s as much as possible, and the specific clock frequency expressed in samples per bit from the value of N samples per bit. And fine control signal generating means (30, 72, 72) for deriving a fine control signal (cs3) for calibrating the data, wherein N is a positive integer value.