KR20000003016A - Method for compiling of computer program - Google Patents

Abstract

PURPOSE: Method for compiling of computer program is provided to remove branch instruction in converting source code of program to code be able performed by data processing system. CONSTITUTION: The method comprises the steps of: fetching instruction, determining the instruction is branch instruction, determining target label is located afterward of the branch instruction when the instruction is branch instruction, determining the instruction converts conditional flag or existence of target label which referred from outside between the branch instruction and the target label when the target label is located afterward of the branch instruction, converting at least first instruction, which exists between the branch instruction and the target label, to second instruction which includes opposite condition from condition of the branch instruction and deleting the branch instruction.

Description

COMPILING METHOD FOR COMPUTER PROGRAM

The present invention relates to a method of compiling a program in a native language into another language, and more particularly, to a method of compiling by changing an execution condition of an instruction of a native program.

Compilation is a process of converting source code of a program written in a language recognizable by a person into code that can be executed in a data processing system. Compilation converts each statement in a program into one or more machine language statements.

Reduced instruction set computer (RISC) microprocessors and microcontrollers simplify the format of computer instructions, simplifying control logic, and using hardwired controls for faster operation. A feature of the RISC processor is that it can execute one instruction every clock cycle. This is accomplished by nesting two, three instructions to fetch, decode, and execute steps in a pipelined way.

In a RISC processor, pipeline data processing operates not only on the data flow but also on the flow of instructions. The instruction pipeline reads the next instruction that is continuously stored in memory while the previous instruction is executing on another segment. . In other words, the instruction fetch and execution steps are overlapped and executed simultaneously. The disadvantage of this method is that when a branch occurs in the flow of instructions, the pipeline must be emptied and all instructions read from memory after the branch instruction must be ignored. This adversely affects performance.

In order to solve this problem, hardware and software methods have been studied for a long time. One hardware solution is to make all instructions in the instruction set conditional executable and allow the programmer to add a branching condition directly to all instructions. Microprocessors manufactured by Advanced RISC Machines support this feature in hardware, eliminating branch instructions. However, this method is difficult for high-level language programmers to program directly.

In an embedded system, the program is usually stored in a ROM. Since the size of the ROM is directly related to the cost, it is necessary to create a small object file. The object file is a source code converted into machine code by a compiler. Therefore, there is a need for a compilation method that can reduce the size of the object file.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems, and removes the branch instruction in the process of converting the source code of the program into code that can be executed in the data processing system, and conditionally condition each instruction To provide a way to translate into executable instructions.

1 is a flow chart showing an operation procedure of a compiled program for compiling a computer program according to a preferred embodiment of the present invention.

According to a feature of the present invention for achieving the object of the present invention as described above, a method of compiling a computer program comprises: fetching an instruction; Determining whether the instruction is a branch instruction; If the instruction is a branch instruction, determining whether a target label of the branch instruction is located after the branch instruction; If the target label is located after the branch instruction, determining whether there is an instruction for changing a conditional flag in the region between the branch instruction and the target label or a target label referenced outside the region; When there is no instruction to change the condition flag and a label referenced outside the region, the at least one first instruction positioned between the branch instruction and the target label includes a condition opposite to a branch condition of the branch instruction; After converting to two instructions, deleting the branch instruction.

In a preferred embodiment, the first instruction located after the at least two branch instructions is converted to a second instruction that includes the result of ANDing conditions opposite to the branch conditions of the branch instructions.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The novel computer program compilation method of the present invention converts instructions placed between the branch instruction and the target label into conditional execution instructions. When compiling a program in a native language into another language, you can eliminate the program's branch instructions by adding execution conditions to the instructions placed between the branch instruction and the target label. The condition for converting instructions placed between the branch instruction and the target label into conditional execution instructions may include the target label after the branch instruction, and a flag change instruction or an external reference between the branch instruction and the target label. There should be no label. By converting instructions placed between the branch instruction and the target label into conditional execution instructions, the size of the compiled object code can be reduced to reduce the size of the memory. In addition, the execution speed of the program is improved.

As an example of how to compile a computer program, ARM 7 assembly language of ARM (Advanced RISC Machines) is described.

[Program 1]

CMP R1, R2

BEQ Label_1

Instr_1_1

Instr_1_2

… …

Instr_1_n

B Label_2

Label_1:

Instr_2_1

Instr_2_2

… …

Instr_2_n

Label_2:

… …

The result of converting the instruction of [Program 1] in the compiler of the present invention is as follows.

[Result 1]

CMP R1, R2

Instr_1_1NE

Instr_1_2NE

… …

Instr_1_nNE

Instr_2_1EQ

Instr_2_2EQ

… …

Instr_2_nEQ

… …

As shown in [Result 1], the branch instructions 'BEQ Label_1' and 'B Label_2' are deleted. Instructions between the branch instruction and the target label are each added with the opposite condition of the branch instruction. However, in a microprocessor such as ARM 7, even if a conditional execution instruction is added to the instructions, the code size is the same as that of a general instruction, and thus the code size does not increase. As a result, the size of the entire program can be reduced.

Looking at [Program 1] and [Result 1] in more detail, when R1 and R2 are compared in 'CMP R1, R2', when the values of R1 and R2 are the same by 'BEQ Label_1' (EQ) Label 1 Branch to If it is not the same (NE), the following command is executed. Therefore, the commands after BEQ Label_1 have the condition 'NE', that is, not equal. This is a condition opposite to the branch condition 'EQ (equal)' of the branch instruction. The condition under which the label 'Label_1' is executed is when the values of R1 and R2 are the same, so 'EQ' is added to the commands belonging to 'Label_1'.

Another example will be described with reference to [Program 2].

[Program 2]

L_00005:

ADD R14, R3, R1, LSL # 2

SUB R1, R1, # 1

STR R12, [R14, # 4]!

L_00006:

CMP R1, # 0

BLT L_00007

LDR R12, [R3, R1, LSL # 2]

CMP R12, R4

BGT L_00005

L_00007:

… …

[Result 2]

L_00005:

ADD R14, R3, R1, LSL # 2

SUB R1, R1, # 1

STR R12, [R14, # 4]!

L_00006:

CMP R1, # 0

LDRGE R12, [R3, R1, LSL # 2]

CMPGE R12, R4

BGT L_00005

L_00007:

… …

[Program 2] compares R1 with 0 at 'CMP R1, # 0'. As a result, if R1 is less than 0 (LT), the process branches to L_00007. Therefore, instructions between the branch instruction 'BLT L_00007' and the target label 'L_00007' are executed when R1 is greater than or equal to 0 (GE; Greater Than). As shown in [Result 2], 'GE' is added to the instructions between the branch instruction and the target label.

[Program 3] below shows the case where there are consecutive branch instructions.

[Program 3]

L_0001:

CMP R3, R4

BEQ L_0002

BLT L_0003

SUB R3, R3, R4

B L_0001

L_0002:

SUB R4, R4, R3

B L_0001

L_0003:

… …

[Result 3]

L_0001:

CMP R3, R4

SUBGT R3, R3, R4

SUBEQ R4, R4, R3

BGE L_0001

L_0003:

… …

The opposite conditions of 'EQ (equal)' and 'LT (less than)' are 'NE (not equal)' and 'GE (greater equal)' respectively, and the result of AND operation of the opposite conditions is 'GT' (greater than) '. Therefore, 'GT' is added to the first SUB command. The condition to execute the label 'L_0002' is when R3 and R4 are the same in 'BEQ L_0002', so 'EQ' is added to the second SUB instruction.

[Program 4] and [Program 5] below show an example in which the instruction following the branch instruction cannot be converted to a conditional execution instruction.

[Program 4] is a case where there is an instruction to change conditional flags between the branch instruction and the target label.

[Program 4]

Label_1:

CMP R1, R2

BEQ Label_2

ADD R3, R4

CMP R5, R6

SUB R7, R8

Label_2:

… …

[Result 4]

Label_1:

CMP R1, R2

ADDNE R3, R4

CMPNE R5, R6

SUBNE R7, R8

Label_2:

… …

Referring to [Result 4] of compiling [Program 4], it is determined whether to execute the ADD instruction and the second CMP instruction according to the result of the first comparison instruction 'CMP R1 and R2'. If the values of R1 and R2 are different (NE), if the second CMP is performed, the condition flag value may vary according to the values of R5 and R6. In [Program 4], the SUB instruction is programmed to be executed when the values of R1 and R2 are different. In [Result 4], the SUB instruction is programmed to be executed when the values of R5 and R6 are different. As a result, results may differ from those intended by the programmer.

Therefore, when there is an instruction for changing the value of the condition flag, such as CMP, between the branch instruction BEQ Label_2 and the target label Label_2, conditionally executing the instructions between the branch instruction BEQ Label_2 and the target label Label_2. Do not change it with a command.

Next, [Program 5] is another example in which an instruction following a branch instruction cannot be converted to a conditional execution instruction, and there is an externally referenced label between the branch instruction and the target label.

[Program 5]

Label_1:

CMP R1, R2

BEQ Label_2

ADD R3, R4, R5

Label_new:

SUB R4, R5, R6

Label_2:

TEQ R10, R10

BEQ Label_new

[Result 5]

Label_1:

CMP R1, R2

ADDNE R3, R4, R5

Label_new:

SUBNE R4, R5, R6

Label_2:

TEQ R10, R10

BEQ Label_new

The 'TEQ' instruction compares two operands for equality. Since the result of 'TEQ R10, R10' in the label 'Label_2' is true, a branch is made to the label 'Label_new'. Program 5 is programmed to execute the SUB command when branched by BEQ Label_new. As a result of converting the 'SUB' command to conditional execution command 'SUBNE', the 'SUB' command is not executed when branching to Label_new by 'BEQ Label_new'.

Therefore, when there is an externally referenced label (Label_new) between the branch instruction (BEQ Label_2) and the target label (Label_2), the instructions between the branch instruction (BEQ Label_2) and the target label (Label_2) are conditional execution instructions. Do not convert.

As described above, an operation procedure of a compilation program for converting instructions positioned between a branch instruction and a target label into a conditional execution instruction is illustrated in FIG. 1.

In step S10, the instruction is fetched. In the next step S20, it is determined whether or not the end of the program is completed. If it is the last time, the compilation is terminated.

In step S30, it is determined whether the fetched instruction is a branch instruction. If it is not a branch instruction, the method returns. If it is a branch instruction, the process proceeds to step S40 to determine whether a target label is located after the branch instruction. If the target label is not located after the branch instruction, the method returns. If the target label is located after the branch instruction, the process proceeds to step S50.

In step S50, it is determined whether there is an instruction for changing a conditional flag in the region between the branch instruction and the target label or a target label referenced outside the region. If there is no instruction to change the condition flag and a label referenced outside the region, the flow advances to step S60, and returns if there is a instruction to change the condition flag and a label referenced outside the region.

In step S60, all instructions located between the branch instruction and the target label are converted into a conditional execution instruction including a condition opposite to the branch condition of the branch instruction. The conditional execution instruction adds a condition to the original instruction, and executes the instruction when the condition is satisfied. If there are two or more branch instructions in a row, the instruction placed after the branch instructions is converted to a second instruction including the result of ANDing conditions opposite to the branch conditions of the branch instructions.

Another feature of the present invention is the range in which a branch instruction is fetched and looking for a target label indicated by the branch instruction, that is, the size of the window is variably set depending on whether the performance is focused on performance or code size. It is possible. In other words, if the size of the window is increased, the code size is greatly reduced. On the other hand, since all instructions in the window must be executed, the process of fetching and decoding the instructions that do not satisfy the condition must be performed. do. Fetching and decoding the instructions that aren't actually executed can slow performance. Therefore, the condition for converting instructions into conditional branch instructions can be changed depending on the compilation performance and code size required by the programmer or the system.

According to the present invention as described above, when compiling a program in a native language into another language, the branch instruction of the program can be eliminated by adding an execution condition to the instruction positioned between the branch instruction and the target label. As a result, the size of the compiled object code can be reduced, thereby reducing the size of the memory. In addition, the execution speed of the program is improved.

Claims (2)

In order to compile computer program instructions using a compiler: Determining whether the instruction is a branch instruction; If the instruction is a branch instruction, determining whether a target label of the branch instruction is located after the branch instruction; If the target label is located after the branch instruction, determining whether there is an instruction for changing a conditional flag in the region between the branch instruction and the target label or a target label referenced outside of the region; If there is no instruction to change the condition flag and a label referenced outside of the area, the at least one first instruction positioned between the branch instruction and the target label includes a condition opposite to the branch condition of the branch instruction. And converting the branch instruction to the second instruction. The method of claim 1, A first instruction placed after at least two branch instructions is converted into a second instruction comprising a result of ANDing conditions opposite to the branch conditions of the branch instructions; Way.