KR19990059133A - How to read data from synchronous static RAM - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method of reading data from a synchronous static RAM (SRAM).

2. Technical problem to be solved by the invention

In order to solve the problem that the cycle time of the memory device increases, the size of the device and the length of the signal line are not integrated, thereby making it difficult to generate and control the internal signal of the device.

3. Summary of the Solution of the Invention

By simultaneously generating two burst address sequences for selecting an address of a memory cell array for simultaneous operation, the device can be operated at high speed and a speed margin can be secured.

Description

How to read data from synchronous static RAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of reading data of a synchronous static random access memory (SRAM), and in particular, as the cycle time increases, the operation speed of the device is proportionally increased. The present invention relates to a method of reading data of a synchronous static RAM to solve a difficult problem.

Synchronous static RAM has a different address selection method than other static RAMs. This uses a burst address. When one address is input from the outside by a control signal, the other address is generated in the memory using a burst address counter.

Conventionally, data is continuously output after generating a burst address for address selection of a memory cell array at the same time. This process is described with reference to FIG. 1 as follows.

1 (a) and 1 (b) are functional diagrams for explaining a conventional method of reading data of a synchronous static RAM and waveform diagrams of respective signals in this case.

First, when the / ADSC signal, which is a signal for receiving external data, is enabled, the address register 12, which receives an address through the address buffer 11, is a memory cell according to an address stored during a first clock period. The word line of the array 15 is selected (t1 time in Fig. 1 (b)). At this time, the burst address counter 14 receives the burst address stored in the 2-bit burst address register 13 for the time t1 to generate a burst sequence to generate the bit line of the memory cell array 15 during the second clock period. (T2 time in Fig. 1 (b)). In this case, the four burst sequences generated by the burst address counter 14 may be, for example, (00, 01, 10, 11), (01, 00, 11, 10), (10, 11, 00, 01) or (11, 10, 01, 00) and the like.

Thereafter, the data of the selected memory cells of the memory cell array 15 is stored in the output register 16 for the time t3, i.e., four clocks from the falling edge of the third clock, and the four through the output buffer 17. Data (D1 to D4) are continuously output.

That is, when data is read from the synchronous static RAM, latches are provided in the address buffer and the output buffer so that four data are continuously output after two cycles of clock pass after the / ADSC signal is enabled.

In this case, as shown in FIG. 1A, the memory cell must be connected during the first clock period and the data of the selected memory cell must be brought to the output latch for one clock (second clock period). However, while the operation cycle time of the memory device increases to 200 MHz (5 ms), 300 MHz (3.3 ms) and 500 MHz (1 ms), the size of the element or the length of the internal signal line are not integrated. Accordingly, there is a problem that the time to operate for a given cycle time becomes too short, making it difficult to generate and control the internal signals of the device during that time.

Accordingly, the present invention is a synchronous type that facilitates high-speed operation of the device and secures a speed margin by simultaneously generating two burst address sequences for selecting an address of a memory cell array so that simultaneous operation is performed. Its purpose is to provide a method of reading data from a static RAM.

In accordance with another aspect of the present invention, there is provided a method of reading a data in a synchronous static RAM according to an embodiment of the present invention, selecting a word line of a memory cell array using an address stored in an address register during a first clock period, Selecting the first and second bit lines of the memory cell array by receiving a burst address for two clock periods to generate first and second burst sequences, and performing a third clock on the first data according to the first burst sequence. Storing the first output register after the period and outputting the second data, storing the second data according to the second burst sequence after the fourth burst period, and outputting the second data during the fourth clock period; Generating a third and fourth burst sequence during a clock period to select third and fourth bit lines of the memory cell array; Storing third data according to a third burst sequence in the first output register for a fifth clock period and then outputting the fourth data according to the fourth burst sequence to the second output register during a sixth clock period. And storing and outputting the stored data.

1 (a) and 1 (b) are block diagrams illustrating a conventional method of reading data of a synchronous static RAM and waveform diagrams of respective signals for explaining the same.

2 (a) and 2 (b) are block diagrams for explaining a method of reading data of a synchronous static RAM according to the present invention, and waveform diagrams for respective signals for explaining the same.

<Description of the symbols for the main parts of the drawings>

21: address register 22: 2-bit burst address register

23: first burst address counter

24: second burst address counter

25: memory cell array 26: first output register

27: second output register 28: output buffer

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 (a) and 2 (b) are functional diagrams for explaining the method of reading the data of the static RAM according to the present invention, and waveform diagrams of the signals in this case, in which the burst sequence is (00, 01, 10, 11). The case of) is shown.

First, when the / ADSC signal, which is a signal for receiving external data, is enabled, the address register 22, which has received an address through the address buffer 21, is stored in the memory cell array 26 according to the address stored during the first clock period. Is selected (t1 time in Fig. 2 (b)). At this time, the first burst address counter 24 reads the initial value of the burst address stored in the two-bit burst address register 23 for t1 time, generates two burst sequences 00 and 01, and stores the memory for the second clock period. The bit lines of the cell array 26 are selected (t1 and t2 times in FIG. 2 (b)). Thereafter, the data D1 of the memory cell selected according to the first burst sequence is stored in the first output register 27 for the third clock period (t3 time in FIG. 2 (b)) and the second burst sequence for the fourth clock period. Is stored in the second output register 28 (t4 time in Fig. 2 (b)).

On the other hand, from the first burst address counter 24 which receives an address from the burst address register 23 and generates a burst sequence during the third and fourth clock periods, the second burst address counter 25 is the third and the fourth. Four burst sequences 10 and 11 are generated to select the bit lines of the memory cell array 26 during the third and fourth clock periods (t3 and t4 times in FIG. 2 (b)). Thereafter, the data D3 of the selected memory cell is stored in the first output register 27 according to the third burst sequence for the fifth clock period (t5 time in FIG. 2B) and the fourth burst sequence for the sixth clock period. The data D4 of the selected memory cell is stored in the second output register 28 (t6 time in FIG. 2 (b)). Thereafter, the data stored in the first and second output registers 27 and 28 are continuously output through the output buffer 29.

In this way, by operating two cycles as if one cycle, it is possible to easily design a high-speed memory device using twice the cycle time.

As described above, according to the present invention, a sequence of burst addresses for selecting an address of a memory cell array is generated by dividing two by two to facilitate simultaneous operation, thereby facilitating high-speed operation of the device and reducing a speed margin. In addition, it is possible to easily design a high-speed synchronous memory device.

Claims (1)

Selecting a word line of the memory cell array using an address stored in an address register during a first clock period; Selecting first and second bit lines of a memory cell array by receiving a burst address during the first clock period and a second clock period to generate first and second burst sequences; Storing the first data according to the first burst sequence in a first output register for a third clock period and then outputting the first data; Storing second data according to the second burst sequence in a second output register for a fourth clock period and then outputting the second data; Generating third and fourth burst sequences during the third and fourth clock periods to select third and fourth bit lines of a memory cell array; Storing the third data according to the third burst sequence in the first output register for a fifth clock period and then outputting the third data; Storing the fourth data according to the fourth burst sequence in the second output register for a sixth clock period and then outputting the fourth data.