KR19990040491A - Voltage controlled oscillator circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillation circuit of a phase locked loop, comprising: a voltage-current converter for outputting a stable current by forming a current mirror by applying a control voltage from the outside; and outputting a reference voltage for maintaining a constant output voltage. A reference voltage generator circuit, a bias circuit for comparing and biasing an input reference voltage and a control voltage, and a differential inverter for receiving an output voltage of a previous stage and generating a constant output voltage under control of a stable current and a reference voltage. Therefore, the voltage-current converter receives a control voltage from an external source, forms a current mirror, outputs a stable current, and outputs a predetermined reference voltage which is started from the reference voltage generator circuit. Then, it takes a stable current and a reference voltage, biases it and outputs it, and the differential inverter receives an output voltage and maintains a stable voltage to output a proper frequency. Therefore, by using a phase locked loop, the clock driver is lowered to reduce noise in the microcomputer, thereby solving EMI problems.

Description

Voltage Controlled Oscillator For Phase Lock Loop

The present invention relates to a voltage controlled oscillator circuit, and more particularly, to a voltage controlled oscillator circuit of a phase locked loop circuit for removing noise in a microcomputer.

A phase-locked loop (PLL) is a circuit for controlling feedback by comparing phases of two signals. By using this principle, if the voltage-controlled oscillation circuit (VCO) is provided on one side and the crystal oscillation circuit on the other side, the frequency stability of the VCO circuit can be set to the same stability as the crystal oscillator generating the input frequency.

In general, an oscillation circuit that changes an oscillation frequency by an externally applied control voltage is called a voltage controlled oscillator circuit (VCO). Recently, oscillation frequency is directly proportional to the control DC input voltage. Therefore, the VCO, which converts the control voltage into frequency, that is, the V-F conversion circuit, plays an important role as an interface with the digital circuit.

In some microcomputers for CTV, electromagnetic interference noise (EMI) is a big problem. Recently, a large amount of electromagnetic interference noise in the UHF band has been removed by applying a grid line using metal 3, etc., but electromagnetic interference noise in the VHF band still remains to generate noise on the screen.

The main cause of this phenomenon is noise from the clock pads by the crystal oscillator, because a large clock driver is required to drive a clock of several MHz.

In order to solve the above problems, the present invention is to provide a voltage controlled oscillation circuit suitable for a phase locked loop circuit of a microcomputer for CTV to reduce electromagnetic interference noise (EMI).

1 is a block diagram showing the configuration of a PLL having a voltage controlled oscillator circuit according to the present invention:

FIG. 2 is a circuit diagram showing a configuration of a voltage controlled oscillation circuit according to the embodiment of the present invention shown in FIG.

* Explanation of symbols on the main parts of the drawings

10: phase comparator 20: low pass filter

30: voltage controlled oscillation circuit 32: voltage-to-current converter

34: reference voltage generating circuit 36: bias circuit

38: differential inverter 40: divider

According to one aspect of the present invention for solving the above problems, a voltage controlled oscillation circuit suitable for a microcomputer phase locked loop: a voltage-current converter for outputting a stable current by forming a current mirror by receiving a control voltage from the outside; Wow; A reference voltage generator circuit for outputting a reference voltage initiated by the bootstrap circuit; A bias circuit which receives the current and the reference voltage and biases them to output them; It includes a differential inverter that determines the output frequency by maintaining a stable output voltage in response to the input voltage.

In a preferred embodiment of this aspect, the voltage-current converter comprises: a first OP amplifier having an externally input control voltage and a feedback voltage; A first P-channel MOS transistor having a power supply voltage connected to the drain terminal; A second P-channel MOS transistor connected to a source terminal of the first P-channel MOS transistor, a source terminal and a gate terminal of the first P-channel MOS transistor, and having a gate terminal grounded; A third N-channel MOS having a drain terminal connected to a source terminal of the second P-channel MOS transistor, a source terminal connected to a cathode terminal of the first comparator, and a gate terminal connected to an output terminal of the first OP amplifier A transistor; A first resistor (R1) having one end connected to the cathode terminal of the first OP amplifier and the other end grounded; The stable current is output in response to the control voltage.

In a preferred embodiment of this aspect, the reference voltage generator circuit comprises: a second resistor, one end of which is connected to a power supply voltage; A fourth N-channel MOS transistor connected to the power supply voltage at a drain terminal thereof and connected to the other end of the second resistor at a gate terminal thereof; A fifth N-channel MOS transistor having a drain terminal connected to the gate terminal of the fourth N-channel MOS transistor, a source terminal grounded, and a gate terminal connected to the drain terminal; A sixth P-channel MOS transistor connected to a drain terminal to the power supply voltage, and a source terminal connected to a source terminal of the fourth N-channel MOS transistor; A seventh N-channel MOS transistor having a drain terminal connected to the source terminal of the sixth P-channel MOS transistor and having a source terminal grounded; An eighth P-channel MOS transistor connected to a drain terminal to the power supply voltage, a gate terminal to a gate terminal of the sixth P-channel MOS transistor, and a source terminal to the gate terminal; A drain terminal is connected to the source terminal of the eighth P-channel MOS transistor, a source terminal is connected to the gate terminal of the seventh N-channel MOS transistor, and a gate terminal is connected to the drain terminal of the seventh N-channel MOS transistor A ninth N-channel MOS transistor; A third resistor having one end connected to the source terminal of the ninth N-channel MOS transistor and the other end grounded; A predetermined reference voltage is output from the source terminal of the ninth N-channel MOS transistor.

In a preferred embodiment of this aspect, the bias circuit comprises: a tenth P-channel MOS transistor having a drain terminal connected to a power supply voltage and a gate terminal connected to an output terminal of the voltage-current converter; An eleventh P-channel MOS transistor connected in series with the tenth P-channel MOS transistor and whose gate terminal is grounded; A twelfth P-channel MOS transistor having a drain terminal connected to a source terminal of the eleventh P-channel MOS transistor, and a gate terminal of which is grounded; A thirteenth P-channel MOS transistor having a gate terminal connected to the output terminal of the reference voltage and connected in parallel with the twelfth P-channel MOS transistor; A fourteenth N-channel MOS transistor having a drain terminal connected to the source terminal of the twelfth P-channel MOS transistor and whose source terminal is grounded; A fifteenth N-channel MOS transistor having a drain terminal connected to a source terminal of the thirteenth P-channel MOS transistor and whose source terminal is grounded; A second OP amplifier having an anode terminal connected to an output terminal of the reference voltage and a cathode terminal connected to a source terminal of the twelfth P-channel MOS transistor and outputting to a gate terminal of the fourteenth and fifteenth N-channel MOS transistors; Include.

In a preferred embodiment of this aspect, the differential inverter comprises: a sixteenth P-channel MOS transistor having a drain terminal connected to a power supply voltage and a gate terminal connected to an output terminal of the current; A seventeenth P-channel MOS transistor connected in series with the sixteenth P-channel MOS transistor and whose gate terminal is grounded; An eighteenth P-channel MOS transistor connected in series with the seventeenth P-channel MOS transistor and having a gate terminal connected to an input terminal; A nineteenth P-channel MOS transistor having a gate terminal connected to the input terminal and connected in parallel with the eighteenth P-channel MOS transistor; A twentieth N-channel MOS transistor connected in series with the eighteenth P-channel MOS transistor, a gate terminal connected to an output terminal of the second OP amplifier, a drain terminal connected to the output terminal, and a source terminal grounded; ; A twenty-first N-channel MOS transistor connected in series with the nineteenth P-channel MOS transistor, a gate terminal connected to an output terminal of the second OP amplifier, a drain terminal connected to an output terminal, and a source terminal grounded do.

Therefore, in the present invention, current mirrors are formed in the first and second transistors by applying a control voltage from the outside of the voltage-current converter and flowing the first resistor. The reference voltage generating circuit generates a predetermined reference voltage and supplies it to the bias circuit. The bias circuit then maintains a stable output voltage of the differential inverter. Therefore, a phase locked loop is used to output a low frequency clock signal at a frequency suitable for the original microcomputer.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

Fig. 1 shows the configuration of a PLL suitable for a microcomputer for CTV (Cable TV). The PLL is a circuit for synchronizing the output frequency Fout to the input frequency Fxtal and includes the novel voltage controlled oscillation circuit (VCO) 30 of the present invention. And a phase comparator 10, a low pass filter 20, and a divider 40.

Referring to the figure, the PLL divides an output frequency Fout into a feedback loop and outputs a desired frequency corresponding to the low input frequency.

For example, in a microcomputer for CTV, the input frequency is used to output a microcomputer clock of 10 MHz using 32.768 KHz. However, since the clock duty ratio of the microcomputer must be 50%, the output of the VCO is divided by two and used.

Therefore, the output frequency of the VCO should be 20 MHz, which is twice the clock frequency of the microcomputer. In order to generate this output frequency, the divider performs 610 division.

And since the VCO generates an output frequency by the level of the input voltage, the input voltage of the VCO generates a frequency of 20 MHz using a voltage between 0 and 5V.

Also, because the PLL generates the output frequency by the input frequency, the VCO must not have a frequency of 0 MHz at any input voltage. That is, it has a linear characteristic.

Specifically, referring to FIG. 2, the VCO 30 includes a voltage-current converter 32, a reference voltage generator circuit 34, a bias circuit 36, and a differential inverter 38.

The voltage-current converter 32 includes a first OP amplifier OP1 for inputting a control voltage Vcontrol input from the outside and a voltage fed back, and a first P-channel MOS transistor MP1 having a power supply voltage connected to a drain terminal. And a drain terminal connected to a source terminal of the first P-channel MOS transistor MP1, a source terminal and a gate terminal of the first P-channel MOS transistor MP1, and a second gate terminal of which is grounded. P-channel MOS transistor MP2 is included.

The drain terminal is connected to the source terminal of the second P-channel MOS transistor MP2, the source terminal is connected to the cathode terminal of the first OP amplifier OP1, and the first OP amplifier OP1 is connected to a gate terminal. And a third N-channel MOS transistor MN3 connected to the output terminal of the C1 and a first resistor R1 of which one end is connected to the cathode terminal of the first OP amplifier OP1 and the other end is grounded. The current flowing through the first resistor R1 becomes Vcontrol / R1. At this time, a wide swing current mirror is formed by the first and second P-channel MOS transistors MP1 and MP2.

Accordingly, the stable current Ib is output to the gate terminal of the first P-channel MOS transistor MP1 in response to the control voltage Vcontrol.

The reference voltage generator 34 has a second resistor R2 having one end applied to the power supply voltage, a power supply voltage applied to the drain terminal, and a gate terminal connected to the other end of the second resistor R2. A fourth N-channel MOS transistor MN4 and a fifth N-channel having a drain terminal connected to a gate terminal of the fourth N-channel MOS transistor MN4, a source terminal grounded, and a gate terminal connected to the drain terminal MOS transistor MN5.

And a sixth P-channel MOS transistor MP6 having a drain terminal accepting the power supply voltage, a source terminal connected to a source terminal of the fourth N-channel MOS transistor MN4, and a drain terminal having the sixth P-channel MOS transistor. A seventh N-channel MOS transistor MN7 is connected to the source terminal of (MP6) and the source terminal is grounded.

An eighth P-channel MOS transistor MP8 connected to a drain terminal thereof to the power supply voltage, a gate terminal connected to a gate terminal of the sixth P-channel MOS transistor MP6, and a source terminal connected to the gate terminal thereof; And a drain terminal is connected to a source terminal of the eighth P-channel MOS transistor MP8, a source terminal is connected to a gate terminal of the seventh N-channel MOS transistor MN7, and a gate terminal is connected to the seventh N-channel MOS. A ninth N-channel MOS transistor MN9 connected to the drain terminal of the transistor MN7 and a third resistor R3 having one end connected to the source terminal of the ninth N-channel MOS transistor MN9 and having the other end grounded thereto. Include.

Thus, a bootstrap reference voltage is started which is started up by the second resistor R2 and the fourth and fifth N-channel MOS transistors MN4 and MN5. That is, a predetermined reference voltage (0.8V) is output from the source terminal of the ninth N-channel MOS transistor MN9.

Subsequently, the bias circuit 36 includes a tenth P-channel MOS transistor MP10 having a drain terminal connected to a power supply voltage, a gate terminal connected to an output terminal of the voltage-current converter 32, and the tenth P channel. An eleventh P-channel MOS transistor MP11 connected in series with the MOS transistor MP10 and having a gate terminal grounded is included.

The drain terminal is connected to the source terminal of the eleventh P-channel MOS transistor MP11, the gate terminal is grounded to the twelfth P-channel MOS transistor MP12, and the gate terminal is connected to the output terminal of the reference voltage Vref. And a thirteenth P-channel MOS transistor MP13 connected in parallel with the twelfth P-channel MOS transistor MP12.

A drain terminal is connected to the source terminal of the twelfth P-channel MOS transistor MP12, and the source terminal is grounded. The fourteenth N-channel MOS transistor MN14 and the drain terminal are the thirteenth P-channel MOS transistor MP13. A 15 th N-channel MOS transistor MN15 and an anode terminal connected to a source terminal of the source terminal and grounded to the output terminal of the reference voltage Vref, and a cathode terminal of the twelfth P-channel MOS transistor MP12. And a second OP amplifier OP2 connected to the source terminals of the N-th transistors and output to the gate terminals of the fourteenth and fifteenth N-channel MOS transistors MN14 and MN15.

The differential inverter 38 has a sixteenth P-channel MOS transistor MP16 and a sixteenth P-channel MOS transistor MP16 having a drain terminal connected to a power supply voltage and a gate terminal connected to an output terminal of the stable current Ib. And a seventeenth P-channel MOS transistor MP17 connected in series with the gate terminal and a seventeenth P-channel MOS transistor MP17 connected in series with the gate terminal connected to the input terminal Vin. 18 P-channel MOS transistor MP18 is included.

The 19th P-channel MOS transistor MP19 connected in parallel with the 18th P-channel MOS transistor MP18 and the 18th P-channel MOS transistor MP18 are connected in series with a gate terminal as an input terminal Vin. And a twentieth N-channel MOS transistor MN20 and a gate terminal connected to an output terminal of the second OP amplifier OP2, a drain terminal connected to an output terminal Vout, and a source terminal grounded. A first terminal connected in series with a P-channel MOS transistor MP19, a gate terminal connected to an output terminal of the second OP amplifier OP2, a drain terminal connected to the output terminal Vout, and a source terminal grounded; 21 N-channel MOS transistor MN21 is included.

The stable current Ib converted by the voltage-current converter is supplied to the inside through the sixteenth P-channel MOS transistor MP16, thereby determining the output frequency Fout of the VCO circuit 30. . Subsequently, a time delay occurs until the output voltage Vout is inverted by the current Ib and the input voltage Vin supplied to the differential inverter 38. This delay is proportional to the output voltage of the load capacitance and inversely proportional to the stable current Ib.

In addition, the twentieth and twenty-first N-channel MOS transistors MN20 and MN21 are designed to operate in a triode region as an active resistor.

In addition, it is important to maintain the triode region. For this purpose, the voltage Vds between the drain terminal and the source terminal of the 20th and 21st N-channel MOS transistors MN20 and MN21 is maintained not to exceed 0.8V. . In the BIOS circuit 36, the active resistor of the differential inverter 38 maintains the triode region by using the reference voltage Vref of 0.8 V and the second OP amplifier OP2.

Therefore, according to the voltage controlled oscillation circuit 30, the voltage-current converter receives a control voltage Vcon from the outside to form a current mirror to output a stable current Ib. The reference voltage generator circuit then outputs a predetermined reference voltage Vref to be started-up. Subsequently, the bias circuit receives the current Ib and the reference voltage Vref, biases them, and outputs them, and the differential inverter receives the current Ib and the reference voltage Vref and inputs a voltage Vin. Outputs a voltage Vout having an appropriate frequency Fout.

According to the present invention described above, it is possible to effectively cope with the electromagnetic interference noise problem by lowering the clock frequency input by using a low frequency crystal oscillator and reducing the noise by the PLL circuit.

Claims (5)

In a voltage controlled oscillator circuit of a phase locked loop suitable for a microcomputer: A voltage-current converter 32 which receives a control voltage Vcnt from the outside and outputs a stable current Ib through a current mirror circuit; A reference voltage generator circuit 34 for outputting a predetermined reference voltage Vref; A bias circuit 36 which receives the current Ib and the reference voltage Vref and biases them to output them; And a differential inverter (38) for outputting a voltage (Vout) having a stable frequency in response to the input voltage (Vin). The method of claim 1, The voltage-current converter 32 is: A first OP amplifier OP1 having an externally input control voltage Vcnt; A first P-channel MOS transistor MP1 having a drain terminal connected to a power supply voltage Vdd; A second P-channel MOS having a drain terminal connected to the source terminal of the first P-channel MOS transistor MP1, a source terminal connected to the gate terminal of the first P-channel MOS transistor MP1, and whose gate terminal is grounded. A transistor MP2; A drain terminal is connected to the source terminal of the second P-channel MOS transistor MP2, the source terminal is connected to the cathode terminal of the first OP amplifier OP1, and the first OP amplifier OP1 is connected to a gate terminal. A third N-channel MOS transistor MN3 connected to an output terminal of the third N-channel MOS transistor MN3; And a first resistor (R1) having one end connected to the cathode terminal of the first OP amplifier (OP1) and grounded at the other end. The method of claim 1, The reference voltage generator circuit 34 is: A second resistor R2 having one end connected to a power supply voltage Vdd; A fourth N-channel MOS transistor (MN4) connected to a drain terminal thereof to the power supply voltage (Vdd) and to a gate terminal thereof to the other end of the second resistor (R2); A fifth N-channel MOS transistor MN5 having a drain terminal connected to the gate terminal of the fourth N-channel MOS transistor MN4, a source terminal being grounded, and a gate terminal connected to the drain terminal; A sixth P-channel MOS transistor (MP6) connected to a drain terminal to the power supply voltage and having a source terminal connected to a source terminal of the fourth N-channel MOS transistor (MN4); A seventh N-channel MOS transistor MN7 having a drain terminal connected to the source terminal of the sixth P-channel MOS transistor MP6 and whose source terminal is grounded; An eighth P-channel MOS transistor (MP8) having a drain terminal connected to the power supply voltage, a gate terminal connected to a gate terminal of the sixth P-channel MOS transistor (MP6), and a source terminal connected to the gate terminal; A drain terminal is connected to the source terminal of the eighth P-channel MOS transistor MP8, a source terminal is connected to the gate terminal of the seventh N-channel MOS transistor MN7, and a gate terminal is connected to the seventh N-channel MOS transistor. A ninth N-channel MOS transistor MN9 connected to the drain terminal of MN7; And a third resistor (R3) whose one end is connected to the source terminal of the ninth N-channel MOS transistor (MN9) and whose other end is grounded. The method of claim 1, The bias circuit 36 is: A tenth P-channel MOS transistor MP10 having a drain terminal connected to a power supply voltage and a gate terminal connected to a terminal for outputting a stable current Ib of the voltage-current converter 32; An eleventh P-channel MOS transistor (MP11) connected in series with the tenth P-channel MOS transistor (MP10) and whose gate terminal is grounded; A twelfth P-channel MOS transistor (MP12) having a drain terminal connected to the source terminal of the eleventh P-channel MOS transistor (MP11) and whose gate terminal is grounded; A thirteenth P-channel MOS transistor MP13 connected to an output terminal of the reference voltage Vref and connected in parallel with the twelfth P-channel MOS transistor MP12; A fourteenth N-channel MOS transistor MN14 having a drain terminal connected to a source terminal of the twelfth P-channel MOS transistor MP12 and whose source terminal is grounded; A fifteenth N-channel MOS transistor MN15 having a drain terminal connected to a source terminal of the thirteenth P-channel MOS transistor MP13 and whose source terminal is grounded; An anode terminal is connected to the output terminal of the reference voltage Vref, and a cathode terminal is connected to the source terminal of the twelfth P-channel MOS transistor MP12 so that the fourteenth and fifteenth N-channel MOS transistors MN14 and MN15 are connected. And a second OP amplifier (OP2) output to the gate terminal of the voltage controlled oscillation circuit. The method of claim 1, The differential inverter 38 is: A sixteenth P-channel MOS transistor MP16 having a drain terminal connected to a power supply voltage Vdd and a gate terminal connected to an output terminal of the stable current Ib; A seventeenth P-channel MOS transistor (MP17) connected in series with the sixteenth P-channel MOS transistor (MP16) and whose gate terminal is grounded; An eighteenth P-channel MOS transistor MP18 connected in series with the seventeenth P-channel MOS transistor MP17 and having a gate terminal connected to an input terminal Vin; A nineteenth P-channel MOS transistor (MP19) connected in parallel with the eighteenth P-channel MOS transistor (MP18) by connecting a gate terminal to the input terminal (Vin); The eighth P-channel MOS transistor MP18 is connected in series, a gate terminal is connected to an output terminal of the second OP amplifier OP2, a drain terminal is connected to an output terminal Vout, and a source terminal is grounded. A twentieth N-channel MOS transistor MN20; The 19th P-channel MOS transistor MP19 is connected in series, a gate terminal is connected to the output terminal of the second OP amplifier OP2, a drain terminal is connected to the output terminal Vout, and a source terminal is And a twenty-first N-channel MOS transistor (MN21) grounded.