KR19990015635A - Using shift register - Google Patents

Abstract

The disclosure relates to an apparatus for performing an interface between a computing system and SDRAM. This device is an address counter for receiving and storing the start address signal from the computing system, and a row / column address FIFO for receiving the starting address signal from the computing system and receiving and storing row / column address signals from the address counter. Transmission counter that resets at the beginning of address counter operation and outputs clock count value, Transmission capacity comparison unit comparing transmission amount input from operation system and count value input from transmission counter, Input read / write command signal from operation system The control signal generator generates a control signal by using the shift register after determining the read / write operation and receives the comparison signal from the transmission comparator, and from the row / column address FIFO according to the control signal of the control signal generator. MUX part and input which receive column address signal and output According to the control signal generation unit stores the data signal transmitted from a computing system / SDRAM to a data FIFO to transfer to the SDRAM / operation system.

Description

SDRAM interface device using shift register

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SDRAM interface device that uses a shift register to speed up data transfer between a computation system and a synchronomic DRAM (SDRAM).

SDRAMs are being developed to improve the functions of DRAMs, which are widely used, and systems using them are gradually increasing. In particular, since MPEG2 decoders are used as core components in digital satellite broadcast receivers, DVDs, and digital TVs, SDRAM is likely to be the next-generation memory of MPEG2 decoders. Also, when designing MPEG2 decoder using SDRAM, SDRAM interface device is used to make efficient operation between computation system and SDRAM. An example of this is shown in FIG. 1.

1 is a diagram illustrating a system to which an SDRAM interface device is applied. As shown, the SDRAM interface device 12 is located between the computing system 11 and the SDRAM 13. When the arithmetic system 11 wants to store data in or read data from the SDRAM 13, the arithmetic system 11 supplies signals such as a transfer amount, a start address, a read / write, and a clock necessary for operation. It generates and outputs to the SDRAM interface device 12. The SDRAM interface device 12 generates a signal of the SDRAM 13, that is, a row address strobe (nRAS), a column address strobe (nCAS), a clock, an address, a write enable (nWE), and a data signal according to an input signal. Output to the SDRAM 13. The SDRAM 13 stores or reads a desired amount of data according to the input signal and transmits the data to the SDRAM interface device 12. The data transferred to the SDRAM interface device 12 is also sent to the computing system 11.

2A and 2B are signal flow diagrams illustrating a write / read operation of the SDRAM 13 in FIG. 1. First, referring to FIG. 2A, the SDRAM interface device 12 receives a transfer address signal of desired data for reading and writing from the operation system 11 and writes data from the read / write signal received. Determine the purpose. Thus, the SDRAM interface device 12 lowers the nRAS signal at clock 1 and transmits a row address signal to the address (b). After that, the SDRAM interface device 12 drops the nCAS signal at clock 4 and transmits a column address to the address (b). In addition, at clock 4, the nWE signal is also lowered to inform the SDRAM 13 that the write operation is performed. At the same time, when data of the desired transfer amount to be written in the clock 4 starts to be transferred to the SDRAM 13, the SDRAM 13 automatically stores the received data sequentially from the start address.

Next, referring to FIG. 2B, the SDRAM interface device 12 receives the start address from the operation system 11 and receives a transfer amount signal of desired data for reading and reads data from the read / write signal received. It is for the purpose. Thus, the SDRAM interface device 12 lowers the nRAS signal at clock 1 and transmits a lower address signal to the address (b). After that, the SDRAM interface device 12 drops the nCAS signal at clock 4 and transmits the column address to the address (b). After that, when the clock reaches 7, the SDRAM 13 automatically reads data sequentially from the start address and transfers the data to the SDRAM interface device 12. This data is thus transmitted to the computing system 11. In addition, such a calculation system 11 generally expects to transfer a large amount of data in a short time, starting from a start address.

Accordingly, an object of the present invention is to provide an SDRAM interface device using a shift register that can perform an efficient operation in accordance with the expectation of such an operation system.

1 is a diagram illustrating a system to which an SDRAM interface device is applied;

2A-B are signal flow diagrams illustrating a write / read operation of the SDRAM in FIG. 1;

3 is a block diagram showing the configuration of an SDRAM interface device using a shift register according to the present invention;

4 is a diagram illustrating a shift register of a control signal generation unit;

5-6 illustrate a process of generating a write / read operation signal of a shift register;

7 is a view showing a process of generating a control signal during a write / read operation of a shift register.

Description of the main parts of the drawings

31: control signal generator 32: address counter

33, 34: raw / column address FIFO 35: musbu

36: Data FIFO 37: Transmission Counter

38: transmission amount comparison

A feature of the present invention for achieving the above object is in an apparatus for performing an interface between the operation system and the SDRAM, an address counter for receiving and storing a start address signal from the operation system, receiving the start address signal from the operation system, The low / column address FIFO, which receives and stores the low / column address signal from the address counter, the transfer counter which resets at the same time as the operation of the address counter and outputs the clock count value, the transfer amount received from the operation system and the transfer amount counter. Transmission comparison unit that compares count values, receives read / write command signals from arithmetic system to determine read / write operations, and receives a comparison signal from transmission comparison unit and then generates control signals using shift registers. Generator, control signal generator According to the control signal, the data is transmitted from the operation system / SDRAM according to the control signal of the MUX unit and the control signal generation unit to receive and output the low / column address signal from the low / column address FIFO, and to transmit the data to the SDRAM / computation system. It resides in an SDRAM interface device containing a FIFO.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram showing a configuration of an SDRAM interface device using a shift register according to the present invention.

The SDRSDRAM interface device includes a control signal generation section 31 for generating all control signals using a shift register and an address counter 32 for storing start addresses input from the computing system 11. Row / column address FIFOs 33 and 34 which receive and store a row / column address from the start address and the address counter 32 are connected to the output terminal of the address counter 32. The mux part 35 which receives the control signal from the control signal generation part 31 and selects and outputs the low / column address is connected to the output terminal of the row / column address FIFOs 33 and 34. The output terminal of the control signal generator 31 is connected with a data FIFO 36 for storing data transmitted from the operation system 11 or the SDRAM 13 in accordance with the control signal of the control signal generator 31.

In addition, the SDRAM interface apparatus includes a transfer amount comparing unit 38 for receiving a transfer amount input from the calculation system 11 and comparing it with a counter amount input from the transfer amount counter 37.

The operation of the SDRAM interface device configured as described above will be described.

The start address signal is input from the arithmetic system 11 of FIG. 1 to the address counter 32 and the row / column address FIFOs 33 and 34 of the SDRAM interface device. At this time, the throughput counter 37 is reset to a value of 0 and this value is transmitted to the throughput comparison unit 38. In addition, the transfer amount from the arithmetic system 11 is input to the transfer amount comparison unit 38 of the SDRAM interface device. The throughput comparison unit 37 compares this value with the value input from the throughput counter 37. The row / column address FIFOs 33 and 34 receive and store row / column addresses from the address counter 32, respectively.

After this operation is performed, the values of the address counter 32 and the throughput counter 37 increase every clock cycle. The transmission comparison unit 38 compares the value received from the transmission counter 37 with the transmission amount and notifies the control signal generation unit 31 when the two values are the same. Then, the increase of the address counter 32 and the transfer amount counter 37 is stopped.

The control signal generator 31 generates a control signal using a shift register in accordance with a signal of a read / write command input from the arithmetic system 11. An operation process of generating the control signal by the control signal generator 31 will be described with reference to FIGS. 4 to 6.

4 is a diagram illustrating a shift register of a control signal generation unit, and FIGS. 5-6 are views illustrating a generation process of a write / read operation signal of a shift register.

First, a write operation process of the SDRAM shown in FIG. 2A will be described with reference to FIGS. 4 through 6. Initially all values of the shift register of FIG. 4 are zero. Then, when the request signal is input from the operation system 11 to the SDRAM interface device 12, it is prepared to input 1 to the registers A, B, C, and Dout of FIG. At clock 1, the bits that are ready at clock 0 are input to the register. The signals of R0, C0, and W0 are output as nRAS, nCAS, and nWE signals, and at the same time, 1 is prepared for Dout (Fig. 5A). In clock 2, all registers are shifted by one bit to the left, and the value prepared for clock 1 is inputted to A, B, C, and Dout, 0 is input to A, B, and C, and 1 is input to Dout. Is prepared (FIG. 5B). Clock 3 performs the same operation as clock 2, and starting from clock 4, the shift register is shifted left by 1 bit, and a value of 0 is input to A, B, C, and Dout, respectively.

In this way, the control signal generator 31 of FIG. 3 outputs the signals of nRAS, nCAS, and nWE to the operation system 13. At this time, the mux unit 35 outputs the address signal input from the lower address FIFO 33 when the nRAS signal is a low level signal, and the column address FIFO 34 when the nCAS signal is a low level signal. Output the input address signal. In addition, when the valid data availability signal is at the low level, data transmitted from the computing system 11 and stored in the data FIFO 36 is transmitted to the SDRAM 13.

Next, the read operation of the SDRAM shown in FIG. 2B will be described with reference to FIGS. 4 through 6. Initially all values of the shift register of FIG. 4 are zero. Then, when the request signal is input from the operation system 11 to the SDRAM interface device 12, it is prepared to input 1 to the registers A, B, and Din of FIG. At clock 1, the bits that are ready at clock 0 are input to the register. The signals of R0, C0, and W0 are output as nRAS, nCAS, nWE signals, and at the same time, 1 is input to Din (Fig. 6A). In clock 2, all registers are shifted by one bit to the left, and the value prepared for clock 1 is input to A, B, C, and Din, 0 is input to A, B, and C, and 1 is input to Din. Is prepared (FIG. 6B). Clock 3 performs the same operation as that of clock 2. From clock 4, the shift register is shifted left by one bit, and a value of 0 is input to each of A, B, C, and Din.

In this way, the control signal generator 31 of FIG. 3 outputs the signals of nRAS, nCAS, and nWE to the SDRAM 13. At this time, the mux unit 35 outputs the address signal input from the lower address FIFO 33 when the nRAS signal is a low level signal, and the column address FIFO 34 when the nCAS signal is a low level signal. Output the input address signal. In addition, when the valid data availability signal is at the low level, the SDRAM 13 automatically transfers data to the data FIFO 36, and the transferred data is transferred to the calculation system 11. 7A-B show a process of generating a control signal for the above described write / read operation of the shift register.

As described above, the SDRAM interface apparatus can perform an efficient operation between the computation system and the SDRAM by simply generating a control signal using the shift register.

Claims (6)

An apparatus for performing an interface between a computing system and a synchronous DRAM (SDRAM), An address counter which receives and stores a start address signal from the computing system; A row / column address FIFO for receiving a start address signal from the computing system and receiving a row / column address signal from the address counter; A transmission amount counter which is reset at the beginning of the operation of the address counter and outputs a clock count value; A transmission amount comparing unit comparing a transmission amount input from the calculation system and a count value input from the transmission amount counter; A control signal generation unit configured to receive a read / write command signal from the operation system, determine a read / write operation, and generate a control signal after receiving a comparison signal from the throughput comparison unit; A mux unit for receiving and outputting a row / column address signal from the row / column address FIFO according to the control signal of the control signal generator; And And a data FIFO for storing the data transmitted from the operation system / SDRAM according to the control signal of the control signal generation unit and transmitting the data to the SDRAM / operation system. The SDRAM interface device according to claim 1, wherein the comparison signal is a signal generated when the transmission amount compared with the transmission comparison unit is equal to the count value. The SDRAM interface device of claim 1, wherein the control signal is a low address strobe (nRAS) signal, a column address strobe (nCAS) signal, a write enable (nWE) signal, and a valid data availability signal. 4. The SDRAM interface device according to claim 1 or 3, wherein said control signal is generated using a shift register. The SDRAM interface device of claim 1, wherein the mux unit outputs the lower address signal when the nRAS signal is at a low level, and outputs the column address signal when the nCAS signal is at a low level. . The SDRAM interface device of claim 1, wherein the data FIFO transfers data to the operation system / SDRAM when the valid data availability signal is at a low level.